SN74LVC162244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com FEATURES • • • • • • • • • • • Member of the Texas Instruments Widebus™ Family Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.4 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) DESCRIPTION/ORDERING INFORMATION SCAS758A – DECEMBER 2003 – REVISED OCTOBER 2005 DGG, DGV, OR DL PACKAGE (TOP VIEW) 1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC 4Y1 4Y2 GND 4Y3 4Y4 4OE 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 2OE 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 VCC 4A1 4A2 GND 4A3 4A4 3OE This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC162244A is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2005, Texas Instruments Incorporated SN74LVC162244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS758A – DECEMBER 2003 – REVISED OCTOBER 2005 ORDERING INFORMATION PACKAGE (1) TA FBGA – GRD FBGA – ZRD (Pb-free) SSOP – DL –40°C to 85°C 2 SN74LVC162244AZRDR SN74LVC162244ADL Tape and reel SN74LVC162244ADLR Tape and reel TVSOP – DGV Tape and reel VFBGA – ZQL (Pb-free) SN74LVC162244AGRDR Tube TSSOP – DGG VFBGA – GQL (1) Tape and reel ORDERABLE PART NUMBER Tape and reel SN74LVC162244ADGGR 74LVC162244ADGGRG4 SN74LVC162244ADGVR 74LVC162244ADGVRE4 SN74LVC162244AGQLR SN74LVC162244AZQLR TOP-SIDE MARKING LD2244A LVC162244A LVC162244A LD2244A LD2244A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. SN74LVC162244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS758A – DECEMBER 2003 – REVISED OCTOBER 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and undershoot. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. abc TERMINAL ASSIGNMENTS (1) (56-Ball GQL/ZQL Package) GQL OR ZQL PACKAGE (TOP VIEW) 1 2 3 4 5 6 A B C D E F G H J K abc 1 2 3 4 5 6 A 1OE NC NC NC NC 2OE B 1Y2 1Y1 GND GND 1A1 1A2 C 1Y4 1Y3 VCC VCC 1A3 1A4 D 2Y2 2Y1 GND GND 2A1 2A2 E 2Y4 2Y3 2A3 2A4 F 3Y1 3Y2 3A2 3A1 G 3Y3 3Y4 GND 3A4 3A3 H 4Y1 4Y2 VCC VCC 4A2 4A1 J 4Y3 4Y4 GND GND 4A4 4A3 K 4OE NC NC NC NC 3OE GND abc abc (1) NC - No internal connection GRD OR ZRD PACKAGE (TOP VIEW) 1 2 3 4 5 6 abc abc TERMINAL ASSIGNMENTS (1) (54-Ball GRD/ZRD Package) A 1 2 3 4 5 6 A 1Y1 NC 1OE 2OE NC 1A1 B 1Y3 1Y2 NC NC 1A2 1A3 C 2Y1 1Y4 VCC VCC 1A4 2A1 D 2Y3 2Y2 GND GND 2A2 2A3 E E 3Y1 2Y4 GND GND 2A4 3A1 F F 3Y3 3Y2 GND GND 3A2 3A3 G 4Y1 3Y4 VCC VCC 3A4 4A1 H 4Y3 4Y2 NC NC 4A2 4A3 J 4Y4 NC 4OE 3OE NC 4A4 B C D G H J (1) NC - No internal connection 3 SN74LVC162244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS758A – DECEMBER 2003 – REVISED OCTOBER 2005 FUNCTION TABLE (EACH 4-BIT BUFFER) INPUTS OE A OUTPUT Y L H H L L L H X Z LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 1 3OE 47 2 46 3 44 5 43 6 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 48 4OE 41 8 40 9 38 11 37 12 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 25 36 13 35 14 33 16 32 17 3Y2 3Y3 3Y4 24 30 19 29 20 27 22 26 23 Pin numbers shown are for the DGG, DGV, and DL packages. 4 3Y1 4Y1 4Y2 4Y3 4Y4 SN74LVC162244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS758A – DECEMBER 2003 – REVISED OCTOBER 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through each VCC or GND θJA Package thermal impedance (4) DGG package 70 DGV package 58 DL package 63 GQL/ZQL package 42 GRD/ZRD package Tstg (1) (2) (3) (4) Storage temperature range V °C/W 36 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage VIH High-level input voltage Operating Data retention only VCC = 1.65 V to 1.95 V MIN MAX 1.65 3.6 1.5 Low-level input voltage VI 1.7 VCC = 2.7 V to 3.6 V 2 VO Output voltage IOH High-level output current 0.35 × VCC 0.7 VCC = 2.7 V to 3.6 V 0.8 0 5.5 High or low state 0 VCC High-impedance state 0 5.5 VCC = 1.65 V –2 VCC = 2.3 V –4 VCC = 2.7 V –8 VCC = 3 V IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature V V V mA –12 VCC = 1.65 V 2 VCC = 2.3 V 4 VCC = 2.7 V 8 VCC = 3 V (1) V VCC = 2.3 V to 2.7 V Input voltage V 0.65 × VCC VCC = 2.3 V to 2.7 V VCC = 1.65 V to 1.95 V VIL UNIT mA 12 –40 10 ns/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5 SN74LVC162244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS758A – DECEMBER 2003 – REVISED OCTOBER 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –100 µA 1.65 V to 3.6 V IOH = –2 mA VOH II 1.2 2.3 V 1.7 2.7 V 2.2 IOH = –6 mA 3V 2.4 IOH = –8 mA 2.7 V 2 IOH = –12 mA 3V 2 IOL = 100 µA 1.65 V to 3.6 V 0.2 1.65 V 0.45 2.3 V 0.7 IOH = –4 mA IOL = 4 mA UNIT VCC – 0.2 V 2.7 V 0.4 IOL = 6 mA 3V 0.55 IOL = 8 mA 2.7 V 0.6 IOL = 12 mA 3V 0.8 3.6 V ±5 µA VI = 0 to 5.5 V V Ioff VI or VO = 5.5 V 0 ±10 µA IOZ VO = 0 to 5.5 V 3.6 V ±10 µA ICC ∆ICC (1) (2) TYP (1) MAX 1.65 V IOL = 2 mA VOL MIN VI = VCC or GND IO = 0 3.6 V ≤ VI ≤ 5.5 V (2) One input at VCC – 0.6 V, 20 3.6 V Other inputs at VCC or GND 20 2.7 V to 3.6 V 500 µA µA Ci VI = VCC or GND 3.3 V 5.5 pF Co VO = VCC or GND 3.3 V 6 pF All typical values are at VCC = 3.3 V, TA = 25°C. This applies in the disabled state only. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A Y ten OE Y tdis OE Y PARAMETER VCC = 1.8 V ± 0.15 V MIN VCC = 2.5 V ± 0.2 V VCC = 2.7 V VCC = 3.3 V ± 0.3 V UNIT MAX MIN MAX MIN MAX MIN MAX 1.5 6 1 4.3 1 5.6 1.1 4.4 ns 1.5 7.3 1 5 1 6.9 1 5.5 ns 1.5 8.9 1 5.5 1 6.8 1.8 6.3 ns Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER Cpd 6 Power dissipation capacitance per buffer/driver Outputs enabled Outputs disabled f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP 31 33 35 2 3 4 UNIT pF SN74LVC162244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS758A – DECEMBER 2003 – REVISED OCTOBER 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 7 PACKAGE OPTION ADDENDUM www.ti.com 6-Aug-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74LVC162244ADGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVC162244ADGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVC162244ADGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVC162244ADGVRG4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVC162244ADLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC162244ADGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC162244ADGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC162244ADL ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC162244ADLG4 ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC162244ADLR ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC162244AGQLR NRND BGA MI CROSTA R JUNI OR GQL 56 1000 SNPB Level-1-240C-UNLIM SN74LVC162244AZQLR ACTIVE BGA MI CROSTA R JUNI OR ZQL 56 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TBD Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 6-Aug-2007 accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVC162244ADGGR DGG 48 SITE 41 330 24 8.6 15.8 1.8 12 24 Q1 SN74LVC162244ADGVR DGV 48 SITE 41 330 24 6.8 10.1 1.6 12 24 Q1 SN74LVC162244ADLR DL 48 SITE 41 330 32 11.35 16.2 3.1 16 32 Q1 SN74LVC162244AGQLR GQL 56 SITE 32 330 16 4.8 7.3 1.45 8 16 Q1 SN74LVC162244AZQLR ZQL 56 SITE 32 330 16 4.8 7.3 1.45 8 16 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74LVC162244ADGGR DGG 48 SITE 41 346.0 346.0 41.0 SN74LVC162244ADGVR DGV 48 SITE 41 346.0 346.0 41.0 SN74LVC162244ADLR DL 48 SITE 41 346.0 346.0 49.0 SN74LVC162244AGQLR GQL 56 SITE 32 346.0 346.0 33.0 SN74LVC162244AZQLR ZQL 56 SITE 32 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. 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