Revised February 2005 74LVTH125 Low Voltage Quad Buffer with 3-STATE Outputs General Description Features The LVTH125 contains four independent non-inverting buffers with 3-STATE outputs. ■ Input and output interface capability to systems at 5V VCC These buffers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH125 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ Outputs source/sink 32 mA/64 mA ■ Functionally compatible with the 74 series 125 ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V Ordering Code: Order Number Package Package Description Number 74LVTH125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVTH125SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVTH125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVTH125MTCX_NL (Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDED J-STD-020B). Device available in Tape and Reel only. © 2005 Fairchild Semiconductor Corporation DS012011 www.fairchildsemi.com 74LVTH125 Low Voltage Quad Buffer with 3-STATE Outputs October 1998 74LVTH125 Connection Diagram Logic Symbol IEEE/IEC Truth Table Inputs Pin Descriptions Pin Names Description An, Bn Inputs On 3-STATE Outputs www.fairchildsemi.com Bn L L L L H H H X Z H HIGH Voltage Level L LOW Voltage Level X Immaterial Z HIGH Impedance 2 Output An On Symbol Parameter VCC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current Value 0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 50 50 ICC DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature Conditions Units V V Output in 3-STATE V Output in HIGH or LOW State (Note 3) VI GND mA VO GND mA 64 VO ! VCC Output at HIGH State 128 VO ! VCC Output at LOW State r64 r128 65 to 150 mA mA mA qC Recommended Operating Conditions Symbol Parameter Min Max 2.7 3.6 V 0 5.5 V HIGH Level Output Current 32 mA LOW Level Output Current 64 mA VCC Supply Voltage VI Input Voltage IOH IOL TA Free-Air Operating Temperature 't/'V Input Edge Rate, VIN 0.8V – 2.0V, VCC 3.0V Units 40 85 qC 0 10 ns/V Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed. 3 www.fairchildsemi.com 74LVTH125 Absolute Maximum Ratings(Note 2) 74LVTH125 DC Electrical Characteristics Symbol TA 40qC to 85qC VCC (V) Parameter Min Typ Max Units Conditions (Note 4) 1.2 VIK Input Clamp Diode Voltage VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC 0.2 2.7 2.4 3.0 2.0 VOL 2.7 Output LOW Voltage 2.0 0.8 32 mA IOL 100 PA IOL 24 mA IOL 16 mA 32 mA 3.0 0.5 IOL 3.0 0.55 IOL II Input Current V 75 PA 75 500 PA 500 Current to Change State Power up/down 3-STATE 8 mA IOH 0.4 3.0 Output Current 100 PA IOH 0.5 Bushold Input Over-Drive IPU/PD IOH V 3.0 II(OD) Power Off Leakage Current VO t VCC 0.1V 2.7 3.0 IOFF V 0.2 Bushold Input Minimum Drive Data Pins II VO d 0.1V or 2.7 II(HOLD) Control Pins 18 mA V V 64 mA VI 0.8V VI 2.0V (Note 5) (Note 6) 3.6 10 VI 5.5V 3.6 r1 VI 0V or VCC VI 0V VI VCC PA 5 3.6 1 0 r100 PA 0–1.5V r100 PA 0V d VI or VO d 5.5V VO VI 0.5V to 3.0V GND or VCC IOZL 3-STATE Output Leakage Current 3.6 5 PA VO 0.5V IOZH 3-STATE Output Leakage Current 3.6 5 PA VO 3.0V IOZH 3-STATE Output Leakage Current 3.6 10 PA VCC VO d 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ Power Supply Current 3.6 0.19 mA VCC d VO d 5.5V 'ICC Increase in Power Supply Current 3.6 0.2 mA One Input at V CC 0.6V Outputs Disabled (Note 7) Other Inputs at V CC or GND Note 4: All typical values are at VCC 3.3V, TA 25qC. Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol Parameter (Note 8) TA VCC (V) Min 25qC Typ Units Max Conditions CL 50 pF, RL VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 9) VOLV Quiet Output Minimum Dynamic VOL 3.3 0.8 V (Note 9) Note 8: Characterized in SOIC package. Guaranteed parameter, but not tested. Note 9: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW. www.fairchildsemi.com 4 500: TA CL Symbol Parameter 40qC to 85qC 50 pF, RL 3.3V r 0.3V VCC Min Typ 500: VCC 2.7V Max Min Max 1.0 3.5 1.0 4.5 1.0 3.9 1.0 4.9 1.0 4.0 1.0 5.5 1.1 4.0 1.1 5.4 1.5 4.5 1.5 5.7 1.3 4.5 1.3 4.0 Units (Note 10) tPLH Propagation Delay Data to Output tPHL tPZH Output Enable Time tPZL Output Disable Time tPHZ tPLZ tOSHL Output to Output Skew tOSLH (Note 11) Note 10: All typical values are at VCC 3.3V, TA 1.0 ns ns ns 1.0 ns 25qC. Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance Symbol (Note 12) Parameter Conditions CIN Input Capacitance VCC 0V, VI COUT Output Capacitance VCC 3.0V, VO Note 12: Capacitance is measured at frequency f 0V or VCC 0V or VCC Typical Units 4 pF 8 pF 1 MHz, per MIL-STD-883B, Method 3012. 5 www.fairchildsemi.com 74LVTH125 AC Electrical Characteristics 74LVTH125 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A www.fairchildsemi.com 6 74LVTH125 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 7 www.fairchildsemi.com 74LVTH125 Low Voltage Quad Buffer with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8