Revised May 2002 74LVXZ161284 Low Voltage IEEE 161284 Translating Transceiver with Power-Up Protection General Description Features The LVXZ161284 contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The device supports the IEEE 1284 standard and is intended to be used in an Extended Capabilities Port mode (ECP). The pinout allows for easy connection from the Peripheral (A-side) to the Host (cable side). ■ Supports IEEE 1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals Outputs on the cable side can be configured to be either open drain or high drive (± 14 mA) and are connected to a separate power supply pin (VCC-Cable) that allows these outputs to be driven by a higher supply voltage than the A-side. The pull-up and pull-down series termination resistance of these outputs on the cable side is optimized to drive an external cable. In addition, the C inputs and the B and Y outputs on the cable side contain internal pull-up resistors connected to the VCC-Cable supply to provide proper input termination and pull-ups for open drain output mode. Outputs on the Peripheral side are standard low-drive CMOS outputs designed to interface with 3V logic. The DIR input controls data flow on the A1–A8/B1–B8 transceiver pins. ■ Translation capability allows outputs on the cable side to interface with 5V signals ■ All inputs have hysteresis to provide noise margin ■ B and Y output resistance optimized to drive external cable ■ B and Y outputs in high impedance mode during power down ■ C inputs and B, Y outputs on cable side have internal 1.4 kΩ pull-up resistors ■ Flow-through pin configuration allows easy interface between the “Peripheral and Host” ■ Replaces the function of two (2) 74ACT1284 devices ■ Power-up protection prevents errors when the printer is powered on but no valid signal is at the input pins (A9 - A13). This device also has an added power-up protection feature which forces the Y outputs (Y9 - Y13) to a high state after power-on until one of the associated inputs (A9 - A13) goes HIGH. When an associated input (A9 - A13) goes HIGH, all Y outputs (Y9 - Y13) are activated. Ordering Code Order Number Package Number 74LVXZ161284MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [RAIL] 74LVXZ161284MEX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 74LVXZ161284MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [RAIL] 74LVXZ161284MTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] Package Description © 2002 Fairchild Semiconductor Corporation DS500729 www.fairchildsemi.com 74LVXZ161284 Low Voltage IEEE 161284 Translating Transceiver with Power-Up Protection May 2002 74LVXZ161284 Logic Symbol Connection Diagram Pin Descriptions Pin Names HD Description High Drive Enable Input (Active HIGH) DIR Direction Control Input A1–A8 Inputs or Outputs B1–B8 Inputs or Outputs A9–A13 Inputs Y9–Y13 Outputs A14–A17 Outputs C14–C17 Inputs PLHIN Peripheral Logic HIGH Input PLH Peripheral Logic HIGH Output HLHIN Host Logic HIGH Input HLH Host Logic HIGH Output Truth Table Inputs Outputs DIR HD L L B1–B8 Data to A1–A8, and A9–A13 Data to Y9–Y13 (Note 1) C14–C17 Data to A14–A17 PLH Open Drain Mode L H B1–B8 Data to A1–A8, and A9–A13 Data to Y9–Y13 C14–C17 Data to A14–A17 H L A1–A8 Data to B1–B8 (Note 2) A9–A13 Data to Y9–Y13 (Note 1) C14–C17 Data to A14–A17 PLH Open Drain Mode H H A1–A8 Data to B1–B8 A9–A13 Data to Y9–Y13 C14–C17 Data to A14–A17 Note 1: Y9–Y13 Open Drain Outputs with 1.4 kΩ pullups Note 2: B1–B8 Open Drain Outputs with 1.4 kΩ pullups www.fairchildsemi.com 2 74LVXZ161284 Logic Diagrams Input Detection Circuit FIGURE 1. Input Detection Circuit Timing 3 www.fairchildsemi.com 74LVXZ161284 Absolute Maximum Ratings(Note 3) Recommended Operating Conditions Supply Voltage VCC −0.5V to +4.6V VCC—Cable −0.5V to +7.0V Supply Voltage VCC—Cable Must Be ≥ VCC Input Voltage (VI)—(Note 4) A1–A13, PLHIN, DIR, HD −0.5V to VCC + 0.5V B1–B8, C14–C17, HLHIN −0.5V to +5.5V (DC) B1–B8, C14–C17, HLHIN −2.0V to +7.0V* VCC 3.0V to 3.6V VCC—Cable 3.0V to 5.5V DC Input Voltage (VI) 0V to VCC Open Drain Voltage (VO) 0V to 5.5V −40°C to +85°C Operating Temperature (TA) *40 ns Transient Output Voltage (VO) A1–A8, A14–A17, HLH −0.5V to VCC +0.5V B1–B8, Y9–Y13, PLH −0.5V to +5.5V (DC) −2.0V to +7.0V* B1–B8, Y9–Y13, PLH *40 ns Transient DC Output Current (IO) A1–A8, HLH ±25 mA B1–B8, Y9–Y13 ±50 mA PLH (Output LOW) 84 mA PLH (Output HIGH) −50 mA Input Diode Current (IIK)—(Note 4) DIR, HD, A9–A13, PLH, HLH, C14–C17 −20 mA Output Diode Current (IOK) A1–A8, A14–A17, HLH ±50 mA B1–B8, Y9–Y13, PLH −50 mA DC Continuous VCC or Ground Current ±200 mA Note 3: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Fairchild does not recommend operation outside the databook specifications. −65°C to +150°C Storage Temperature ESD Human Body Model Note 4: Either voltage limit or current limit is sufficient to protect inputs. 4000V Machine Model 200V Charged Device Model 2000V DC Electrical Characteristics Symbol Parameter VCC (V) VCC—Cable (V) TA = 0°C TA = −40°C to +70°C to +85°C Units Conditions Guaranteed Limits VIK Input Clamp 3.0 3.0 −1.2 −1.2 V Ii = −18 mA Diode Voltage VIH VIL ∆VT VOH Minimum An, Bn, PLHIN, DIR, HD 3.0–3.6 3.0–5.5 2.0 2.0 HIGH Level Cn 3.0–3.6 3.0–5.5 2.3 2.3 Input Voltage HLHIN 3.0–3.6 3.0–5.5 2.6 2.6 V Maximum An, Bn, PLHIN, DIR, HD 3.0–3.6 3.0–5.5 0.8 0.8 LOW Level Cn 3.0–3.6 3.0–5.5 0.8 0.8 Input Voltage HLHIN 3.0–3.6 3.0–5.5 1.6 1.6 Minimum Input An, Bn, PLHIN, DIR, HD 3.3 5.0 0.4 0.4 Hysteresis Cn 3.3 5.0 0.8 0.8 HLHIN 3.3 5.0 0.2 0.2 An, HLH 3.0 3.0 2.8 2.8 IOH = −50 µA 3.0 3.0 2.4 2.4 IOH = −4 mA Minimum HIGH Level Output Voltage www.fairchildsemi.com V VT+ – VT− V VT+ – VT− VT+ – VT− 3.0 3.0 2.0 2.0 3.0 4.5 2.23 2.23 IOH = −14 mA PLH 3.15 3.15 3.1 3.1 IOH = −500 µA 4 V IOH = −14 mA Bn, Yn Bn, Yn Symbol Parameter (Continued) VCC (V) VCC—Cable (V) TA = 0°C TA = −40°C to +70°C to +85°C Units Conditions Guaranteed Limits VOL Maximum LOW An, HLH Level Output Voltage RD Maximum Output IIH IOZL IOZPU IOZPD IOFF IOFF 3.0 0.8 0.8 3.0 4.5 0.77 0.77 PLH 3.0 3.0 0.85 0.95 IOL = 84 mA PLH 3.0 4.5 0.8 0.9 IOL = 84 mA B1 - B8, Y9 -Y13 3.3 3.3 60 60 3.3 5.0 55 55 B1 - B8, Y9 - Y13 3.3 3.3 30 30 3.3 5.0 35 35 B1 - B8, Y9 - Y13, 3.3 3.3 1650 1650 3.3 5.0 1650 1650 Minimum Pull-Up B1 -B8, Y9 - Y13 3.3 3.3 1150 1150 Resistance C14 - C17 3.3 5.0 1150 1150 3.6 3.6 1.0 1.0 Maximum Input A9 - A13, PLHIN, Current in HD, DIR, HLHIN C14 - C17 3.6 3.6 50.0 50.0 C14 -C17 3.6 5.5 100 100 3.6 3.6 −1.0 −1.0 Maximum Input A9 - A13, PLHIN, Current in HD, DIR, HLHIN C14 - C17 3.6 3.6 −3.5 −3.5 C14 - C17 3.6 5.5 −5.0 −5.0 Maximum Output A1 - A 8 3.6 3.6 20 20 Disable Current B1 - B8 3.6 3.6 50 50 (HIGH) B1 - B8 3.6 5.5 100 100 Maximum A1 - A8 3.6 3.6 −20 −20 Output Disable B1 - B8 3.6 3.6 −3.5 −3.5 Current (LOW) B1 - B8 3.6 5.5 −5.0 −5.0 V IOL = 14 mA (Note 5)(Note 7) Ω (Note 5)(Note 7) Ω Ω VI = 3.6V µA VI = 3.6V VI = 5.5V µA VI = 0.0V mA VI = 0.0V VO = 3.6V µA VO = 3.6V VO = 5.5V µA mA VO = 0.0V Maximum Power-Up Y9 - Y13 0 to 1.5 0 to 1.5 350 350 µA VO = 5.5V Disable Current B1 - B8 (Note 8) (Note 8) −5 −5 mA VO = 0.0V Maximum Power-Down Y9 - Y13 0 to 1.5 0 to 1.5 350 350 µA VO = 5.5V Disable Current B1 - B8 (Note 8) (Note 8) −5 −5 mA VO = 0.0V Power Down B1 - B8, Y9 - Y13, Output Leakage PLH 0.0 0.0 100 100 µA VO = 5.5V 0.0 0.0 100 100 µA VI = 5.5V 0.0 0.0 250 250 µA (Note 6) 0.0 0.0 250 250 µA (Note 6) Power Down C14–C17, HLHIN Power Down Leakage to VCC IOFF—ICC2 Power Down Leakage to VCC—Cable ICC IOL = 14 mA 3.0 C14 - C17 Input Leakage IOFF—ICC IOL = 50 µA IOL = 4 mA Resistance LOW State IOZH 0.2 0.4 Maximum Pull-Up HIGH State IIL 0.2 0.4 Bn, Yn Impedance RP 3.0 3.0 Bn, Yn Impedance Minimum Output 3.0 3.0 Maximum Supply 3.6 3.6 45 45 mA VI = VCC or GND Current 3.6 5.5 70 70 mA VI = VCC or GND Note 5: Output impedance is measured with the output active LOW and active HIGH (HD = HIGH). Note 6: Power-down leakage to VCC or VCC—Cable is tested by simultaneously forcing all pins on the cable-side (B1–B8, Y9–Y13, PLH, C14–C17 and HLHIN) to 5.5V and measuring the resulting ICC or ICC—Cable. Note 7: This parameter is guaranteed but not tested, characterized only. Note 8: Connect all VCC pins and VCC-Cable pins when forcing voltage applied, DIR = HD = 0V. 5 www.fairchildsemi.com 74LVXZ161284 DC Electrical Characteristics 74LVXZ161284 AC Electrical Characteristics TA = 0°C to +70°C Symbol Parameter TA = −40°C to +85°C VCC = 3.0V–3.6V VCC = 3.0V–3.6V VCC—Cable = 3.0V–5.5V VCC—Cable = 3.0V–5.5V Units Figure Number Min Max Min Max tPHL A1–A8 to B1–B8 2.0 40.0 2.0 44.0 ns Figure 2 tPLH A1–A8 to B1–B8 2.0 40.0 2.0 44.0 ns Figure 3 tPHL B1–B8 to A1–A8 2.0 40.0 2.0 44.0 ns Figure 4 tPLH B1–B8 to A1–A8 2.0 40.0 2.0 44.0 ns Figure 4 tPHL A9–A13 to Y9–Y13 2.0 40.0 2.0 44.0 ns Figure 2 tPLH A9–A13 to Y9–Y13 2.0 40.0 2.0 44.0 ns Figure 3 tPHL C14–C17 to A14–A17 2.0 40.0 2.0 44.0 ns Figure 4 tPLH C14–C17 to A14–A17 2.0 40.0 2.0 44.0 ns Figure 4 tSKEW LH-LH or HL-HL 12.0 ns (Note 10) 10.0 tPHL PLHIN to PLH 2.0 40.0 2.0 44.0 ns Figure 2 tPLH PLHIN to PLH 2.0 40.0 2.0 44.0 ns Figure 3 tPHL HLHIN to HLH 2.0 40.0 2.0 44.0 ns Figure 4 tPLH HLHIN to HLH 2.0 40.0 2.0 44.0 ns Figure 4 tPHZ Output Disable Time 2.0 15.0 2.0 18.0 ns Figure 8 ns Figure 9 ns Figure 10 ns Figure 3 ns Figure 3 tPLZ DIR to A1–A8 2.0 15.0 2.0 18.0 tPZH Output Enable Time 2.0 50.0 2.0 50.0 tPZL DIR to A1–A8 2.0 50.0 2.0 50.0 tPHZ Output Disable Time 2.0 50.0 2.0 50.0 tPLZ DIR to B1–B8 2.0 50.0 2.0 50.0 tpEN Output Enable Time 2.0 25.0 2.0 28.0 tpDIS tpEN–tpDIS HD to B1–B8, Y9–Y13 2.0 25.0 2.0 28.0 Output Disable Time 2.0 25.0 2.0 28.0 HD to B1–B8, Y9–Y13 2.0 25.0 2.0 28.0 Output Enable- 10.0 12.0 ns V/ns Output Disable tSLEW Output Slew Rate tPLH B1–B8, Y9–Y13 tPHL tr, tf 0.05 0.40 0.05 0.40 0.05 0.40 0.05 0.40 tRISE and tFALL 120 120 B1–B8 (Note 9), 120 120 ns Y9–Y13 (Note 9) Note 9: Open Drain Note 10: tSKEW is measured for common edge output transitions and compares the measured propagation delay for a given path type: (i) A1–A8 to B1–B8, A9–A13 to Y9–Y13 (ii) B1–B8 to A1–A8 (iii) C14–C17 to A14–A17 Note 11: This parameter is guaranteed but not tested, characterized only. Capacitance Symbol Parameter Typ Units CIN Input Capacitance 3 pF VCC = 0.0V (HD, DIR, A9–A13, C14–C17, PLHIN and HLHIN) Conditions CI/O (Note 12) I/O Pin Capacitance 5 pF VCC = 3.3V Note 12: CI/O is measured at frequency = 1 MHz, per MIL-STD-883B, Method 3012 www.fairchildsemi.com 6 Figure 6 Figure 5 Figure 7 (Note 11) 74LVXZ161284 AC Loading and Waveforms Pulse Generator for all pulses: Rate ≤1.0 MHz; ZO ≤ 50Ω; tf ≤ 2.5 ns, tr ≤ 2.5 ns. FIGURE 2. Port A to B and A to Y Propagation Delay Waveforms FIGURE 3. Port A to B and A to Y Output Waveforms FIGURE 4. Port B to A, C to A and HLHin to HLH Propagation Delay Waveforms 7 www.fairchildsemi.com 74LVXZ161284 AC Loading and Waveforms (Continued) FIGURE 5. Port A to B and A to Y HL Slew Test Load and Waveforms FIGURE 6. Port A to B and A to Y LH Slew Test Load and Waveforms www.fairchildsemi.com 8 74LVXZ161284 AC Loading and Waveforms (Continued) tr = Output Rise Time, Open Drain tf = Output Fall Time, Open Drain FIGURE 7. Ports A to B and A to Y Rise and Fall Test Load and Waveforms for Open Drain Outputs FIGURE 8. tPHZ and tPLZ Test Load and Waveforms, DIR to A1–A8 9 www.fairchildsemi.com 74LVXZ161284 AC Loading and Waveforms (Continued) FIGURE 9. tPZH and tPZL Test Load and Waveforms, DIR to A1–A8 FIGURE 10. tPHZ and tPLZ Test Load and Waveforms DIR to B1–B8 www.fairchildsemi.com 10 74LVXZ161284 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 11 www.fairchildsemi.com 74LVXZ161284 Low Voltage IEEE 161284 Translating Transceiver with Power-Up Protection Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 12