74LVCZ161284A LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER WITH ERROR-FREE POWER-UP ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 9ns (MAX.) at VCC = 3V LOW POWER DISSIPATION: ICC=20µA (MAX) at VCC=3.6V TA=85°C TTL COMPATIBLE INPUTS VIH=2V (MIN) VIL=0.8(MAX) OPERATING VOLTAGE RANGE: VCC(OPR) = 3.0V to 3.6V A PORT HAVE STANDARD 4mA TOTEM POLE OUTPUT B PORT HIGH DRIVE SOURCE/SINK CAPABILITY OF 14mA AUTO POWER-UP FEATURE TO PREVENT PRINTER ERRORS SUPPORT IEEE STD 1284-I (LEVEL 1 TYPE) AND IEEE STD 1284-II (LEVEL 2 TYPE) FOR BIDIRECTIONAL PARALLEL COMMUNICATIONS BETWEEN PERSONAL COMPUTER ANT PRINTING PERIPHERALS TRANSLATION CAPABILITY ALLOW OUTPUTS ON CABLE SIDE TO INTERFACE WITH 5V SIGNAL PULL-UP RESISTOR INTEGRATED ON ALL OPEN-DRAIN OUTPUT ELIMINATE THE NEED FOR DISCRETE RESISTOR REPLACE THE FUNCTION OF TWO 74LVC1284 DEVICES TSSOP ORDER CODES PACKAGE TSSOP TUBE T&R 74LVCZ161284ATTR PIN CONNECTION DESCRIPTION The 74LVCZ161284A contains eight high speed non inverting bidirectional buffers and eleven control/status non-inverting buffers with open drain outputs fabricated in silicon gate C2MOS technology. It’s intended to provide a standard signaling method for a bi-direction parallel peripheral in an Extended Capabilities Port Mode (ECP). The HD (Active HIGH) input pin enables the Cable port to switch from Open Drain to a high drive totem pole output, capable of sourcing 14mA on all thirteen buffer and 84mA on PERI LOGIC OUTPUT buffer. The DIR input determines the direction of data flow on the bidirectional buffers. DIR (Active HIGH) enables data flow from A port to B port. DIR (Active LOW) enables data flow from B port to A port. The Y output (Y9-Y13) stay in the high state after power-on until an associated input A9-A13) goes high. When an associated input goes high, all Y outputs are active, and non July 2005 1/12 74LVCZ161284A inverting signals of the associated inputs are driven through Y outputs. This special feature prevents printer system errors caused by deasserting the BUSY signal in the cable at power-on. It is available in the commercial temperature range. LOGIC DIAGRAM NOTE A: NOTE B: NOTE C: The PMOS transistors prevent backdriving current from the signal pins to VCC/CABLE when VCC/CABLE is open or at GND. The PMOS transistor is turned off when the associated driver is in the low state. The PMOS transistor prevents backdriving current from the signal pins to VCC/CABLE when VCC/CABLE is open or at GND. Active input detection circuit forces Y9-Y13 to the low state after power-on until one of the A9-A13 goes high. See below. ACTIVE INPUT DETECTION CIRCUIT 2/12 74LVCZ161284A PIN DESCRIPTION PIN N° SYMBOL 1 2, 3, 4, 5, 6 8, 9, 11, 12, 13, 14, 16, 17 HD A9 to A13 A1 to A8 PLI Peripheral Logic Input 24 A14 to A17 HLO Host Logic Output 25 HLI 29, 28, 27, 26 C14 to C17 PLO 19 20, 21, 22, 23 30 41, 40, 38, 37, 36, 35, 33, 32 47, 46, 45, 44, 43 48 10, 15, 34, 39 NAME AND FUNCTION High Drive Enable Input Side A Input Side A Input or Output Side A Output Host Logic Input Side Cable Output Peripheral Logic Output Side Cable Input or Output Side Cable Output Direction Control Input Ground (0V) 7, 18 B1 to B8 Y9 to Y13 DIR GND VCC 31, 42 VCC/CABLE Cable Power Supply Positive Supply Voltage TRUTH TABLE INPUT OUTPUT DIR HD L L L H H L H H B1-B8 Data to A1-A8 A9-A13 Data to Y9-Y13 C14-C17 Data to A14-A17 A1-A8 Data to B1-B8 A9-A13 Data to Y9-Y13 C14-C17 Data to A14-A17 OUTPUT Y9-Y13 and PLO Open Drain Y9-Y13 and PLO Totem Pole B1-B8 Y9-Y13 and PLO Open Drain B1-B8 Y9-Y13 and PLO Totem Pole 3/12 74LVCZ161284A ABSOLUTE MAXIMUM RATINGS Symbol VCC VCCcable Parameter Value Unit Supply Voltage -0.5 to +4.6 V Cable Supply Voltage (must be ≥ VCC) -0.5 to +7.0 V -0.5 to +VCC + 0.5 V -0.5 to +5.5 V VIA DC Input Voltage A1-A13, PLIN, DIR, HDIN VIB DC Input Voltage B1-B8, C14-C17, HLIN VIBp DC Input Voltage B1-B8, C14-C17, HLIN (40ns transient) VOA DC Output Voltage A1-A8, A14-A17, HLIN -2 to +7 V -0.5 to +VCC + 0.5 V -0.5 to +5.5 V VOB DC Output Voltage B1-B8, Y9-Y13, PLIN VOBp DC Output Voltage B1-B8, Y9-Y13, PLIN (40ns transient) -2 to +7 V IIK DC Input Diode Current DIR, HD A9-A13, PLIN C14-C17 - 20 mA IOK DC Output Diode Current ± 50 mA A1-A8, A14-A17, HLIN B1-B8, Y9-Y13, PLIN IO DC Output Current A1-A8, HLIN B1-B8, Y9-Y13 PLO = LOW PLO = HIGH ICC or IGND DC VCC or Ground Current per Supply Pin Storage Temperature Tstg TL Lead Temperature (10 sec) - 50 ± 25 mA ± 50 84 -50 ± 200 mA -65 to +150 °C 300 °C Absolute Maximum Rating are those value beyond which damage to the device may occur. Functional operation under these condition is not implied RECOMMENDED OPERATING CONDITIONS Symbol VCC VCCcable 4/12 Parameter Value Unit Supply Voltage 3.0 to 3.6 V Cable Supply Voltage 3.0 to 5.5 V VI Input Voltage 0 to VCC V VO Open Drain Output Voltage 0 to 5.5 V Top Operating Temperature -40 to 85 °C 74LVCZ161284A DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH VOL II Parameter High Level Input Voltage Low Level Input Voltage IOZ IOFF Vhys ZO RP -40 to 85 °C VCCcable (V) Min. An, Bn, PLIN, DIR, HD Cn HLIN An, Bn, PLIN, DIR, HD 3.0 to 5.5 V 2.6 0.8 0.8 V 1.6 3.0 3.0 IO=-50µA 2.8 3.0 3.0 IO=-4mA 2.4 Bn, Yn 3.0 3.0 IO=-14mA 2.0 Bn, Yn 3.0 4.5 IO=-14mA 2.23 PL 3.15 3.15 IO=-500µA 3.1 3.0 3.0 IO=50µA Input Current Max. 2.3 3.0 to 3.6 High Level An, HL Output Voltage Low Level An, HL Output Voltage Unit 2 Cn HLIN V 0.2 3.0 3.0 IO=4mA 0.4 Bn, Yn 3.0 3.0 IO=14mA 0.8 Bn, Yn 3.0 4.5 IO=14mA 0.77 PL 3.0 3.0 IO=84mA 0.95 V PL 3.0 4.5 IO=84mA 0.90 Cn 3.6 3.6 VI = VCC 50 µA 3.6 3.6 VI=GND (Pull-up res) -3.5 mA 3.6 5.0 VI = VCC or GND ±1 µA 3.6 5.0 3.6 All input except B or C ICC VCC (V) Value Quiescent Supply Current VI = VCC IO=0 0.8 VI=GND (12xPull-up) 45 5.0 VO = VCC 20 µA 3.6 3.6 VO=GND (Pull-up res) -3.5 mA 3.6 5.0 VO = VCC or GND ± 20 µA mA High Impedance Output Leakage Current Bn Open Drain Y Output 3.6 3.6 VO=GND (Pull-up res) -3.5 mA Power Off Leakage Current Input Hysteresis B, Y output (to GND) 0 5.0 VI or VO = 0 to 7V 100 µA B, Y output (to VCC) 0 5.0 VI or VO = 0 to 7V 10 µA An, Bn, PLIN, DIR, HD 3.3 5.0 0.4 Cn HLIN 3.3 5.0 0.8 3.3 5.0 0.2 B1-B8, Y9-Y13 3.3 5.0 VB = VOH 30 55 Ω B1-B8, Y9-Y13, C14-C17 3.3 5.0 VB = VOH 1150 1650 Ω Output Impedance Pull-up Resistance A1-A8 V 5/12 74LVCZ161284A AC ELECTRICAL CHARACTERISTICS Test Condition Symbol tPLH tPHL Parameter Propagation Delay Time A1-A8 to B1-B8, A9-A13 to Y9-Y13 B1-B8 to A1-A8, C14-C17 to A14-A17 PLIN to PLOUT VCC (V) 3.0 to 3.6 Enable Delay Time DIR to A tPLZ tPHZ Disable Delay Time DIR to A tr tf Rise and Fall Time B1-B8, Y9-Y13 Open Drain HD to Bn, Y9-Y13 DIR to A HD to Bn, Y9-Y13 tOSLH tOSHL Output To Output Skew Time (note1, 2) -40 to 85 °C VCCcable (V) 3.0 to 5.5 HLIN to HLOUT tPZH tPZL Value 3.0 to 3.6 3.0 to 5.5 3.0 to 3.6 3.0 to 5.5 3.0 to 3.6 3.0 to 3.6 3.0 to 5.5 3.0 to 5.5 Unit Min. Max. RL=500Ω CL=50pF 1 7.5 ns RL=500Ω CL=50pF 1 9.0 ns RL=500Ω CL=50pF 1 7.0 ns RL=500Ω CL=50pF 1 11.0 ns RL=500Ω CL=50pF 1 12 ns RL=500Ω CL=50pF 1 8.5 ns RL=500Ω CL=50pF 1 8.5 ns RL=500Ω CL=50pF 1 8.5 ns RL=500Ω CL=50pF 1 8.5 ns RL=500Ω CL=50pF 1 120 ns RPULL-UP=500Ω CL=50pF 1 2 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn| 2) Parameter guaranteed by design CAPACITANCE CHARACTERISTICS Test Condition Symbol CIN CI/O 6/12 Parameter Control Input Capacitance (HD, DIR, A9-A13, C14-C17, PLIN, HLIN) I/O Pin Capacitance Value TA = 25 °C Unit VCC (V) VCC/CABLE (V) Open Open 4 pF 3.3 5.0 6 pF Min. Typ. Max. 74LVCZ161284A TEST CIRCUIT TEST tPHL (A1-A8 to B1-B8, A9-A13 to Y9-Y13, PLHIN to PLH) (see waveform 2) tPLH (A1-A8 to B1-B8, A9-A13 to Y9-Y13, PLHIN to PLH, HD to B1-B8, Y9-Y13, PLH) (see waveform 2) tPHL, tPLH (B1-B8 to A1-A8, C14-C17 to A14-A17, HLHIN to HLH) (see waveform 3) tr, tf (A1-A8 to B1-B8, A9-A13 to Y9-Y13) (see waveform 2) tPLZ (DIR to A1-A8) (see waveform 5) S1 S2 S3 Open VCC VCC Open GND GND Open GND GND Open VCC GND 6V GND GND tPHZ (DIR to A1-A8) (see waveform 5) Open GND GND tPZL (DIR to A1-A8) (see waveform 4) 1.4V GND GND tPZH (DIR to A1-A8) (see waveform 4) 4.4V GND GND tPLZ (DIR to B1-B8) (see waveform 5) 6V GND GND tPHZ (DIR to B1-B8) (see waveform 5) Open GND GND CL = 50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: ERROR-FREE CIRCUIT TIMING CHART (f=1MHz; 50% duty cycle) 7/12 74LVCZ161284A WAVEFORM 2: PROPAGATION DELAY INPUT An TO OUTPUT (f=1MHz; 50% duty cycle) WAVEFORM 3: PROPAGATION DELAY INPUT Bn TO OUTPUT (f=1MHz; 50% duty cycle) VMO = 50%VCC 8/12 74LVCZ161284A WAVEFORM 4: DATA TO OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) WAVEFORM 5: DIR TO OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 9/12 74LVCZ161284A TSSOP48 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. 1.2 A1 0.05 0.047 0.15 A2 MAX. 0.002 0.006 0.9 0.035 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 D 12.4 12.6 0.488 0.496 E 8.1 BSC E1 6.0 0.318 BSC 6.2 e 0.236 0.5 BSC 0.244 0.0197 BSC K 0° 8° 0° 8° L 0.45 0.75 0.018 0.030 A A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 7065588D 10/12 74LVCZ161284A Tape & Reel TSSOP48 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 30.4 0.519 1.197 Ao 8.7 8.9 0.343 0.350 Bo 13.1 13.3 0.516 0.524 Ko 1.5 1.7 0.059 0.067 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 11/12 74LVCZ161284A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 12/12