Data Sheet STEREO 2W AUDIO POWER AMPLIFIER AA4002 General Description Features The AA4002 is a monolithic stereo audio power amplifier including DC volume control, a selectable gain/bass boost, and stereo bridged audio power amplifiers, with the capability of producing 2W into 4Ω with THD+N less than 1%. The AA4002 is specially designed for Notebook PC, LCD monitor and portable media player. · · · · DC Volume Control Interface, 0dB to -78dB, 31 Steps System Beep Detect Very Low Power Consumption in Shutdown Mode, ISD=0.7µA Stereo Power Output for Speakers/Headphones with BTL Mode/SE Mode Selectable Internal/External Gain Bass Boost Pop Noise Suppression Circuit Thermal Shutdown Protection The AA4002 features low power consumption in shutdown mode, power amplifier and headphone mute for maximum system flexibility and performance. It also provides thermal shutdown protection. · · · · The AA4002 is available in TSSOP-28 with ExposedDAP package. Applications · · · · · Notebook PC LCD monitor Portable DVD Player Portable Media Player Digital Photo Frame TSSOP-28 with Exposed-DAP Figure 1. Package Type of AA4002 Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited 1 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER AA4002 Pin Configuration G Package (TSSOP-28 with Exposed-DAP) GND 1 28 RIGHT OUT+ SHUTDOWN 2 27 VDD GAIN SELECT 3 26 RIGHT OUT- MODE 4 25 RIGHT GAIN 2 MUTE 5 24 RIGHT GAIN 1 VDD 6 23 GND DC VOL 7 22 BYPASS GND 8 21 HP SENSE RIGHT DOCK 9 20 GND RIGHT IN 10 19 LEFT GAIN 1 BEEP IN 11 18 LEFT GAIN 2 LEFT IN 12 17 LEFT OUT- LEFT DOCK 13 16 VDD GND 14 15 LEFT OUT+ Figure 2. Pin Configuration of AA4002 Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited 2 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER AA4002 Pin Description Pin Number Pin Name Function 1, 8, 14, 20, 23 GND 2 SHUTDOWN Shutdown mode control signal input, place entire IC in shutdown mode when held high, IDD=0.7µA. 3 GAIN SELECT Gain select input pin, logic high will switch the amplifier to external gain mode, and logic low will switch to internal unity gain. 4 MODE Mode select input pin, fixed gain when logic L and gain adjustable mode when logic H. 5 MUTE Mute control input pin, active H. 6, 16, 27 VDD 7 DC VOL 9 RIGHT DOCK 10 RIGHT IN 11 BEEP IN Beep signal input pin. 12 LEFT IN Left channel audio input pin. 13 LEFT DOCK Left docking output pin. 15 LEFT OUT+ Left channel positive output pin. 17 LEFT OUT- Left channel negative output pin. 18 LEFT GAIN 2 Connect pin 2 of the external gain setting resistor for left channel. 19 LEFT GAIN 1 Connect pin 1 of the external gain setting resistor for left channel. 21 HP SENSE 22 BYPASS 24 RIGHT GAIN 1 Connect pin 1 of the external gain setting resistor for right channel. 25 RIGHT GAIN 2 Connect pin 2 of the external gain setting resistor for right channel. 26 RIGHT OUT- Right channel negative output pin. 28 RIGHT OUT+ Right channel positive output pin. Ground for circuitry. Supply voltage input pin. Volume control function input pin. Right docking output pin. Right channel audio input pin. Headphone sense control pin. Bypass pin. Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited 3 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER AA4002 Functional Block Diagram GAIN SELECT 3 Mute Mode HP Sense LEFT DOCK LEFT GAIN 1 13 LEFT GAIN 2 19 18 5 4 Mode Control 21 10kΩ 10kΩ _ 17 DC VOL 7 LEFT OUT- + 20kΩ 20kΩ LEFT IN 12 _ _ 15 + BEEP IN 11 Beep Detect Bias Volume Control 31 Steps Bias LEFT OUT+ + + 10 RIGHT IN _ + 28 _ SHUTDOWN RIGHT OUT+ 2 20kΩ VDD GND 20kΩ 6, 16, 27 1, 8, 14, 20, 23 + Power Management 26 _ RIGHT OUT- 10kΩ Bypass 22 Click and Pop Suppression Circuitry 10kΩ 24 9 RIGHT DOCK RIGHT GAIN 1 25 RIGHT GAIN 2 Figure 3. Functional Block Diagram of AA4002 Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited 4 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER AA4002 Truth Table for Logic Inputs (Note 1) Gain Sel Mode Headphone Sense Mute Shutdown Output Stage Set To DC Volume Output Stage Configuration 0 0 0 0 0 Internal Gain Fixed BTL 0 0 1 0 0 Internal Gain Fixed SE 0 1 0 0 0 Internal Gain Adjustable BTL 0 1 1 0 0 Internal Gain Adjustable SE 1 0 0 0 0 External Gain Fixed BTL 1 0 1 0 0 External Gain Fixed SE 1 1 0 0 0 External Gain Adjustable BTL 1 1 1 0 0 External Gain Adjustable SE X X X 1 0 Muted X Muted X X X X 1 Shutdown X X Note 1: If system beep is detected on the BEEP IN pin, the system beep will be passed through the bridged amplifier regardless of the logic of the MUTE and HP SENSE pins. Ordering Information AA4002 - Circuit Type E1: Lead Free Package TR: Tape and Reel Blank: Tube G: TSSOP-28 with Exposed-DAP Package Temperature Range TSSOP-28 with Exposed-DAP -40 to 85 ℃ Part Number Marking ID Packing Type AA4002G-E1 AA4002G-E1 Tube AA4002GTR-E1 AA4002G-E1 Tape & Reel BCD Semiconductor's Pb-free products, as designated with "E1" suffix in the part number, are RoHS compliant. Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited 5 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER AA4002 Absolute Maximum Ratings (Note 2) Parameter Symbol Value Unit Supply Voltage VDD 6.0 V Input Voltage VIN -0.3 to VDD + 0.3 V Power Dissipation PD Internally limited ESD 200 (Note 3) V TJ 150 oC TSTG -65 to 150 oC TL 260 oC RθJA (Note 4) 45 oC/W ESD (Machine Model) Operating Junction Temperature Storage Temperature Lead Temperature (Soldering 10s) Package Thermal Resistance Note 2: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operation is not implied. Exposure to "Absolute Maximum Ratings" for extended periods may affect device reliability. Note 3: This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Note 4: The Chip is soldered to 200mm2 copper of 1oz. with 12x0.5mm vias. Recommended Operating Conditions Parameter Supply Voltage Operating Temperature Symbol Min Max Unit VDD 2.7 5.5 V TA -40 85 oC Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited 6 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER AA4002 Electrical Characteristics (VDD=5V, TA=25oC, unless otherwise specified.) Parameter Symbol Conditions Min Typ Max Unit 5.5 V Standby and Logical Section 2.7 Supply Voltage VDD Quiescent Power Supply Current IDD VIN=0V, IOUT=0A 11 30 mA Shutdown Current ISD VSHUTDOWN=VDD 0.7 2.0 µA Headphone Sense High Input Voltage VIH Headphone Sense Low Input Voltage VIL (Mute, Shutdown, Mode, Select) High Input Voltage Gain VIH (Mute, Shutdown, Mode, Select) Low Input Voltage Gain 4 V 0.8 V V 3 VIL 1 V Volume Attenuators Section Attenuator Range CRANGE Mute Attenuation AM ± 0.75 VVOL=5V (DC), No load dB VVOL=0V (DC), BTL and SE Mode -75 dB VMUTE=5V, BTL Mode -78 dB VMUTE=5V, SE Mode -78 dB Single-ended (SE) Mode Section Output Power Total Harmonic Distortion + Noise POUT THD=1%, f=1kHz, RL=32Ω 85 THD=10%, f=1kHz, RL=32Ω 95 THD+N VOUT=1VRMS, f=1kHz, RL=10KΩ, AVD=1 mW 0.065 % Power Supply Rejection Ratio PSRR CB=1.0µF, f=120kHz, RL=32Ω, VRIPPLE=200mVRMS 58 dB Signal to Noise Ratio SNR POUT=75mW, RL=32Ω, A-Wtd Filter 102 dB f=1kHz, CB=1.0µF 65 dB Channel Separation BTL Mode Section Output Offset Voltage VOS ±5 VIN=0V, No load THD+N=1%, f=1kHz, RL=4Ω, LPF=22kHz Output Power POUT THD+N=1%, f=1kHz, RL=8Ω, THD+N=10%, f=1kHz, RL=8Ω, Total Harmonic Distortion + Noise Power Supply Rejection Ratio THD+N POUT=1.0W, RL=4Ω, AVD=2 20Hz<f<20kHz PSRR CB=1.0µF, f=120Hz, VRIPPLE=200mVRMS, RL=8Ω Sep. 2006 Rev. 1. 1 ± 50 mV 2 W 1.0 1.1 1.5 0.3 % 74 dB BCD Semiconductor Manufacturing Limited 7 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER AA4002 Electrical Characteristics (Continued) (VDD=5V, TA=25oC, unless otherwise specified.) Parameter Symbol Conditions Min Typ Max Unit SNR POUT=1.1W, RL=8Ω, A-Wtd Filter 93 dB CB=1.0µF, f=1kHz 70 dB BTL Mode Section (Continued) Signal to Noise Ratio Channel Separation Typical Performance Characteristics 10 10 VDD=5V BTL Mode RL=3.9Ω LPF=80KHz 1 THD+N (%) THD+N (%) VDD=5V SE Mode RL=33Ω LPF=80KHz 1KHz 20KHz 20Hz 1 0.1 1KHz (COUT=220µF) 20KHz (COUT=220µF) 20Hz (COUT=1000µF) 0.01 10 Output Power (mW) 0.1 100 100m Figure 4. THD+N vs. Output Power Figure 5. THD+N vs. Output Power 0 10 VDD=5V BTL Mode RL=8.2Ω LPF=80KHz 1 -20 1KHz 20KHz 20Hz PSRR (dB) THD+N (%) 1 Output Power (W) VDD=5V SE Mode CB=1.0µF VRIPPLE=200mVRMS -40 -60 -80 0.1 -100 10m 100m 1 20 Output Power (W) 100 1k 10k 20K Frequency (Hz) Figure 6. THD+N vs. Output Power Figure 7. PSRR vs. Frequency Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited 8 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER AA4002 Typical Performance Characteristics (Continued) 10 1 1 0.1 VDD=5V BTL Mode RL=3.9Ω Po=1.5W LPF=30KHz THD+N (%) THD+N (%) VDD=5V SE Mode RL=33Ω Po=75mW COUT=1000µF LPF=80KHz 0.1 20 100 1k 10k 100 20 160 160 SE Mode f=1KHz RL=33Ω THD=1% LPF=80KHz 100 80 60 40 20 2.5 SE Mode f=1KHz RL=33Ω THD=10% LPF=80KHz 140 Output Power (mW) Output Power (mW) 120 10k Figure 9. THD+N vs. Frequency Figure 8. THD+N vs. Frequency 140 1k Frequency (Hz) Frequency (Hz) 120 100 80 60 40 3.0 3.5 4.0 4.5 5.0 20 2.5 5.5 Supply Voltage (V) 3.0 3.5 4.0 4.5 5.0 5.5 Supply Voltage (V) Figure 10. Output Power vs. Supply Voltage Figure 11. Output Power vs. Supply Voltage Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited 9 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER AA4002 Typical Performance Characteristics (Continued) 2.2 1.8 Output Power (W) 1.4 2.0 1.8 Output Power (W) 1.6 BTL Mode RL=8.2Ω f=1KHz THD=1% 1.2 1.0 0.8 0.6 1.6 1.4 1.2 1.0 0.8 0.4 0.6 0.2 0.4 0.0 2.5 3.0 3.5 4.0 4.5 5.0 BTL Mode RL=8.2Ω f=1KHz THD=10% 0.2 2.5 5.5 3.0 4.5 5.0 5.5 Figure 13. Output Power vs. Power Supply Figure 12. Output Power vs. Supply Voltage 700 2.4 VDD=5V SE Mode f=1KHz LPF=80KHz 650 600 550 VDD=5V BTL Mode f=1KHz LPF=80KHz 2.2 2.0 1.8 500 THD+N=1% THD+N=10% 450 Output Power (W) Output Power (mW) 4.0 Supply Voltage (V) Supply Voltage (V) 400 350 300 250 200 1.4 1.2 1.0 0.8 0.6 100 0.4 50 THD+N=1% THD+N=10% 1.6 150 0 3.5 0.2 8.0 16.0 24.0 32.0 40.0 48.0 56.0 0.0 64.0 Load Resistance (Ω) 8.0 16.0 24.0 32.0 40.0 48.0 56.0 64.0 Load Resistance (Ω) Figure 15. Output Power vs. Load Resistance Figure 14. Output Power vs. Load Resistance Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited 10 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER AA4002 Typical Performance Characteristics (Continued) 0.26 1.8 VDD=5V SE Mode f=1KHz THD<1% LPF=80KHz Power Dissipation (W) 0.22 0.20 1.6 1.4 AA4002 RL=8Ω Power Dissipation (W) 0.24 0.18 0.16 0.14 0.12 AA4002 RL=33Ω 0.10 VDD=5V BTL Mode f=1KHz RL=3.9Ω 1.2 1.0 0.8 0.6 0.4 0.08 0.2 0.06 0.04 0.0 40.0m 80.0m 120.0m 160.0m 0.0 0.0 200.0m 0.5 1.0 Figure 16. Power Dissipation vs. Output Power 2.5 0 VIN=0mV IO=0mA -10 16 -20 14 Attenuation (dB) Supply Current (mA) 2.0 Figure 17. Power Dissipation vs. Output Power 20 18 1.5 Output Power (W) Output Power (W) 12 BTL Mode 10 8 SE Mode 6 -30 -40 -50 -60 4 -70 2 0 2.5 3.0 3.5 4.0 4.5 5.0 -80 0.0 5.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Volume Control Voltage (V) Supply Voltage (V) Figure 18. Supply Current vs. Supply Voltage Figure 19. Volume Control Characteristics Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited 11 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER AA4002 Typical Performance Characteristics (Continued) 12.0 -50 VDD=5V SE Mode RL=33Ω f=1KHz CB=1µF CBS=0.1µF 8.0 -60 6.0 CBS=0.22µF 4.0 -70 2.0 -80 20 CBS=0.068µF 10.0 Output Level (dB) Channel Separation (dB) -40 100 1k 0.0 20 10k Frequency (Hz) VDD=5V RL=8.2 Ω RI=RBS=RF=20KΩ 50 100 200 300 500 1K 2K 5K 10K 20K Frequency (Hz) Figure 20. Channel Separation vs. Frequency Figure 21. External Gain/Bass Boost Characteristics Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited 12 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Application Information 28, RPU=100k, RL=1.5k, DC voltage at HP_SENSE is about 75mV. AC signal equals output amplitude of OUT- through COUT, so signal at HP_SENSE node is 75mV DC plus AC signal. The maximum Peak-toPeak voltage at OUT- is not greater than VDD=5.0V supply voltage, so the positive maximum voltage of HP_SENSE node is not greater than 2.5V+75mV=2.575V, which can not reach HP_SENSE input high level minimum value (4.0V), there is no risk of mode switching between SE and BTL. SE/BTL Mode, HP_SENSE Pin The AA4002 can be operated in 2 types of output configurations, SE (Single-Ended) mode and BTL (Bridged-Tied-Load) mode, determined by HP_SENSE pin (pin 21) logic level. (Here is the discussion about left channel only, it also applies to right channel.) 10kΩ Left Out- 17 + 20kΩ OP1 HP_SENSE pin can also be connected to MCU I/O port, it is necessary to note that AA4002 still can drive headphone even in BTL mode because OUT- is always active whatever SE or BTL mode. COUT 220µF + 10kΩ _ RL 1.5kΩ 20kΩ Internal/External Gain, Gain SELECT Pin _ Bias + AA4002 The AA4002 provides 2 selectable feedback loops, Internal and External determined by SELECT pin (pin 3) logic level. Applying low level to SELECT pin, the AA4002 switches to internal feedback loop, OP1 works as unity gain. If applying high level to SELECT pin, external components are used as feedback loop, and the gain is expressed by formula below. Left Out+ 15 OP2 Figure 22. BTL Configuration in Left Channel If applying high level to pin 21, the output of OP2 unit is in high impedance, the chip operates in SE mode. There is no current loop between OUT+ and OUT-, also no power consumption. AVFB = When HP_SENSE pin is held low, OP2 unit is turned on, the chip operates in BTL mode. AC signal at OUT+ is -180o phase shift of OUT-. OP2 has fixed unity gain internally, so DC components (Bias voltage, approx 1/2 VDD) between OUT+, OUT- is canceled. There is no need for DC block capacitors in system. ( RBS // ZC BS ) + RF ..............................(1) RI Here ZCBS is the impedance of bass boost capacitor, ZCBS=1/2π*f*CBS. So AVFB approaches 2 points, AVFBLF at low frequency, AVFBHF at high frequency, expressed by formula 2 and 3. In BTL mode, voltage between speaker load is about 2 times that in SE mode, so there is 4 times output power compared to SE mode with same load. In SE mode, output audio signal rides on Bias voltage at OUT-, so it is necessary to use capacitor to block DC bias and couple AC signal. See Figure 28 typical application circuit. AVDLF = RBS + RF .............................................(2) RI AVFBHF = RF ........................................................(3) RI Bass Boost From above discussion, the AA4002 can improve gain of audio signal at low frequency, which is hard to listening for human ears relative to middle band (2kHz to 3kHz). The boost corner frequency is determined by formula 4. It is recommended to connect HP_SENSE to the control pin of headphone jack, illustrated in Figure 28. When headphone plug is not inserted, the voltage of HP_SENSE pin is determined by voltage divider formed by RPU, RL. For given resistors value in Figure Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited 13 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Application Information (Continued) AA4002 Table 1. Volume Attenuation vs. DC VOL Pin Voltage f BS = 1 2πRBS C BS ..............................................(4) VDD=5V Assuming RBS=RF=RI=20kΩ, CBS=0.068µF and fBS=117Hz, the bass boost characteristic is shown in Figure 21. Fixed Gain/Adjustable Gain Loop, MODE pin, DC Volume Control The AA4002 can be set in fixed gain or adjustable gain, according to applying high or low level to MODE pin (pin 4). Low level is for fixed gain, High level is for adjustable gain, which permits to change volume by applying various DC voltages to DC VOL pin (pin7). Table 1 shows the relationship of Volume Attenuation vs. the voltage of DC VOL pin. There are 31 steps from 0 to -78dB; step size is different for different volume control voltage, 1dB/step from 0dB to -6dB, 2dB/step from -6dB to -36dB, 3dB/step from -36dB to -47dB, 4dB/step from -47db to -51dB, 5dB/step from -51dB to -66dB, The last step is 12dB from -66dB to -78dB. Figure 23. Volume Attenuation vs. DC VOL Pin Voltage For example, increasing voltage applied to DC VOL pin from 3.437V (point B in Figure 23) to 3.562V (point D), gain will change one step from -4dB to -3dB (point F). Sep. 2006 Rev. 1. 1 Attenuation (dB) High Level (V) Low Level (V) 0 5 3.875 -1 3.937 3.750 -2 3.812 3.625 -3 3.687 3.500 -4 3.562 3.375 -5 3.437 3.250 -6 3.312 3.125 -8 3.187 3.000 -10 3.06 2.875 -12 2.937 2.750 -14 2.812 2.625 -16 2.687 2.500 -18 2.562 2.375 -20 2.437 2.250 -22 2.312 2.125 -24 2.187 2.000 -26 2.062 1.875 -28 1.937 1.750 -30 1.812 1.625 -32 1.687 1.500 -34 1.562 1.375 -36 1.437 1.250 -39 1.312 1.125 -42 1.187 1.000 -45 1.062 0.875 -47 0.937 0.750 -51 0.812 0.625 -56 0.687 0.500 -61 0.562 0.375 -66 0.437 0.250 -78 0.312 0 BCD Semiconductor Manufacturing Limited 14 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER fixed gain, ignoring MUTE and HP_SENSE pin logic level. For AA4002, VDETECT is about 2.8V. Beep signal passes through Left/Right channel input path, the gain under BTL load is only dependent on the ratio of RF(L/R) to RBEEP. Application Information (Continued) But, decreasing voltage from 3.562V (point F), gain does not change immediately, the change occurs at 3.5V (point E). There is a hysteresis which guarantees that the volume control is monotonic, with immunity against noise coupled from system. In above Table 1, the column of Low Level means the lower threshold voltage with the voltage of DC VOL varying from high to low, High Level column means the other upper threshold voltage DC VOL voltage varying from low to high. AVBEEP ( L / R ) = 2 ∗ When applying high level to MUTE pin (pin 5), the AA4002 will mute output stage stereo dock outputwhatever in BTL or SE mode. The AA4002 offers shutdown function which can further reduce power consumption. SHUTDOWN pin (pin 2) should be held low in normal operation. If applying high level to SHUTDOWN pin, the AA4002 will turn off internal bias circuits, enter into shutdown mode with very low quiescent current, 0.7µA Typ. MUTE, SHUTDOWN pin should be tied to high or low level to avoid undesired operation state. For input stages of Left/Right channel, input capacitors (CIL, CIR), are used to accommodate different DC level between input source and AA4002 bias voltage (about 1/2 VDD). Input capacitors (CIL, CIR) and input resistors (RIL, RIR) form first order High Pass Filters, which determine the corner frequency, f CI ( L / R ) = There are stereo amplifiers built-in AA4002 front-end input stages. It provide very low distortion audio monitor signal for line out, the pass-band gain is determined by external feedback resistors, RI ( L / R ) .................................(6) RBEEP CI, COUT, CB and CS (Power Supply Bypassing Capacitor) Selection Left/Right Dock Output RF ( L / R ) RF ( L / R ) For resistors value given in Figure 28, AVBEEP is about 0.2 (-14dB). If this feature is not used, connecting the capacitor (CBEEP) to ground, it is recommended removing two resistors (RBEEP, 200kΩ), to minimize crosstalk between left and right channel. Mute, Shutdown AVDOCK ( L / R ) = AA4002 1 ..........................(7) 2πRI ( L / R ) ∗ C I ( L / R ) For given values in Figure 28, RIL=RIR=20kΩ, CIL=CIR=0.33µF, the corner frequency of input stage is about 24Hz. .....................................(5) Similarly, for output stage in SE mode, output capacitor (COUT), and headphone load also form a first order High Pass Filter, and its cut-off frequency is determined by classic formula below. The dock output is also used as input source for backend amplifiers, so the gain of docking output (AVDOCK) will affect total loop gain. The function of COUT(L/R) (0.1µF) serial in Left/Right dock output is to remove DC bias. f CO ( L / R ) = Beep Detect 1 2πRHP ( L / R ) ∗ CO ( L / R ) ....................(8) For bypass capacitor (CB), the purpose is to filter internal bias noise, reduce harmonic distortion, and improve power supply rejection ratio performance. Tantalum or ceramic capacitor with low ESR is recommended, and is placed as close as possible to chip bypass pin in PCB layout. Both input and output BCD Semiconductor Manufacturing Limited Beep feature is used in Notebook PC system for alerting. If peak-to-peak voltage of beep signal applied to BEEP DETECT pin (pin 11) exceeds a certain voltage called detect voltage, the feature will be activated, then AA4002 will be forced at BTL mode with internal Sep. 2006 Rev. 1. 1 15 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER According to formulas above, it is easy to plot Amplitude-Frequency characteristic curve. The lower corner frequency is dependant on AVIN, AVOUT, Bass Boost feature relies on AVOUT. Application Information (Continued) signal ride on such reference voltage, the chip can not work until internal DC bias is set up completely. So the size of CB can also affect the chip start-up time, which is approx linearly proportional to the value of bypass capacitor. For AA4002, here are the start-up times for several typical capacitor values. Example VDD=5V, RL=8Ω, BTL configuration, desired output power each channel, PO=1.0W, THD+N ≤ 1%. Input signal, VIN=1.0VRMS from D-A converter. Table 2. CB vs. Start-up Time CB (µF) Start-up Time (ms) 0.47 300 1.0 600 2.2 1300 Step 1, To check if the chip can deliver 1W to 8Ω load with the limitation of THD+N ≤ 1%, VDD=5V by Figure 6, 15. Step 2, If yes, to calculate output voltage, . So total pass-band gain (ignoring Bass boost feature, low frequency attenuation caused by AC coupling capacitors, AVFB=1x.), For AA4002 power supply, it is better to use individual power source generated from voltage regulators split from video, digital circuit units in system. For bypassing capacitors, it is recommended to use one electrolytic capacitor of 4.7µF to 10µF in parallel with 0.1µF ceramic capacitor which is located close to the part. AVTOTAL=VOUT/VIN=2.83x. Step 3, AVIN=AVTOTAL/( AVFB*AVOUT )=2.83/(1*2)=1.415, RF(L/R)=AVIN*RI(L/R), assuming components values are given in Figure 28, just changing RF(L/R) to 20kΩ*1.415=28.3kΩ. Select the closest standard value 28kΩ. Setup Proper Gain, Design Example The total closed loop gain is determined by three individual units - input stage, feedback network and output stage. Optimizing CLICK/POP Noise Input stage, pass-band gain AVIN = RF ( L / R ) AA4002 The AA4002 includes a circuit to suppress CLICK/ POP noise during power up/down transition. In practical application, the chip can effectively suppress common mode signal including CLICK/POP noise in BTL configuration. In SE mode, decreasing the size of output capacitor (COUT) can minish POP noise, which can also affect low frequency response according to formula 8 above. Increasing bypass capacitor value (CB) can slower ramp of charge, prolong start-up time, mask most of transient noises before bias voltage is set-up. ...................................................(9) RI ( L / R ) Feedback network, Internal pass-band gain, AVFB=1, for external gain, see formula 1, 2, 3. Output stage, for BTL mode, AVOUT=2, for SE mode, AVOUT=1. So the total pass-band gain of AA4002, AVTOTAL is, Proper power on/off sequence can also optimize CLICK/POP noise. The recommended is shown in Figure 24. AVTOTAL = AVIN ∗ AVFB ∗ AVOUT ........................(10) Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited 16 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER Here Application Information (Continued) AA4002 TJMAX is maximum operating junction temperature 150oC, TA is ambient temperature, θJA is thermal resistance form junction to ambient. For G package (TSSOP-28 with exposed DAP), it is 45oC/W given in datasheet page 6. VDD(V) (pin6,16,27) Assuming TA is +25oC, the maximum allowed power dissipation PDMAX is about 2.78W according to formula 12. Mute(V) (pin5) There is the other formula about power dissipation drawn from application for each channel which is determined by supply voltage and load resistance. Shutdown(V) (pin2) 2 OFF STBY MUTE PLAY MUTE STBY 2 1) Power ON operation, enable mute, then enable shutdown; after VDD is stable, release shutdown first, then mute. If power dissipation calculated by application is larger than permissible by package, it is necessary to assemble additional heat sinking, or keep ambient temperature around the chip very low, or increasing load impedance, or decreasing power supply voltage. 2) Power OFF, enable mute, then enable shutdown; after VDD is discharged completely, release shutdown firstly, then mute. Here is an example, assuming VDD=5.0V, RL=4Ω, stereo in BTL mode, Efficiency, Power Dissipation and Thermal Consideration in Design PDBTLMAX = ........................................................(11) , for 2 channels, total power dissipation PDTOTAL=2* PDBTLMAX=2*1.266=2.53W, according to formula 13, the maxim ambient temperature is, 4VDD Here VP is peak voltage of output swing. TA = TJMAX − θ JA ∗ PDBTLMAX =150-45*2.53=36.2 oC Thermal dissipation becomes major concern when output power is close to 2W especially in BTL mode. The maximum power dissipation of package for AA4002 can be calculated by following equation. PDMAX = TJMAX − TA θ JA 2VDD 2 × 52 = = 1.266W 2 π RL 3.14 2 × 4 2 For Class-AB amplifier, Figure 11 is the basic equation of efficiency worked in BTL configuration, πVP PDBTLMAX 2V = 2DD (for BTL mode).................(14) π RL OFF Figure 24. Recommended Sequences for Power ON/OFF η= PDSEMAX V (for SE mode)....................(13) = DD 2π 2 RL That is to say, if user wants AA4002 can delivery maximum output power to 4Ω load, at VDD=5.0V, BTL mode, ambient temperature has to hold less than 36.2oC. When junction temperature exceeds about +165oC, thermal shutdown circuit built-in AA4002 ........................................(12) Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited 17 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER AA4002 and make sure to keep them contact well when soldering to PCB. See Figure 24. Application Information (Continued) will turn off output stage to limit total power dissipation. Recommended PCB Layout for AA4002 Using wide traces for power supply, output power to reduce losses caused by parasitic resistance is recommended, which can also help to release heat away from the chip. It is recommended to place bypass capacitor, power supply bypassing capacitors as close as possible to the chip. Figure 25, 26 shows the recommended layout of double layer PCB. There is an exposed thermal pad on bottom of the chip to provide the direct thermal path from die to external heat sink. It is recommended to use copper on the surface of PC Board as heat sink for AA4002. To dig some matrix regular holes under chip, set diameter for each hole at 0.8~1.0mm, keep distance around 1.7mm between holes, remove copper solder mask of this area, Figure 25. Copper and Holes under the Chip Figure 26. Top Route, Copper and Silkscreen Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited 18 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER AA4002 Application Information (Continued) Figure 27. Bottom Route, Copper and Silkscreen Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited 19 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER AA4002 Typical Application VDD VDD VDD CV 0.1µF DC Volume Control RPU 100kΩ 5 Mute 4 Mode 13 Left Dock 7 DC Vol 19 18 Left Gain 1 Left Gain 2 RBS 20kΩ Mode Control 0.1µF + RIL 20kΩ CIL 0.33µF + 12 11 20kΩ Left In Beep In RIR 20kΩ CIR 0.33µF _ CONTROL PIN Beep Detect Volume Control 31 Steps Bias Bias Left Out+ 15 + + _ Right Out+ TIP 20kΩ COUTR 1µF Right Out - 26 + 6, 16, 27 VDD 1, 8, 14, 20, 23 GND Power Management SLEEVE HEADPHONE JACK 20kΩ + CS 0.1µF 28 Right Dock + COUT 220µF _ CS1 10µF To HP Sense Circuit _ RFR 20kΩ 9 PIN RING _ + Right In RL 1.5kΩ 20kΩ + 10 + Left Out- 17 + RBEEP 200kΩ Audio In Right COUT 220µF + 10kΩ RFL 20kΩ RBEEP 200kΩ BEEP In 10kΩ _ Audio In Left + CBS 0.068µF COUTL Left Dock Right Dock RF 20kΩ RI 20kΩ 3 Gain Select RS 100kΩ 21 HP Sense To Control Pin on Headphone Jack RW 10kΩ 10kΩ CS 0.1µF RL 1.5kΩ 10kΩ 22 Bypass CB 1µF Click and Pop Suppression Circuitry RBS 20kΩ Shutdown Right Gain 1 2 CBS 0.068µF Right Gain 2 24 25 RF 20kΩ RI 20kΩ Figure 28. Typical Application of AA4002 Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited 20 Data Sheet STEREO 2W AUDIO POWER AMPLIFIER AA4002 Mechanical Dimensions TSSOP-28 with Exposed-DAP Unit: mm(inch) 9.600(0.378) 9.800(0.386) 6.250(0.246) 6.550(0.258) BASE PLANE GAUGE LINE 0.250(0.010) PIN #1 ID. 4.300(0.169) 4.500(0.177) 0.800(0.032) 1.050(0.041) 1.200(0.047)MAX 0° 8° 0.650(0.026) BSC 0.190(0.007) 0.300(0.012) 0.050(0.002) 0.150(0.006) EXPOSED PAD 0.450(0.018) 0.750(0.030) 0.090(0.004) 0.200(0.008) SEATING PLANE 2.740(0.108) 3.050(0.120) 5.640(0.222) 5.940(0.234) Sep. 2006 Rev. 1. 1 BCD Semiconductor Manufacturing Limited 21 http://www.bcdsemi.com IMPORTANT NOTICE BCD Semiconductor Manufacturing Limited reserves the right to make changes without further notice to any products or specifications herein. BCD Semiconductor Manufacturing Limited does not assume any responsibility for use of any its products for any particular purpose, nor does BCD Semiconductor Manufacturing Limited assume any liability arising out of the application or use of any its products or circuits. BCD Semiconductor Manufacturing Limited does not convey any license under its patent rights or other rights nor the rights of others. MAIN SITE BCD Semiconductor Manufacturing Limited BCD Semiconductor Manufacturing Limited - Wafer Fab Shanghai SIM-BCD Semiconductor Manufacturing Limited 800, Yi Shan Road, Shanghai 200233, China Tel: +86-21-6485 1491, Fax: +86-21-5450 0008 - IC Design Group Advanced Analog Circuits (Shanghai) Corporation 8F, Zone B, 900, Yi Shan Road, Shanghai 200233, China Tel: +86-21-6495 9539, Fax: +86-21-6485 9673 REGIONAL SALES OFFICE Shenzhen Office Shanghai SIM-BCD Semiconductor Manufacturing Co., Ltd. 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