ACT–PD1M16 Fast Page Mode 16 Megabit Plastic Monolithic DRAM Pin Configuration Top View Vcc I/O0 I/O1 I/O2 I/O3 Vcc I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC NC A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 CIRCUIT TECHNOLOGY www.aeroflex.com VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS Features Fast Access Time (tRAC): 70ns ■ Power Supply: 5.0V ± 0.5V ■ Packaging ■ ● 42 Lead Plastic Surface-Mount SOJ (L4) Industrial and Military Temperature Ranges ■ Three-State Unlatched Output ■ Fast Page Mode ■ RAS-Only Refresh ■ xCAS Before RAS Refresh ■ Hidden Refresh ■ 1024 Cycle Refresh in 16ms ■ Low Power Dissipation ■ Long Refresh Period Option ■ Data Input / Output WE Read/Write Enable OE Output Enable RAS Row Address Strobe UCAS Upper Byte Control / Column Address Strobe LCAS Lower Byte Control / Column Address Strobe VCC +5.0V Power Supply VSS Ground NC Not Connected C LE X LA ISO 9001 E I NC . I/O0-15 F S Address Inputs B A0–9 A E RO Pin Description RTIFIED eroflex Circuit Technology - Advanced Multichip Modules © SCD3750 REV A 8/31/98 Absolute Maximum Ratings Symbol TC TSTG Parameter MINIMUM MAXIMUM Units Case Operating Temp. -55 +125 °C Storage Temperature -55 +150 °C IOS Short Circuit Output Current - 50 mA PT Power Dissipated - 1 W VCC Supply Voltage Range -1.0 +7.0 V VT Voltage Range on any Pin* -1.0 +7.0 V Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability. * All voltage values are with respect to Vss. Recommended Operating Conditions Symbol Parameter Minimum Maximum Units VCC Power Supply Voltage +4.5 +5.5 V VIH Input High Voltage +2.4 - V VIL Input Low Voltage - +0.8 V TCM Operating Temp. (Mil) -55 +125 °C TCI Operating Temp. (Ind.) -40 +85 °C Capacitance (VIN = 0V, f = 1MHz, Tc = 25°C) Symbol Parameter Maximum Units CI(A) A0-9 Input Capacitance 10 pF CI(RC) RAS and CAS Input Capacitance 10 pF CI(OE) OE Input Capacitance 10 pF CI(WE) WE Input Capacitance 10 pF Output Capacitance 15 pF CO These parameters are guaranteed by design but not tested. DC Characteristics (VCC = 5.0V, VSS = 0V, TCI or TCM) Parameter Sym Conditions Min Output Low Voltage VOL IOL = 4.2 mA - Output High Voltage VOH IOH = -5 mA 2.4 Max 0.4 Units V V Input Leakage Current IL VI = 0 to +6.5V, All others 0V to V CC -10 +10 µA Output Leakage Current IO VO = 0 to VCC, CAS high -10 +10 µA 190 mA Read or Write Cycle Current 1,2 Aeroflex Circuit Technology ICC1 VCC = 5.5V, minimum cycle 2 SCD3750 REV A 8/31/98 Plainview NY (516) 694-6700 DC Characteristics (continued) (VCC = 5.0V, VSS = 0V, TCI or TCM) Parameter Sym Conditions Max Units ICC2 VIH = 2.4V (TTL), After 1 memory cycle, RAS and CAS high - 2 mA ICC3 VIH = Vcc - 0.05V (CMOS), After 1 memory cycle, RAS and CAS high - 1 mA - 100 mA Standby Current Average Page Current 2 Min ICC4 RAS low, CAS cycling 1. Measured with a maximum of one address change while RAS = VIL. 2. Measured with a maximum of one address change while CAS = VIH. AC Characteristics* (VCC = 5.0V ±10%, VSS= 0V, TCI or TCM) Parameter Sym Min Max Access Time from Column-Address tAA - 35 ns CAS Low Access Time from CAS tCAC - 20 ns Column Access Time from CAS Precharge tCPA - 40 ns Access Time from RAS tRAC - 70 ns tOEA - 20 ns tOFF 0 15 ns tOEZ 0 15 ns OE Access Time Output Buffer Turn-off Delay 1 Output Buffer Turn-off Delay Time from OE 1 Units * Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access times as the outputs are driven when CAS goes low. 1. tOFF and tOEZ are specified when the outputs are no longer driven. The outputs are disabled by bringing either OE or CAS high. AC Characteristics (VCC = 5.0V, VSS = 0V, TCI or TCM) Parameter Sym 1 Min Max Units tRC 130 - ns tPC 45 - ns tPRWC 90 - ns tRASP 70 200,000 ns tRAS 70 10,000 ns Pulse Duration, CAS Low 4 tCAS 20 10,000 ns Pulse Duration, CAS High Precharge Time tCP 10 - ns Pulse Duration, RAS High Precharge Time tRP 50 - ns Pulse Duration, WE Low tWP 15 - ns Setup Time, Column Address before CAS Low tASC 0 - ns Setup Time, Row Address before RAS Low tASR 0 - ns tDS 0 - ns Setup Time, WE High before CAS Low tRCS 0 - ns Setup Time, WE Low before CAS High tCWL 20 - ns Setup Time, WE Low before RAS High tRWL 20 - ns Cycle Time, Read or Write Random Cycle Time, Fast Page Mode Read or Write 1,2 Cycle Time, Fast Page Mode Read-Modify-Write 1 Pulse Duration, RAS Low Fast Page Mode Pulse Duration, RAS Low Nonpage Mode Setup Time, Data Aeroflex Circuit Technology 3 3 5 3 SCD3750 REV A 8/31/98 Plainview NY (516) 694-6700 AC Characteristics (continued) (VCC = 5.0V, VSS = 0V, TCI or TCM) Parameter Sym Setup Time, WE Low before CAS Low (early-write operation only) tWCS 0 - ns Hold Time, Column Address after CAS Low tCAH 15 - ns Hold Time, Data 5 tDH 15 - ns Min Max Units tRAH 10 - ns 6 tRCH 0 - ns Hold Time, WE High after RAS High 6 tRRH 0 - ns Hold Time, Row Address after RAS Low Hold Time, WE High after CAS High 1. All cycle times assume tT = 5ns, reference to VIH (min) and V IL (max). 2. To assume tPC min, tASC should be ≥ tCP. 3. In read-write cycle, tRWD and tRWL must be observed. 4. In read-write cycle, tCWD and tCWL must be observed. 5. Referenced to the later of xCAS or WE in write operations. 6. Either t RRH or t RCH must be satisfied for a read cycle. AC Characteristics (VCC = 5.0V, VSS = 0V, TCI or TCM) Parameter Sym Min Max WE Low before CAS Low Hold Time (early-write operation only) tWCH 15 - ns OE Command Hold Time tOEH 15 - ns RAS Referenced to OE Hold Time tROH 10 - ns RAS from CAS Precharge (Fast Page Mode) tRHCP 40 - ns Column Address to WE Low Delay Time (read-write operation only) tAWD 60 - ns RAS Low to CAS High Delay Time (CBR refresh only) tCHR 15 - ns CAS High to RAS Low Delay Time (CAS to RAS Precharge Time) tCRP 5 - ns RAS Low to CAS High Delay Time (CAS Hold Time) tCSH 70 - ns CAS Low to RAS Low Delay Time (CAS Set-up Time) tCSR 5 - ns CAS Low to WE Low Delay Time (read-write operation only) tCWD 45 - ns OE to Data Delay Time tOED 15 - ns tRAD 15 35 ns Column Address to RAS High Delay Time tRAL 35 - ns RAS Low to CAS Low Delay Time 1 tRCD 20 50 ns RAS High to CAS Low Precharge Time tRPC 5 - ns CAS Low to RAS High Delay Time (RAS Hold Time) tRSH 20 - ns RAS Low to WE Low Delay Time (read-write operation only) tRWD 95 - ns WE Low after CAS Precharge Delay Time (read-write operation only) tCWD 65 - ns Refresh Time Interval tREF 16 ms 50 ns RAS Low to Column Address Delay Time Transition time 1 2 tT 3 Units 1. The maximum value is specified only to assure access time 2. Transition times (rise and fall) for RAS and xCAS are to be a minimum of 3ns and a maximum of 30ns. Aeroflex Circuit Technology 4 SCD3750 REV A 8/31/98 Plainview NY (516) 694-6700 AC Test Circuit Current Source IOL CL = 50 pF Typical Units Input Pulse Level 0 – 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V VZ ~ 1.5 V (Bipolar Supply) To Device Under Test Parameter IOH Current Source Notes: 1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance ZO = 75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance load circuit. 6) ATE Tester includes jig capacitance. Aeroflex Circuit Technology 5 SCD3750 REV A 8/31/98 Plainview NY (516) 694-6700 OPERATIONS RAS low time and the xCAS page-mode cycle time used. With minimum xCAS page-cycle time, all columns can be accessed without intervening RAS cycles. OPERATIONS DUAL CAS Unlike conventional page-mode DRAMs, the column address buff-ers in this device are activated on the falling edge of RAS. The buffers act as transparent or flow-through latches while xCAS is high. The falling edge of the first xCAS latches the column addresses. This feature allows the devices to operate at a higher data bandwidth than conventional page-mode parts because data retrieval begins as soon as the column address is valid rather than when xCAS transitions low. This performance improvement is referred to as enhanced page mode. A valid column address may be presented immediately after tRAH (row-address hold time) has been satisfied, usually well in advance of the falling edge of xCAS. In this case, data is obtained after tCAC maximum (access time from xCAS low) if tAA maximum (access time from column address) has been satisfied. In the event that column addresses for the next page cycle are valid at the time xCAS goes high, minimum access time for the next cycle is determined by tCPA (access time from rising edge of the last xCAS). Two CAS pins (LCAS and UCAS) are provided to give independent control of the 16 data-I/O pins (I/O0-15), with LCAS corresponding to I/O0-7 and UCAS corresponding to I/O8-15. For read or write cycles, the column address is latched on the first xCAS falling edge. Each xCAS going low enables its corresponding I/Ox pin with data associated with the column address latched on the first falling xCAS edge. All address setup and hold parameters are referenced to the first falling xCAS edge. The delay time from xCAS low to valid data out (see parameter tCAC) is measured form each individual xCAS to its corresponding I/Ox pin. In order to latch in a new column address, both xCAS pins must be brought high. The column-precharge time (see parameter tCP ) is measured from the last xCAS rising edge to the first xCAS falling edge of the new cycle. Keeping a column address valid while toggling xCAS requires a minimum setup time, tCLCH. During tCLCH at least one xCAS must be brought low before the other xCAS is taken high. ADDRESS: A0-9 For early-write cycles, the data is latched on the first xCAS falling edge. Only the I/Os that have the corresponding xCAS low are written into. Each xCAS must meet tCAS minimum in order to ensure writing into the storage cell. To latch a new address and new data, all xCAS pins must be high and meet tCP. Twenty address bits are required to decode 1 of 1048576 storage cell locations. For the ACTPD1M16, 10 row-address bits are set up on A0 through A9 and latched onto the chip by RAS. Ten, column-address bits are set up on A0 through A9 and latched onto the chip by the first xCAS. All addresses must be stable on or before the falling edge of RAS and xCAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. xCAS is used as a chip select, activating its correspond-ing output buffer and latching the address bits into the column-address buffers. PAGE MODE Page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum number of columns that can be accessed is determined by the maximum Aeroflex Circuit Technology 6 SCD3750 REV A 8/31/98 Plainview NY (516) 694-6700 WRITE ENABLE (WE) in the low-impedance state until either OE or xCAS is brought high. The read or write mode is selected through WE. A logic high on WE selects the read mode and a logic low selects the write mode. The data inputs are disabled when the read mode is selected. When WE goes low prior to xCAS (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with OE grounded. *Output Enable can be held low during write cycles. RAS-ONLY REFRESH A refresh operation must be performed at least once every 16ms (128ms for long refresh periods) to retain data. This can be achieved by strobing each of the 1024 rows (A0-9). A normal read or write cycle refreshes all bits in each row that is selected. A RAS-only operation can be used by holding both xCAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. DATA IN (I/O0-15) Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge of xCAS or WE strobes data into the on-chip data latch. In an early-write cycle, WE is brought low prior to xCAS and the data is strobed in by the first occurring xCAS with setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, xCAS is already low and the data is strobed in by WE with setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring the output buffers to the high-impedance state prior to impressing data on the I/O lines. HIDDEN REFRESH Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding xCAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. The external address is ignored and the refresh address is generated internally. xCAS-BEFORE-RAS (xCBR) REFRESH DATA OUT (I/O0-15) Data out is the same polarity as data in. The output is in the high-impedance (floating) state until xCAS and OE are brought low. In a read cycle, the output becomes valid after the access time interval tCAC (which begins with the negative transition of xCAS) as long as tRAC and tAA are satisfied. xCBR refresh is utilized by bringing at least one xCAS low earlier than RAS (see parameter tCSR) and holding it low after RAS fails (see parameter tCHR). For succesive xCBR refresh cycles, xCAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated internally. OUTPUT ENABLE (OE)* OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance state. It is necessary for both RAS and xCAS to be brought low for the output butters to go into the low-impedance state, and they remain Aeroflex Circuit Technology POWER UP To achieve proper device operation, an initial pause of 200µs followed by a minimum of eight initialization cycles is required after power up to full Vcc level. These eight initialization cycles must include at least one refresh (RAS-only or xCBR) cycle. 7 SCD3750 REV A 8/31/98 Plainview NY (516) 694-6700 Package Outline "L4" — SOJ Package, 42 Leads 0.20 (0.008) TYP 27.30 (1.075) ±0.13 (0.005) 42 22 10.16 (0.400) ±0.13 (0.005) 11.18 (0.440) ±0.13 (0.005) 1 9.40 (0.370) ±0.25 (0.070) 21 3.51 (0.138) ±0.25 (0.01) Pin 1 Identifier (Do not block with Label) 2.69 (0.106) TYP .46 ±0.05 TYP (.018 ±0.002) 1.27 TYP (0.050) All dimensions in millimeters Dimensions in millimeters mm Dimensions in inches () Aeroflex Circuit Technology 8 SCD3750 REV A 8/31/98 Plainview NY (516) 694-6700 CIRCUIT TECHNOLOGY Ordering Information (Typical) Model Number Options Speed Package ACT-PD1M16N–070L4I None 70ns 42 Lead SOJ ACT-PD1M16W–070L4I Burn-in 70ns 42 Lead SOJ ACT-PD1M16X–070L4I Temp Cycle 70ns 42 Lead SOJ ACT-PD1M16Y–070L4I Temp Cycle & Burn-in 70ns 42 Lead SOJ ACT-PD1M16N–070L4T None 70ns 42 Lead SOJ ACT-PD1M16W–070L4T Burn-in 70ns 42 Lead SOJ ACT-PD1M16X–070L4T Temp Cycle 70ns 42 Lead SOJ ACT-PD1M16Y–070L4T Temp Cycle & Burn-in 70ns 42 Lead SOJ Part Number Breakdown \\\ ACT- P D 1M 16 N– 070 L4 T Aeroflex Circuit Technology Plastic Path Electrical Testing I = Industrial Temp, -40°C to +85°C T = Military Temp, -55°C to +125°C Memory Type D = Plastic DRAM Memory Depth, Locations Memory Width, Bits Package Type & Size L4 = 42 Pin Plastic SOJ Options N = None W = Burn-in * X = Temperature Cycle * Y = Burn-in & Temperature Cycle * * Screened to the test methods of MIL-STD-883 Memory Speed, ns 070 = 70ns Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: 1-(800) 843-1553 Aeroflex Circuit Technology 35 South Service Road Plainview New York 11830 Aeroflex Circuit Technology 9 SCD3750 REV A 8/31/98 Plainview NY (516) 694-6700