TI TMS428169A

TMS418169A, TMS428169A
1048576 BY 16-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS892C – AUGUST 1996 – REVISED SEPTEMBER 1997
D
D
D
D
D
D
D
D
D
D
D
This data sheet is applicable to TMS418169A
and TMS428169A symbolized by Revision “E”,
and subsequent revisions as described in the
device symbolization section.
Organization . . . 1 048576 by 16 Bits
Single 5-V Power Supply for TMS418169A
(± 10% Tolerance)
Single 3.3-V Power Supply for TMS428169A
(± 0.3 V Tolerance)
1 024-Cycle Refresh in 16 ms
Performance Ranges:
’418169A-50
’418169A-60
’418169A-70
’428169A-60
’428169A-70
ACCESS ACCESS ACCESS READ OR
TIME
TIME
TIME
EDO
tRAC
tCAC
tAA
CYCLE
MAX
MAX
MAX
MIN
50 ns
13 ns
25 ns
20 ns
60 ns
15 ns
30 ns
25 ns
70 ns
18 ns
35 ns
30 ns
60 ns
15 ns
30 ns
25 ns
70 ns
18 ns
35 ns
30 ns
Extended-Data-Out (EDO) Operation
xCAS-Before-RAS ( xCBR) Refresh
3-State Unlatched Output
Low Power Dissipation
High-Reliability Plastic 42-Lead
400-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package (DZ Suffix) and
44/50-Lead Surface-Mount Thin
Small-Outline Package ( TSOP) (DGE Suffix)
Ambient Temperature Range
0°C to 70°C
DGE PACKAGE
( TOP VIEW )
DZ PACKAGE
( TOP VIEW )
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NC
NC
W
RAS
NC
NC
A0
A1
A2
A3
VCC
1
42
2
41
3
40
4
39
5
38
6
37
7
36
8
35
9
34
10
33
11
32
12
31
13
30
14
29
15
28
16
27
17
26
18
25
19
24
20
23
21
22
description
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
VSS
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NC
1
50
2
49
3
48
4
47
5
46
6
45
7
44
8
43
9
42
10
41
11
40
NC
NC
W
RAS
NC
NC
A0
A1
A2
A3
VCC
15
36
16
35
17
34
18
33
19
32
20
31
21
30
22
29
23
28
24
27
25
26
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
VSS
PIN NOMENCLATURE
The TMS418169A and TMS428169A are
16 777 216-bit dynamic random-access memory
(DRAM) devices organized as 1 048 576 words of
16 bits each. They employ state-of-the-art
technology for high performance, reliability, and
low power at low cost.
A[0:9]
DQ[0:15]
LCAS
UCAS
NC
OE
RAS
VCC
VSS
W
Address Inputs
Data In / Data Out
Lower Column-Address Strobe
Upper Column-Address Strobe
No Internal Connection
Output Enable
Row-Address Strobe
5-V or 3.3-V Supply
Ground
Write Enable
The TMS418169A features maximum RAS
access times of 50-, 60-, and 70 ns, and the
TMS428169A features maximum RAS access
times of 60- and 70 ns. All addresses and data-in lines are latched on-chip to simplify system design. Data out
is unlatched to allow greater system flexibility.
The TMS418169A is offered in a 42-lead plastic surface-mount SOJ package (DZ suffix). The TMS428169A
is offered in a 44/50-lead plastic surface-mount TSOP (DGE suffix). These packages are designed for operation
from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TMS418169A, TMS428169A
1048576 BY 16-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS892C – AUGUST 1996 – REVISED SEPTEMBER 1997
logic symbol (TMS418169A and TMS428169A)†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
RAS
17
18
19
20
23
24
25
26
27
28
14
LCAS 31
UCAS 30
RAM 1M × 16
20D10/21D0
A
0
1 048 575
20D19 / 21D9
C20[ROW]
G23/[REFRESH ROW]
24[PWR DWN]
C21
G24
&
23C22
31
C21
G34
&
31
23C32
Z31
W 13
OE 29
DQ0 2
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
3
4
5
7
8
9
10
33
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
34
35
36
38
39
40
41
23,21D
24,25EN27
34,25EN37
25
A,22D
∇26,27
A, Z26
A,32D
∇36,37
A, Z36
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
The pin numbers shown correspond to the DZ package.
2
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TMS418169A, TMS428169A
1048576 BY 16-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS892C – AUGUST 1996 – REVISED SEPTEMBER 1997
functional block diagram (TMS418169A and TMS428169A)
RAS UCAS LCAS
W
OE
Timing and Control
A0
A1
10
Column Decode
Sense Amplifiers
Column Address
Buffers
256K Array
256K Array
A9
Row Address
Buffers
256K Array
R
o
w
256K Array
32
D
e
c
o
d
e
32
10
256K Array
32
32
I/O
Buffers
16 of 32
Selection
DataIn
Reg.
DataOut
Reg.
16
16
DQ0 – DQ15
256K Array
10
operation
dual xCAS
Two xCAS pins (LCAS and UCAS) are provided to give independent control of the 16 data I/O pins
(DQ0– DQ15), with LCAS corresponding to DQ0 – DQ7 and UCAS corresponding to DQ8 – DQ15. Each xCAS
going low enables its corresponding DQx pins.
In write cycles, data-in setup and hold times (tDS and tDH) and write-command setup and hold times (tWCS, tCWL,
and tWCH) must be satisfied for each individual xCAS to ensure writing into the storage cells of the corresponding
DQ pins.
Different modes of operation for upper and lower bytes in one cycle are not allowed, such as the example in
Figure 1.
RAS
Delay write
UCAS
Early write
LCAS
W
Figure 1. Illegal Dual-xCAS Operation
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3
TMS418169A, TMS428169A
1048576 BY 16-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS892C – AUGUST 1996 – REVISED SEPTEMBER 1997
extended data out
Extended data out (EDO) allows for data output rates of up to 50 MHz for 50-ns devices. When keeping the same
row address while selecting random column addresses, the time for row-address setup-and-hold and address
multiplexing is eliminated. The maximum number of columns that can be accessed is determined by tRASP , the
maximum RAS low time.
EDO does not enter the DQs into the high-impedance state with the rising edge of xCAS. The output remains
valid for the system to latch the data. After xCAS goes high, the DRAM decodes the next address. OE and W
can be used to control the output impedance. Descriptions of OE and W further explain the benefit of EDO
operation.
address: A0 – A9
Twenty address bits are required to decode each of the 1 048 576 storage cell locations. Ten row-address bits
are set up on A0 – A9 and latched on the chip by RAS. Ten column-address bits are set up on A0 – A9 and latched
on the chip by the first xCAS. All addresses must be stable on or before the falling edge of RAS and xCAS. RAS
is similar to a chip-enable in that it activates the sense amplifiers as well as the row decoder. xCAS is used as
a chip-select, activating its corresponding output buffer and latching the address bits into the column-address
buffers.
The column address is latched on the first xCAS falling edge with address setup and hold parameters
referenced to that edge. In order to latch in a new column address, both xCAS pins must be brought high. The
column-precharge time (see parameter tCP) is measured from the last xCAS rising edge to the first xCAS falling
edge of the new cycle. Keeping a column address valid while toggling xCAS requires a minimum setup time,
tCLCH. During tCLCH, at least one xCAS must be brought low before the other xCAS is taken high.
write enable ( W)
The read- or write mode is selected through W. A logic high on W selects the read mode and a logic low selects
the write mode. The data input is disabled when the read mode is selected. When W goes low prior to xCAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation
independent of the state of OE. This permits early-write operations to be completed with OE grounded. If W goes
low in an EDO-read cycle, the DQ pins go into the high-impedance state as long as xCAS is high (see Figure 9).
data in (DQ0 – DQ15)
Data is written during a write- or read-modify-write cycle. Depending on the mode of operation, the falling edge
of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to an xCAS
falling edge, and data is strobed into the on-chip data latch for the corresponding DQ pins with setup-and-hold
times referenced to this xCAS signal.
In a delayed-write- or read-modify-write cycle, xCAS is already low and data is strobed in by W with
setup-and-hold times referenced to this signal. Also, OE must be high to bring the output buffers to the
high-impedance state prior to impressing data on the I / O lines (see parameter tOED).
data out (DQ0 – DQ15)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until xCAS and OE
are brought low. In a read cycle, the output becomes valid after the access-time interval tCAC (which begins with
the negative transition of xCAS) as long as tRAC and tAA are satisfied. The delay time from xCAS low to valid
data out is measured from each individual xCAS to its corresponding DQx pin.
4
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TMS418169A, TMS428169A
1048576 BY 16-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS892C – AUGUST 1996 – REVISED SEPTEMBER 1997
output enable (OE)
OE controls the impedance of the output buffers. While xCAS and RAS are low and W is high, OE can be brought
low or high and the DQs transition between valid data and high impedance. There are two methods of placing
the DQs into the high-impedance state and keeping them in that state during xCAS high time by using OE. The
first method is to transition OE high before xCAS transitions high and to keep OE high for tCHO past the xCAS
transition. This disables the DQs and they remain in the high-impedance state, regardless of OE, until xCAS
falls again (see Figure 8). The second method is to have OE low as xCAS transitions high. Then OE can pulse
high for a minimum of tOEP anytime during xCAS high time, disabling the DQs regardless of further transitions
on OE until xCAS falls again (see Figure 8).
RAS-only refresh
A refresh operation must be performed at least once every 16 ms to retain data. This is achieved by strobing
each of the 1 024 rows (A0 – A9). A normal read or write cycle refreshes all bits in each row that is selected. A
RAS-only operation can be used by holding both xCAS pins at the high (inactive) level, conserving power as
the output buffers remain in the high-impedance state. Externally generated addresses must be used for a
RAS-only refresh.
hidden refresh
Hidden refresh can be performed while maintaining valid data at the output pins. This is accomplished by holding
xCAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle. The external address is ignored and the refresh address is generated internally.
xCAS-before-RAS (xCBR) refresh
xCBR refresh is achieved by bringing at least one xCAS low earlier than RAS (see parameter tCSR) and holding
it low after RAS falls (see parameter tCHR). For successive xCBR refresh cycles, xCAS can remain low while
cycling RAS. The external address is ignored and the refresh address is generated internally.
power-up
To achieve proper device operation, an initial pause of 200 µs, followed by a minimum of eight initialization
cycles, is required after power up to the full VCC level. These eight initialization cycles must include at least one
refresh (RAS-only or xCBR) cycle.
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5
TMS418169A, TMS428169A
1048576 BY 16-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS892C – AUGUST 1996 – REVISED SEPTEMBER 1997
absolute maximum ratings over ambient temperature range (unless otherwise noted)†
Supply voltage range, VCC:
TMS418169A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
TMS428169A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Voltage range on any pin (see Note 1): TMS418169A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
TMS428169A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
’418169A
’428169A
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
3
3.3
3.6
VCC
VSS
Supply voltage
VIH
VIL
High-level input voltage
2.4
6.5
2
Low-level input voltage (see Note 2)
–1
0.8
– 0.3
Supply voltage
0
0
UNIT
V
V
VCC + 0.3
0.8
V
V
TA
Ambient temperature
0
70
0
70
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
6
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TMS418169A, TMS428169A
1048576 BY 16-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS892C – AUGUST 1996 – REVISED SEPTEMBER 1997
TMS418169A
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted)
PARAMETER
TEST CONDITIONS†
VOH
High-level output
voltage
VOL
Low-level output voltage
II
Input current (leakage)
IO
Output current
(leakage)
VCC = 5.5 V,
xCAS high
ICC1‡§
Average read- or
write-cycle current
VCC = 5.5 V,
ICC2
Average
g standby
y
current
IOH = – 5 mA
’418169A - 50
MIN
’418169A - 60
MAX
2.4
IOL = 4.2 mA
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VCC
MIN
MAX
2.4
’418169A - 70
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
± 10
± 10
± 10
µA
VO = 0 V to VCC,
± 10
± 10
± 10
µA
Minimum cycle
180
160
150
mA
VIH = 2.4 V ( TTL),
After one memory cycle,
RAS and xCAS high
2
2
2
mA
VIH = VCC – 0.2 V (CMOS),
After one memory cycle,
RAS and xCAS high
1
1
1
mA
ICC3§
Average refresh current
(RAS-only refresh or
xCBR)
VCC = 5.5 V,
Minimum cycle,
RAS cycling,
xCAS high (RAS only),
xCAS before RAS (xCBR)
180
160
150
mA
ICC4‡¶
Average EDO current
VCC = 5.5 V,
RAS low,
140
110
100
mA
tHPC = MIN,
xCAS cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
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TMS418169A, TMS428169A
1048576 BY 16-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS892C – AUGUST 1996 – REVISED SEPTEMBER 1997
TMS428169A
electrical characteristics over recommended ranges of supply voltage and ambient conditions
(unless otherwise noted)
PARAMETER
’428169A -60
TEST CONDITIONS†
MIN
’428169A - 70
MAX
MAX
High-level
g
output
voltage
IOH = – 2 mA
IOH = – 100 µA
LVTTL
VOL
Low level output voltage
Low-level
IOL = 2 mA
IOL = 100 µA
LVTTL
0.4
0.4
LVCMOS
0.2
0.2
II
Input current (leakage)
VCC = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VCC
± 10
± 10
µA
IO
Output current (leakage)
VCC = 3.6 V,
xCAS high
VO = 0 V to VCC,
± 10
± 10
µA
ICC1‡§
Average read- or write-cycle
current
VCC = 3.6 V,
Minimum cycle
150
140
mA
VIH = 2 V (LVTTL),
After one memory cycle,
RAS and xCAS high
2
2
mA
VIH = VCC – 0.2 V (LVCMOS),
After one memory cycle,
RAS and xCAS high
1
1
mA
ICC2
Average standby current
2.4
UNIT
VOH
LVCMOS
2.4
MIN
VCC – 0.2
V
VCC – 0.2
V
ICC3§
Average refresh current
(RAS-only refresh
or xCBR)
VCC = 3.6 V,
Minimum cycle,
RAS cycling,
xCAS high (RAS-only refresh) xCBR
150
140
mA
ICC4‡¶
Average EDO current
VCC = 3.6 V,
RAS low,
110
100
mA
tHPC = MIN,
xCAS cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
8
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TMS418169A, TMS428169A
1048576 BY 16-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS892C – AUGUST 1996 – REVISED SEPTEMBER 1997
capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 – A9
5
pF
Ci(OE)
Input capacitance, OE
7
pF
Ci(RC)
Input capacitance, xCAS and RAS
7
pF
Ci(W)
Input capacitance, W
Output capacitance†
7
pF
7
pF
CO
† xCAS and OE = VIH to disable outputs
NOTE 3: VCC = 5 V ± 0.5 V or 3.3 V ± 0.3 V, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and ambient temperature
(see Note 4)
’418169A - 60
’428169A -60
’418169A - 50
PARAMETER
MIN
MAX
MIN
MAX
’418169A - 70
’428169A-70
MIN
UNIT
MAX
tAA
tCAC
Access time from column address (see Note 5)
25
30
35
ns
Access time from xCAS (see Note 5)
13
15
18
ns
tCPA
tRAC
Access time from xCAS precharge (see Note 5)
28
35
40
ns
Access time from RAS (see Note 5)
50
60
70
ns
tOEA
tCLZ
Access time from OE (see Note 5)
13
15
18
ns
Delay time, xCAS to output in the low-impedance state
0
tOEZ
tREZ
Output buffer turnoff delay from OE (see Note 6)
3
13
3
15
3
18
ns
Output buffer turnoff delay from RAS (see Note 6)
3
13
3
15
3
18
ns
tCEZ
tWEZ
Output buffer turnoff delay from xCAS (see Note 6)
3
13
3
15
3
18
ns
Output buffer turnoff delay from W (see Note 6)
3
13
3
15
3
18
ns
0
0
ns
NOTES: 4. With ac parameters, it is assumed that tT = 2 ns.
5. Access times for TMS428169A are measured with output reference levels of VOH = 2 V and VOL = 0.8 V.
6. The MAX specifications of tREZ , tCEZ , tWEZ, and tOEZ are specified when the output is no longer driven. Data-in should not be driven
until one of the applicable maximum specifications is satsified.
EDO timing requirements (see Note 4)
’418169A - 50
MIN
’418169A - 60
’428169A-60
MAX
MIN
MAX
’418169A - 70
’428169A -70
MIN
UNIT
MAX
tHPC
tPRWC
Cycle time, EDO page-mode read or write
20
25
30
ns
Cycle time, EDO read-write
57
68
78
ns
tCSH
tCHO
Delay time, RAS active to xCAS precharge
40
48
58
ns
Hold time, OE from xCAS
7
10
10
ns
tDOH
tCAS
Hold time, output from xCAS active
5
5
5
ns
Pulse duration, xCAS active (see Note 7)
8
tWPE
tCP
Pulse duration, W (output disable only)
7
7
7
ns
Pulse duration, xCAS precharge
8
10
10
ns
tOCH
tOEP
Setup time, OE before xCAS
8
10
10
ns
Precharge time, OE (output disable only)
5
5
5
ns
10 000
10
10 000
12
10 000
ns
NOTES: 4. With ac parameters, it is assumed that tT = 2 ns.
7. In a read-write cycle, tCWD and tCWL must be observed.
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TMS418169A, TMS428169A
1048576 BY 16-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS892C – AUGUST 1996 – REVISED SEPTEMBER 1997
ac timing requirements (see Note 4)
’418169A - 50
MIN
MAX
’418169A - 60
’428169A-60
MIN
MAX
’418169A - 70
’428169A -70
MIN
UNIT
MAX
tRC
tWC
Cycle time, read
tRWC
tRASP
Cycle time, read-write
Pulse duration, RAS active, page mode (see Note 8)
50 100 000
60 100 000
70 100 000
ns
tRAS
tRP
Pulse duration, RAS active, nonpage mode (see Note 8)
50
60
70
ns
Pulse duration, RAS precharge
30
40
50
ns
tWP
tASC
Pulse duration, write command
8
10
10
ns
Setup time, column address
0
0
0
ns
tASR
tDS
Setup time, row address
0
0
0
ns
Setup time, data in (see Note 9)
0
0
0
ns
tRCS
tCWL
Setup time, read command
0
0
0
ns
Setup time, write command before xCAS precharge
8
10
12
ns
tRWL
Setup time, write command before RAS precharge
8
10
12
ns
tWCS
Setup time, write command before xCAS active
(early-write only)
0
0
0
ns
10
10
10
ns
Cycle time, write
84
104
124
ns
84
104
124
ns
111
135
160
ns
10 000
10 000
10 000
tWRP
tCSR
Setup time, write before RAS active (xCBR refresh only)
Setup time, xCAS referenced to RAS (xCBR refresh only)
5
5
5
ns
tCAH
tDH
Hold time, column address
8
10
12
ns
Hold time, data in (see Note 9)
8
10
12
ns
tRAH
tRCH
Hold time, row address
8
10
10
ns
Hold time, read command referenced to xCAS (see Note 10)
0
0
0
ns
tRRH
Hold time, read command referenced to RAS (see Note 10)
0
0
0
ns
tWCH
Hold time, write command during xCAS active
(early-write only)
8
10
12
ns
tCLCH
tRHCP
Hold time, xCAS low to xCAS high
5
5
5
ns
Hold time, RAS active from xCAS precharge
28
35
40
ns
tOEH
tROH
Hold time, OE command
13
15
18
ns
8
10
10
ns
tWRH
Hold time, write after RAS active (xCBR refresh only)
10
10
10
ns
tAWD
Delay time, column address to write command
(read-write only)
42
49
57
ns
Delay time, xCAS referenced to RAS (xCBR refresh only)
8
10
10
ns
Delay time, xCAS precharge to RAS
5
5
5
ns
Delay time, xCAS to write command
(read-write operation only)
30
34
40
ns
tCHR
tCRP
tCWD
Hold time, RAS referenced to OE
NOTES: 4.
8.
9.
10.
10
With ac parameters, it is assumed that tT = 2 ns.
In a read-write cycle, tRWD and tRWL must be observed.
Referenced to the later of xCAS or W in write operations
Either tRRH or tRCH must be satisfied for a read cycle.
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TMS418169A, TMS428169A
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SMKS892C – AUGUST 1996 – REVISED SEPTEMBER 1997
ac timing requirements (see Note 4) (continued)
’418169A - 50
MIN
tOED
tRAD
Delay time, OE to data in
13
Delay time, RAS to column address (see Note 11)
10
tRAL
tCAL
Delay time, column address to RAS precharge
25
Delay time, column address to xCAS precharge
18
tRCD
tRPC
Delay time, RAS to xCAS (see Note 11)
12
tRSH
tRWD
Delay time, xCAS active to RAS precharge
Delay time, RAS active to write command (read-write only)
tCPW
Delay time, xCAS precharge to write command (read-write only)
45
tREF
Refresh time interval
Delay time, RAS precharge to xCAS
MAX
’418169A - 60
’428169A-60
MIN
MAX
15
25
12
30
12
ns
35
14
ns
ns
25
45
UNIT
MAX
35
20
14
MIN
18
30
37
’418169A - 70
’428169A-70
ns
52
ns
5
5
5
ns
8
10
12
ns
67
79
92
ns
54
62
ns
’418169A
16
16
16
ms
’428169A
16
16
16
ms
30
ns
tT
Transition time
NOTES: 4. With ac parameters, it is assumed that tT = 2 ns.
11. The maximum value is specified only to assure access time.
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2
30
2
11
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PARAMETER MEASUREMENT INFORMATION
VTH
VCC
RL
R1
Output Under Test
Output Under Test
R2
CL = 100 pF
(see Note A)
CL = 100 pF
(see Note A)
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
DEVICE
R1 (Ω )
R2 (Ω )
’418169A
VCC ( V )
5
RL (Ω )
295
VTH ( V )
1.31
828
’428169A
3.3
1178
868
1.4
500
Figure 2. Load Circuits for Timing Parameters
12
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PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tT
tRP
tRCD
tCAS
See Note D
UCAS
tCLCH
(see Note A)
tCAS
See Note D
LCAS
tCP
tCRP
tCSH
tRSH
tRAD
tRAH
tASC
tCAL
tASR
Address
tRAL
Row
Column
Don’t Care
tRRH
tCAH
tRCH
tRCS
W
tCAC
Don’t Care
Don’t Care
(see Note B)
tAA
tREZ
tCLZ
Valid Data Out
DQ0 – DQ15
See Note C
tRAC
tOEZ
tROH
OE
NOTES: A.
B.
C.
D.
Don’t Care
tOEA
Don’t Care
To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
tCAC is measured from xCAS to its corresponding DQx.
Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
xCAS order is arbitrary.
Figure 3. Read-Cycle Timing
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PARAMETER MEASUREMENT INFORMATION
tWC
tRAS
RAS
tT
UCAS
tRP
tRCD
tCAS
See Note B
tCLCH
(see Note A)
LCAS
tCP
See Note B
tASR
tCRP
tCSH
tRSH
tRAH
tASC
tCAL
Address
Row
tRAL
Column
Don’t Care
tCAH
tCWL
tRAD
(see Note C)
tRWL
W
Don’t Care
Don’t Care
tWP
tDH
DQ0 – DQ15
Don’t Care
Don’t Care
Valid Data In
tDS
tOED
tOEH
Don’t Care
OE
NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. xCAS order is arbitrary.
C. tCWL must be satisfied for each xCAS to write properly to each byte.
Figure 4. Write-Cycle Timing
14
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PARAMETER MEASUREMENT INFORMATION
tWC
tRAS
RAS
tT
tRP
tRCD
tCSH
UCAS
tCRP
tCAS
See Note B
tRSH
tCLCH
(see Note A)
LCAS
See Note B
tRAD
tCP
tASR
tRAH
tCAS
tASC
tCAL
tRAL
Address
(see Note C)
(see Note C)
W
Column
Row
Don’t Care
tCAH
tWCS
tWCS
tWCH (see Note C)
tWCH
Don’t Care
Don’t Care
tCWL
(see Note E)
tRWL
tWP
DQ8 – DQ15
Don’t Care
(see Note D)
DQ0 – DQ7
Valid Data In
Don’t Care
tDH (see Note D)
tDS
Don’t Care
Valid Data In
(see Note D)
tDH (see Note D)
tDS
Don’t Care
OE
NOTES: A.
B.
C.
D.
E.
Don’t Care
To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
xCAS order is arbitrary.
tWCS and tWCH must be satisfied for each xCAS.
tDS and tDH of a DQ input is referenced to the corresponding xCAS.
tCWL must be satisfied for each xCAS to properly write to each byte.
Figure 5. Early-Write-Cycle Timing
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PARAMETER MEASUREMENT INFORMATION
tRWC
tRAS
RAS
tRP
tT
tCRP
tRCD
tCAS
tASR
xCAS
tCP
tRAH
tCAH
tRAD
Address
tT
tASC
Row
Don’t Care
Column
tCWL
tRCS
tRWL
tRWD
tWP
Don’t Care
W
tAWD
tCWD
tCAC
tDS
tAA
tDH
tCLZ
DQ0 – DQ15
Hi-Z
Data
Out
(See Note A)
tRAC
Data
In
tOEZ
tOEA
tOED
OE
Don’t Care
tOEH
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 6. Read-Write-Cycle Timing
16
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PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tRCD
tCRP
tCAS
UCAS (See Note F)
tRHCP
tRSH
tCLCH
(see Note A)
tHPC
tCSH
tCAS
tCP
(See Note F)
tASR
LCAS
tRAH
tCAL
tASC
tRAL
tCAH
Address
Row
Column
#1
Column #2
Don’t Care
Don’t Care
tRAD
W
tRCH
Don’t
Care
tRRH
Don’t Care
tCAC
(see Note B)
tAA
tCPA
(see Note C)
tRCS
tRAC
tREZ
tDOH
tCLZ
DQ8 – DQ15
(see Note D)
Data #1
tAA
DQ0 – DQ7
(see Note D)
Data #1
Data #2
tOEZ
OE
Don’t Care
tOEA
NOTES: A.
B.
C.
D.
E.
To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
tCAC is measured from xCAS to its corresponding DQx.
Access time is tCPA-, tAA-, or tCAC-dependent.
Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write- and read-modify-write timing
specifications are not violated.
F. xCAS order is arbitrary.
Figure 7. EDO Read-Cycle Timing (See Note E)
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PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRHCP
RAS
tCSH
tHPC
tCAS
tCP
tRSH
xCAS
tASR
tRAH
tASC
tCAL
tCAH
tRAL
Column #1
Address
tRAD
Column #2
Column #3
tOCH
tCHO
tOEP
OE
tOEA
tRRH
tRCS
tRCH
tOEA
tCAC
W
tDOH
tCLZ
tAA
tOEZ
tCAC
tCAC
tAA
Data #1
Data #1
Data #2
NOTE A: Output is turned off by tCEZ if RAS goes high during xCAS low.
Figure 8. EDO Read-Cycle Timing With OE Control
18
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(see Note A)
tREZ
tOEZ
tRAC
DQ0 – DQ15
tCEZ
tCPA
tAA
• HOUSTON, TEXAS 77251–1443
Data #3
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PARAMETER MEASUREMENT INFORMATION
tRASP
tRHCP
RAS
tCSH
tHPC
tRSH
tCP
tCRP
tCAS
xCAS
tASR
tRAH
tASC
Address
Row
tCAH
tCAL
Column #1
tRAL
Column #2
Column #3
tRAD
OE
tOEA
tCAC
tRCS
tCAC
tWPE
tRCH
tRRH
W
tDOH
tCAC
tWEZ
tAA
tCPA
tCPA
tCLZ
tCEZ
(see Note A)
tAA
tAA
tRAC
DQ0 – DQ15
Data #1
Data #2
Data #3
NOTE A: Output is turned off by tCEZ if RAS goes high during xCAS low.
Figure 9. EDO Read-Cycle Timing With W Control
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19
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PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tRSH
UCAS
tCAS
(See Note C)
tRCD
(See Note C)
LCAS
tRHCP
tHPC
tCLCH
(see Note A)
tCP
tCSH
tCRP
tCAS
tASR
tCAH
tASC
tCAL
tRAH
Address
tRAL
Don’t Care
Column
Row
tRAD
tCWL
tCWL
tWP
tDS
W
Don’t Care
Column
tRWL
tDS
Don’t Care
Don’t Care
Don’t Care
tDH
DQ8 –
DQ15
Valid In
Don’t Care
tDH
DQ0 –
DQ7
Valid In
Valid In
Don’t Care
tOED
OE
NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read- and read-modify-write timing
specifications are not violated.
C. xCAS order is arbitrary.
Figure 10. EDO Write-Cycle Timing
20
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SMKS892C – AUGUST 1996 – REVISED SEPTEMBER 1997
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tRSH
UCAS
(See Note C)
tCAS
tRCD
(See Note C)
LCAS
tRHCP
tHPC
tCLCH
(see Note A)
tCP
tCSH
tCRP
tCAS
tASR
tCAH
tASC
tCAL
tRAH
Address
tRAL
Don’t Care
Column
Row
Don’t Care
Column
tRAD
tCWL
tCWL
(see Note F)
tWCS
(see Note D)
tRWL
(see Note D)
W
Don’t Care
(see Note E)
DQ8 –
DQ15
Don’t Care
Don’t Care
tDS
Don’t Care
Valid In
tDH (see Note E)
DQ0 –
DQ7
Valid In
Valid In
Don’t Care
NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read- and read-modify-write timing
specifications are not violated.
C. xCAS order is arbitrary.
D. tWCS and tWCH must be satisfied for each xCAS in an early-write cycle.
E. tDS and tDH of a DQ input are referenced to the corresponding xCAS.
F. tCWL must be satisfied for each xCAS to ensure proper writing to each byte.
Figure 11. EDO Early Write-Cycle Timing (See Note B)
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21
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PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tRHCP
tCSH
tRCD
UCAS
tRSH
tCRP
tPRWC
See Note D
tCAS
tCP
tCLCH
(see Note A)
See Note D
LCAS
tASR
tASC
tCAH
tRAD
Address
Row
Column
Column
tCWD
tAWD
tRAH
tWP
tRWD
tCWL
tRWL
tCPW
W
tCAC
See Note F tAA
tDS
tRCS
tAA
tRAC
tCPA
(see Note B)
tDH
(see Note C)
tCLZ
Valid In
DQ0 – DQ15
Valid Out
tOEA
tOEH
Valid Out
Valid In
tOEH
tOEZ
tOED
OE
To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
Access time is tCPA-, tAA-, or tCAC-dependent.
Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
xCAS order is arbitrary.
A read or write cycle can be intermixed with read-modify-write cycles as long as the read- and write-cycle timing specifications are
not violated.
F. tCAC is measured from xCAS to its corresponding DQx.
NOTES: A.
B.
C.
D.
E.
Figure 12. EDO Read-Modify-Write-Cycle Timing (See Note E)
22
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PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tCRP
tT
xCAS
See Note A
Don’t Care
tASR
Address
Don’t Care
tRPC
tRAH
Don’t Care
Row
Row
Don’t Care
W
Hi-Z
DQ0 – DQ15
Don’t Care
OE
NOTE A: Both LCAS and UCAS must be high.
Figure 13. RAS-Only Refresh-Cycle Timing
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23
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PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
Memory Cycle
tRP
tRP
tRAS
tRAS
RAS
tCHR
tCAS
xCAS
tCAH
tASC
tRAH
tASR
Address
Row
Col
Don’t Care
tWRH
tWRP
tWRH
tRRH
tWRP
tRAC
W
tCAC
tWEZ
tREZ
tCEZ
tAA
Valid Data Out
DQ0 – DQ15
tCLZ
tOEZ
tOEA
OE
Figure 14. Hidden-Refresh-Cycle (Read) Timing
24
tWRH
tWRP
tRCS
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PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
Refresh Cycle
tRP
tRAS
tRP
tRAS
RAS
tCHR
tCAS
xCAS
tCAH
tASC
tRAH
tASR
Row
Address
Don’t Care
Col
tWRH
tWRP
tWCS
tWP
W
tWCH
tDH
tDS
DQ0 – DQ15
Don’t Care
Valid Data
Don’t Care
OE
Figure 15. Hidden-Refresh Cycle (Write) Timing
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25
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SMKS892C – AUGUST 1996 – REVISED SEPTEMBER 1997
PARAMETER MEASUREMENT INFORMATION
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
xCAS
tWRP
tWRH
Don’t Care
W
Address
Don’t Care
OE
Don’t Care
Hi-Z
DQ0 – DQ15
NOTE A: Any xCAS can be used. If both UCAS and LCAS are used, both must satisfy tCSR and tCHR.
Figure 16. Automatic (xCBR) Refresh-Cycle Timing
device symbolization (TMS418169A illustrated)
TI
-SS
Speed ( - 50, - 60, - 70)
TMS418169A
DZ
Package Code
W
E
Y
M LLLL P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
26
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MECHANICAL DATA
DGE (R-PDSO-G44/50)
PLASTIC SMALL-OUTLINE PACKAGE
0.018 (0,45)
0.012 (0,30)
0.031 (0,80)
50
0.006 (0,16) M
26
0.471 (11,96)
0.455 (11,56)
0.404 (10,26)
0.396 (10,06)
1
25
0.006 (0,15) NOM
0.829 (21,05)
0.821 (20,85)
Gage Plane
0.010 (0,25)
0°– 5°
0.024 (0,60)
0.016 (0,40)
Seating Plane
0.047 (1,20) MAX
0.002 (0,05) MIN
0.004 (0,10)
4040070-4 / C 4/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
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27
TMS418169A, TMS428169A
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SMKS892C – AUGUST 1996 – REVISED SEPTEMBER 1997
MECHANICAL DATA
DZ (R-PDSO-J42)
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
1.080 (27,43)
1.070 (27,18)
42
22
0.445 (11,30)
0.435 (11,05)
0,405 (10,29)
0.395 (10,03)
1
21
0.032 (0,81)
0.026 (0,66)
0.148 (3,76)
0.128 (3,25)
0.106 (2,69) NOM
Seating Plane
0.020 (0,51)
0.016 (0,41)
0.004 (0,10)
0.007 (0,18) M
0.380 (9,65)
0.360 (9,14)
0.008 (0,20) NOM
0.050 (1,27)
4040094-6 / C 4/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
28
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IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
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