Low Cost Low Power Instrumentation Amplifier AD620 FEATURES CONNECTION DIAGRAM APPLICATIONS Weigh scales ECG and medical instrumentation Transducer interface Data acquisition systems Industrial process controls Battery-powered and portable equipment 1 8 –IN 2 7 +VS +IN 3 6 –VS 4 AD620 RG OUTPUT 5 REF TOP VIEW Figure 1. 8-Lead PDIP (N), CERDIP (Q), and SOIC (R) Packages PRODUCT DESCRIPTION The AD620 is a low cost, high accuracy instrumentation amplifier that requires only one external resistor to set gains of 1 to 10,000. Furthermore, the AD620 features 8-lead SOIC and DIP packaging that is smaller than discrete designs and offers lower power (only 1.3 mA max supply current), making it a good fit for battery-powered, portable (or remote) applications. The AD620, with its high accuracy of 40 ppm maximum nonlinearity, low offset voltage of 50 µV max, and offset drift of 0.6 µV/°C max, is ideal for use in precision data acquisition systems, such as weigh scales and transducer interfaces. Furthermore, the low noise, low input bias current, and low power of the AD620 make it well suited for medical applications, such as ECG and noninvasive blood pressure monitors. The low input bias current of 1.0 nA max is made possible with the use of Superϐeta processing in the input stage. The AD620 works well as a preamplifier due to its low input voltage noise of 9 nV/√Hz at 1 kHz, 0.28 µV p-p in the 0.1 Hz to 10 Hz band, and 0.1 pA/√Hz input current noise. Also, the AD620 is well suited for multiplexed applications with its settling time of 15 µs to 0.01%, and its cost is low enough to enable designs with one in-amp per channel. 30,000 10,000 3 OP AMP IN-AMP (3 OP-07s) RTI VOLTAGE NOISE (0.1 – 10Hz) (µV p-p) 1,000 20,000 15,000 AD620A 10,000 RG TYPICAL STANDARD BIPOLAR INPUT IN-AMP 100 G = 100 10 AD620 SUPERβETA BIPOLAR INPUT IN-AMP 1 5,000 0 0 5 10 SUPPLY CURRENT (mA) 15 20 Figure 2. Three Op Amp IA Designs vs. AD620 0.1 1k 10k 100k 1M SOURCE RESISTANCE (Ω) 10M 100M 00775-0-003 25,000 00775-0-002 TOTAL ERROR, PPM OF FULL SCALE RG 00775-0-001 Easy to use Gain set with one external resistor (Gain range 1 to 10,000) Wide power supply range (±2.3 V to ±18 V) Higher performance than 3 op amp IA designs Available in 8-lead DIP and SOIC packaging Low power, 1.3 mA max supply current Excellent dc performance (B grade) 50 µV max, input offset voltage 0.6 µV/°C max, input offset drift 1.0 nA max, input bias current 100 dB min common-mode rejection ratio (G = 10) Low noise 9 nV/√Hz @ 1 kHz, input voltage noise 0.28 µV p-p noise (0.1 Hz to 10 Hz) Excellent ac specifications 120 kHz bandwidth (G = 100) 15 µs settling time to 0.01% Figure 3. Total Voltage Noise vs. Source Resistance Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD620 TABLE OF CONTENTS Specifications .....................................................................................3 Input Protection ..........................................................................16 Absolute Maximum Ratings ............................................................5 RF Interference............................................................................16 ESD Caution ..................................................................................5 Common-Mode Rejection.........................................................17 Typical Performance Characteristics ..............................................7 Grounding....................................................................................17 Theory of Operation .......................................................................13 Ground Returns for Input Bias Currents.................................18 Gain Selection..............................................................................16 Outline Dimensions........................................................................19 Input and Output Offset Voltage ..............................................16 Ordering Guide ...........................................................................20 Reference Terminal .....................................................................16 REVISION HISTORY 12/04—Rev. F to Rev. G 7/03—Data Sheet changed from REV. E to REV. F Updated Format.................................................................. Universal Edit to FEATURES............................................................................1 Change to Features............................................................................1 Changes to SPECIFICATIONS .......................................................2 Change to Product Description.......................................................1 Removed AD620CHIPS from ORDERING GUIDE ...................4 Changes to Specifications.................................................................3 Removed METALLIZATION PHOTOGRAPH...........................4 Added Metallization Photograph....................................................4 Replaced TPCs 1–3 ...........................................................................5 Replaced Figure 4-Figure 6 ..............................................................6 Replaced TPC 12 ...............................................................................6 Replaced Figure 15 ............................................................................7 Replaced TPC 30 ...............................................................................9 Replaced Figure 33 ..........................................................................10 Replaced TPCs 31 and 32...............................................................10 Replaced Figure 34 and Figure 35.................................................10 Replaced Figure 4 ............................................................................10 Replaced Figure 37 ..........................................................................10 Changes to Table I...........................................................................11 Changes to Table 3 ..........................................................................13 Changes to Figures 6 and 7 ............................................................12 Changes to Figure 41 and Figure 42 .............................................14 Changes to Figure 8 ........................................................................13 Changes to Figure 43 ......................................................................15 Edited INPUT PROTECTION section........................................13 Change to Figure 44 ........................................................................17 Added new Figure 9........................................................................13 Changes to Input Protection section ............................................15 Changes to RF INTERFACE section ............................................14 Deleted Figure 9...............................................................................15 Edit to GROUND RETURNS FOR INPUT BIAS CURRENTS section...............................................................................................15 Changes to RF Interference section ..............................................15 Edit to Ground Returns for Input Bias Currents section...........17 Updated OUTLINE DIMENSIONS .............................................16 Added AD620CHIPS to Ordering Guide ....................................19 Rev. G | Page 2 of 20 AD620 SPECIFICATIONS Typical @ 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted. Table 1. AD620A Parameter GAIN Gain Range Gain Error2 G=1 G = 10 G = 100 G = 1000 Nonlinearity G = 1–1000 G = 1–100 Gain vs. Temperature VOLTAGE OFFSET Input Offset, VOSI Overtemperature Average TC Output Offset, VOSO Overtemperature Average TC Offset Referred to the Input vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Overtemperature Average TC Input Offset Current Overtemperature Average TC INPUT Input Impedance Differential Common-Mode Input Voltage Range3 Overtemperature Overtemperature Conditions Min G = 1 + (49.4 kΩ/RG) 1 VOUT = ±10 V VOUT = −10 V to +10 V RL = 10 kΩ RL = 2 kΩ Typ AD620B Max Min 10,000 1 Typ Max Min 10,000 1 AD620S1 Typ Max Unit 10,000 0.03 0.15 0.15 0.40 0.10 0.30 0.30 0.70 0.01 0.10 0.10 0.35 0.02 0.15 0.15 0.50 0.03 0.15 0.15 0.40 0.10 0.30 0.30 0.70 % % % % 10 10 40 95 10 10 40 95 10 10 40 95 ppm ppm 10 −50 ppm/°C ppm/°C 125 µV 225 µV G=1 Gain >12 (Total RTI Error = VOSI + VOSO/G) VS = ±5 V 30 to ± 15 V VS = ±5 V to ± 15 V VS = ±5 V 0.3 to ± 15 V VS = ±15 V 400 VS = ± 5 V VS = ±5 V to ± 15 V VS = ±5 V 5.0 to ± 15 V 10 −50 10 −50 125 15 185 50 30 85 1.0 0.1 0.6 0.3 1.0 µV/°C 1000 1500 2000 200 500 750 1000 400 1000 1500 2000 µV µV µV 15 2.5 7.0 5.0 15 µV/°C VS = ±2.3 V to ±18 V 80 95 110 110 100 120 140 140 0.5 3.0 0.3 VS = ±2.3 V −VS + 1.9 to ±5 V −VS + 2.1 VS = ± 5 V −VS + 1.9 to ±18 V −VS + 2.1 80 100 120 120 2.0 2.5 100 120 140 140 0.5 3.0 0.3 1.0 1.5 80 95 110 110 1.0 1.5 100 120 140 140 0.5 8.0 0.3 0.5 0.75 1.5 1.5 8.0 10||2 10||2 10||2 10||2 10||2 10||2 dB dB dB dB 2 4 1.0 2.0 nA nA pA/°C nA nA pA/°C +VS − 1.2 −VS + 1.9 +VS − 1.2 −VS + 1.9 +VS − 1.2 GΩ_pF GΩ_pF V +VS − 1.3 +VS − 1.4 −VS + 2.1 −VS + 1.9 +VS − 1.3 +VS − 1.4 −VS + 2.1 −VS + 1.9 +VS − 1.3 +VS − 1.4 V V +VS − 1.4 −VS + 2.1 +VS + 2.1 −VS + 2.3 +VS − 1.4 V Rev. G | Page 3 of 20 AD620 AD620A AD620B Parameter Conditions Min Typ Max Common-Mode Rejection Ratio DC to 60 Hz with 1 kΩ Source Imbalance VCM = 0 V to ± 10 V G=1 73 90 G = 10 93 110 G = 100 110 130 G = 1000 110 130 OUTPUT Output Swing RL = 10 kΩ VS = ±2.3 V −VS + +VS − 1.2 to ± 5 V 1.1 Overtemperature −VS + 1.4 +VS − 1.3 VS = ±5 V −VS + 1.2 +VS − 1.4 to ± 18 V Overtemperature −VS + 1.6 +VS – 1.5 Short Circuit Current ±18 DYNAMIC RESPONSE Small Signal –3 dB Bandwidth G=1 1000 G = 10 800 G = 100 120 G = 1000 12 Slew Rate 0.75 1.2 Settling Time to 0.01% 10 V Step G = 1–100 15 G = 1000 150 NOISE Voltage Noise, 1 kHz Total RTI Noise = (e 2ni ) + (e / G)2 Min Typ 80 100 120 120 90 110 130 130 Max Min AD620S1 Typ Max 73 93 110 110 90 110 130 130 Unit dB dB dB dB −VS + 1.1 +VS − 1.2 −VS + 1.1 +VS − 1.2 V −VS + 1.4 −VS + 1.2 +VS − 1.3 +VS − 1.4 −VS + 1.6 −VS + 1.2 +VS − 1.3 +VS − 1.4 V V +VS – 1.5 –VS + 2.3 +VS – 1.5 −VS + 1.6 0.75 ±18 ±18 V mA 1000 800 120 12 1.2 1000 800 120 12 1.2 kHz kHz kHz kHz V/µs 15 150 µs µs 0.75 15 150 no Input, Voltage Noise, eni Output, Voltage Noise, eno RTI, 0.1 Hz to 10 Hz G=1 G = 10 G = 100–1000 Current Noise 0.1 Hz to 10 Hz REFERENCE INPUT RIN IIN Voltage Range Gain to Output POWER SUPPLY Operating Range4 Quiescent Current 9 72 3.0 0.55 0.28 100 10 f = 1 kHz 20 50 VIN+, VREF = 0 −VS + 1.6 1 ± 0.0001 ±2.3 VS = ±2.3 V to ±18 V Overtemperature TEMPERATURE RANGE For Specified Performance 13 100 60 +VS − 1.6 0.9 ±18 1.3 1.1 1.6 −40 to +85 9 72 13 100 9 72 13 100 nV/√Hz nV/√Hz 3.0 0.55 0.28 100 10 6.0 0.8 0.4 3.0 0.55 0.28 100 10 6.0 0.8 0.4 µV p-p µV p-p µV p-p fA/√Hz pA p-p 20 50 −VS + 1.6 1 ± 0.0001 ±2.3 −40 to +85 1 See Analog Devices military data sheet for 883B tested specifications. Does not include effects of external resistor RG. 3 One input grounded. G = 1. 4 This is defined as the same supply range that is used to specify PSR. 2 Rev. G | Page 4 of 20 60 +VS − 1.6 0.9 ±18 1.3 1.1 1.6 20 50 60 +VS − 1.6 kΩ µA V 0.9 ±18 1.3 V mA 1.1 1.6 mA −VS + 1.6 1 ± 0.0001 ±2.3 −55 to +125 °C AD620 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Internal Power Dissipation1 Input Voltage (Common-Mode) Differential Input Voltage Output Short-Circuit Duration Storage Temperature Range (Q) Storage Temperature Range (N, R) Operating Temperature Range AD620 (A, B) AD620 (S) Lead Temperature Range (Soldering 10 seconds) 1 Rating ±18 V 650 mW ±VS 25 V Indefinite −65°C to +150°C −65°C to +125°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. −40°C to +85°C −55°C to +125°C 300°C Specification is for device in free air: 8-Lead Plastic Package: θJA = 95°C 8-Lead CERDIP Package: θJA = 110°C 8-Lead SOIC Package: θJA = 155°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. G | Page 5 of 20 00775-0-004 AD620 Figure 4. Metallization Photograph. Dimensions shown in inches and (mm). Contact sales for latest dimensions. Rev. G | Page 6 of 20 AD620 TYPICAL PERFORMANCE CHARACTERISTICS (@ 25°C, VS = ±15 V, RL = 2 kΩ, unless otherwise noted.) 2.0 50 SAMPLE SIZE = 360 1.5 INPUT BIAS CURRENT (nA) PERCENTAGE OF UNITS 40 30 20 10 1.0 +IB –I B 0.5 0 –0.5 –1.0 –40 0 40 80 INPUT OFFSET VOLTAGE (µV) 175 00775-0-008 –80 5 00775-0-009 0 00775-0-005 –1.5 –2.0 –75 –25 25 75 TEMPERATURE (°C) 125 Figure 8. Input Bias Current vs. Temperature Figure 5. Typical Distribution of Input Offset Voltage 2.0 50 CHANGE IN OFFSET VOLTAGE (µV) SAMPLE SIZE = 850 PERCENTAGE OF UNITS 40 30 20 0 –1200 –600 0 600 1200 INPUT BIAS CURRENT (pA) 00775-0-006 10 1.5 1.0 0.5 0 0 1 2 3 WARM-UP TIME (Minutes) 4 Figure 9. Change in Input Offset Voltage vs. Warm-Up Time Figure 6. Typical Distribution of Input Bias Current 1000 50 SAMPLE SIZE = 850 GAIN = 1 VOLTAGE NOISE (nV/ Hz) 30 20 10 100 GAIN = 10 10 GAIN = 100, 1,000 0 –400 –200 0 200 400 INPUT OFFSET CURRENT (pA) 1 1 Figure 7. Typical Distribution of Input Offset Current 10 100 1k FREQUENCY (Hz) 10k 100k 00775-0-010 GAIN = 1000 BW LIMIT 00775-0-007 PERCENTAGE OF UNITS 40 Figure 10. Voltage Noise Spectral Density vs. Frequency (G = 1−1000) Rev. G | Page 7 of 20 AD620 10 1 10 100 FREQUENCY (Hz) 1000 00775-0-014 100 00775-0-011 CURRENT NOISE (fA/ Hz) 1000 Figure 14. 0.1 Hz to 10 Hz Current Noise, 5 pA/Div Figure 11. Current Noise Spectral Density vs. Frequency TOTAL DRIFT FROM 25°C TO 85°C, RTI (µV) 10,000 FET INPUT IN-AMP 1000 AD620A 100 10 1k 10k 100k 1M SOURCE RESISTANCE (Ω) 10M 00775-0-015 TIME (1 SEC/DIV) 00775-0-012 RTI NOISE (2.0µV/DIV) 100,000 Figure 15. Total Drift vs. Source Resistance Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1) 160 140 RTI NOISE (0.1µV/DIV) 120 G = 1000 G = 100 G = 10 CMR (dB) 100 G=1 80 60 40 Figure 13. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000) 0 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k 1M 00775-0-016 00775-0-013 TIME (1 SEC/DIV) 20 Figure 16. Typical CMR vs. Frequency, RTI, Zero to 1 kΩ Source Imbalance Rev. G | Page 8 of 20 AD620 180 35 160 30 G = 10, 100, 1000 G = 1000 G = 100 80 G = 10 60 G=1 15 10 5 20 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k 1M 00775-0-017 G = 1000 1k 10k 100k FREQUENCY (Hz) Figure 17. Positive PSR vs. Frequency, RTI (G = 1−1000) 160 –0.5 INPUT VOLTAGE LIMIT (V) (REFERRED TO SUPPLY VOLTAGES) +VS –0.0 140 PSR (dB) 120 100 G = 1000 80 G = 100 60 G = 10 G=1 10 100 1k FREQUENCY (Hz) 10k 100k 1M 00775-0-018 40 1 –1.5 +1.5 +1.0 +0.5 0 5 10 15 SUPPLY VOLTAGE ± Volts 20 20 Figure 21. Input Voltage Range vs. Supply Voltage, G = 1 1000 OUTPUT VOLTAGE SWING (V) (REFERRED TO SUPPLY VOLTAGES) +VS –0.0 100 10 1 1k 10k 100k FREQUENCY (Hz) 1M 10M 00775-0-019 GAIN (V/V) –1.0 –VS +0.0 Figure 18. Negative PSR vs. Frequency, RTI (G = 1−1000) 0.1 100 1M Figure 20. Large Signal Frequency Response 180 20 0.1 G = 100 0 00775-0-020 40 G=1 20 00775-0-021 100 25 00775-0-022 PSR (dB) 120 BW LIMIT OUTPUT VOLTAGE (V p-p) 140 –0.5 RL = 10kΩ –1.0 RL = 2kΩ –1.5 +1.5 RL = 2kΩ +1.0 RL = 10kΩ +0.5 –VS +0.0 0 5 10 15 SUPPLY VOLTAGE ± Volts Figure 22. Output Voltage Swing vs. Supply Voltage, G = 10 Figure 19. Gain vs. Frequency Rev. G | Page 9 of 20 AD620 .... .... .... .... .... .... .... .... .... .... VS = ±15V G = 10 20 10 0 100 1k LOAD RESISTANCE (Ω) 10k 00775-0-023 0 00775-0-026 .... .... .... .... .... .... .... .... .... .... Figure 26. Large Signal Response and Settling Time, G = 10 (0.5 mV = 0.01%) Figure 23. Output Voltage Swing vs. Load Resistance .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... 00775-0-027 00775-0-024 .... .... .... .... .... .... .... .... .... .... Figure 24. Large Signal Pulse Response and Settling Time G = 1 (0.5 mV = 0.01%) Figure 27. Small Signal Response, G = 10, RL = 2 kΩ, CL = 100 pF .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... Figure 25. Small Signal Response, G = 1, RL = 2 kΩ, CL = 100 pF 00775-0-030 00775-0-025 OUTPUT VOLTAGE SWING (V p-p) 30 Figure 28. Large Signal Response and Settling Time, G = 100 (0.5 mV = 0.01%) Rev. G | Page 10 of 20 AD620 20 .... .... .... .... .... .... .... .... ........ SETTLING TIME (µs) 15 TO 0.01% TO 0.1% 10 00775-0-029 0 0 Figure 29. Small Signal Pulse Response, G = 100, RL = 2 kΩ, CL = 100 pF 5 10 OUTPUT STEP SIZE (V) 20 15 00775-0-032 5 .... .... .... .... .... .... .... .... ........ Figure 32. Settling Time vs. Step Size (G = 1) 1000 SETTLING TIME (µs) .... .... .... .... .... .... .... .... .... .... 100 10 1 1 10 100 1000 GAIN Figure 33. Settling Time to 0.01% vs. Gain, for a 10 V Step Figure 30. Large Signal Response and Settling Time, G = 1000 (0.5 mV = 0.01% ) .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... ........ .... .... .... .... .... .... .... .... .... .... 00775-0-031 00775-0-034 .... .... .... .... .... .... .... .... ........ Figure 31. Small Signal Pulse Response, G = 1000, RL = 2 kΩ, CL = 100 pF Rev. G | Page 11 of 20 Figure 34. Gain Nonlinearity, G = 1, RL = 10 kΩ (10 µV = 1 ppm) 00775-0-033 00775-0-030 .... .... .... .... .... .... .... .... .... .... AD620 10kΩ * INPUT 10V p-p .... .... .... .... .... .... .... .... ........ 1kΩ 10T 10kΩ 100k Ω VOUT +VS 11kΩ 1kΩ 2 100 Ω 7 1 G = 1000 G=1 AD620 G = 100 G = 10 .... .... .... .... .... .... .... .... ........ 49.9Ω 499 Ω 5.49k Ω 6 5 00775-0-035 8 3 –VS *ALL RESISTORS 1% TOLERANCE Figure 35. Gain Nonlinearity, G = 100, RL = 10 kΩ (100 µV = 10 ppm) Figure 37. Settling Time Test Circuit .... .... .... .... .... .... .... .... ........ 00775-0-036 .... .... .... .... .... .... .... .... ........ Figure 36. Gain Nonlinearity, G = 1000, RL = 10 kΩ (1 mV = 100 ppm) Rev. G | Page 12 of 20 00775-0-037 4 AD620 THEORY OF OPERATION I1 20µA VB I2 20µA A1 The input transistors Q1 and Q2 provide a single differentialpair bipolar input for high precision (Figure 38), yet offer 10× lower input bias current thanks to Superϐeta processing. Feedback through the Q1-A1-R1 loop and the Q2-A2-R2 loop maintains constant collector current of the input devices Q1 and Q2, thereby impressing the input voltage across the external gain setting resistor RG. This creates a differential gain from the inputs to the A1/A2 outputs given by G = (R1 + R2)/RG + 1. The unity-gain subtractor, A3, removes any common-mode signal, yielding a single-ended output referred to the REF pin potential. A2 10kΩ C2 C1 10kΩ A3 R3 400Ω R1 R2 Q1 Q2 R4 400Ω RG GAIN SENSE OUTPUT 10kΩ REF +IN GAIN SENSE –VS 00775-0-038 – IN 10kΩ Figure 38. Simplified Schematic of AD620 The AD620 is a monolithic instrumentation amplifier based on a modification of the classic three op amp approach. Absolute value trimming allows the user to program gain accurately (to 0.15% at G = 100) with only one resistor. Monolithic construction and laser wafer trimming allow the tight matching and tracking of circuit components, thus ensuring the high level of performance inherent in this circuit. The value of RG also determines the transconductance of the preamp stage. As RG is reduced for larger gains, the transconductance increases asymptotically to that of the input transistors. This has three important advantages: (a) Open-loop gain is boosted for increasing programmed gain, thus reducing gain related errors. (b) The gain-bandwidth product (determined by C1 and C2 and the preamp transconductance) increases with programmed gain, thus optimizing frequency response. (c) The input voltage noise is reduced to a value of 9 nV/√Hz, determined mainly by the collector current and base resistance of the input devices. The internal gain resistors, R1 and R2, are trimmed to an absolute value of 24.7 kΩ, allowing the gain to be programmed accurately with a single external resistor. The gain equation is then G= 49.4 kΩ RG = RG +1 49.4 kΩ G−1 Make vs. Buy: a Typical Bridge Application Error Budget The AD620 offers improved performance over “homebrew” three op amp IA designs, along with smaller size, fewer components, and 10× lower supply current. In the typical application, shown in Figure 39, a gain of 100 is required to amplify a bridge output of 20 mV full-scale over the industrial temperature range of −40°C to +85°C. Table 3 shows how to calculate the effect various error sources have on circuit accuracy. Rev. G | Page 13 of 20 AD620 Note that for the homebrew circuit, the OP07 specifications for input voltage offset and noise have been multiplied by √2. This is because a three op amp type in-amp has two op amps at its inputs, both contributing to the overall input error. Regardless of the system in which it is being used, the AD620 provides greater accuracy at low power and price. In simple systems, absolute accuracy and drift errors are by far the most significant contributors to error. In more complex systems with an intelligent processor, an autogain/autozero cycle will remove all absolute accuracy and drift errors, leaving only the resolution errors of gain, nonlinearity, and noise, thus allowing full 14-bit accuracy. 10V 10kΩ * R = 350Ω 10kΩ ** REFERENCE PRECISION BRIDGE TRANSDUCER AD620A MONOLITHIC INSTRUMENTATION AMPLIFIER, G = 100 SUPPLY CURRENT = 1.3mA MAX 100Ω ** 10kΩ ** OP07D 00775-0-040 R = 350Ω 00775-0-039 R = 350Ω 10kΩ * OP07D AD620A OP07D 10kΩ * 10kΩ* "HOMEBREW" IN-AMP, G = 100 *0.02% RESISTOR MATCH, 3ppm/°C TRACKING **DISCRETE 1% RESISTOR, 100ppm/ °C TRACKING SUPPLY CURRENT = 15mA MAX Figure 39. Make vs. Buy Table 3. Make vs. Buy Error Budget Error Source ABSOLUTE ACCURACY at TA = 25°C Input Offset Voltage, µV Output Offset Voltage, µV Input Offset Current, nA CMR, dB DRIFT TO 85°C Gain Drift, ppm/°C Input Offset Voltage Drift, µV/°C Output Offset Voltage Drift, µV/°C RESOLUTION Gain Nonlinearity, ppm of Full Scale Typ 0.1 Hz to 10 Hz Voltage Noise, µV p-p Error, ppm of Full Scale AD620 Homebrew AD620 Circuit Calculation “Homebrew” Circuit Calculation 125 µV/20 mV 1000 µV/100 mV/20 mV 2 nA ×350 Ω/20 mV 110 dB(3.16 ppm) ×5 V/20 mV (150 µV × √2)/20 mV ((150 µV × 2)/100)/20 mV (6 nA ×350 Ω)/20 mV (0.02% Match × 5 V)/20 mV/100 6,250 500 18 791 10,607 150 53 500 Total Absolute Error 7,559 11,310 100 ppm/°C Track × 60°C (2.5 µV/°C × √2 × 60°C)/20 mV (2.5 µV/°C × 2 × 60°C)/100 mV/20 mV 3,600 3,000 450 6,000 10,607 150 Total Drift Error 7,050 16,757 40 14 54 14,663 40 27 67 28,134 (50 ppm + 10 ppm) ×60°C 1 µV/°C × 60°C/20 mV 15 µV/°C × 60°C/100 mV/20 mV 40 ppm 0.28 µV p-p/20 mV 40 ppm (0.38 µV p-p × √2)/20 mV Total Resolution Error Grand Total Error G = 100, VS = ±15 V. (All errors are min/max and referred to input.) Rev. G | Page 14 of 20 00775-0-041 R = 350Ω RG 499Ω AD620 5V 3kΩ 3kΩ 3kΩ 3kΩ 20kΩ 7 3 REF 8 AD620B G = 100 499Ω 6 IN 10kΩ 5 1 ADC 4 2 20kΩ 1.7mA DIGITAL DATA OUTPUT AD705 0.10mA 00775-0-042 1.3mA MAX AGND 0.6mA MAX Figure 40. A Pressure Monitor Circuit that Operates on a 5 V Single Supply Pressure Measurement Medical ECG Although useful in many bridge applications, such as weigh scales, the AD620 is especially suitable for higher resistance pressure sensors powered at lower voltages where small size and low power become more significant. The low current noise of the AD620 allows its use in ECG monitors (Figure 41) where high source resistances of 1 MΩ or higher are not uncommon. The AD620’s low power, low supply voltage requirements, and space-saving 8-lead mini-DIP and SOIC package offerings make it an excellent choice for batterypowered data recorders. Figure 40 shows a 3 kΩ pressure transducer bridge powered from 5 V. In such a circuit, the bridge consumes only 1.7 mA. Adding the AD620 and a buffered voltage divider allows the signal to be conditioned for only 3.8 mA of total supply current. Small size and low cost make the AD620 especially attractive for voltage output pressure transducers. Since it delivers low noise and drift, it will also serve applications such as diagnostic noninvasive blood pressure measurement. R1 10kΩ R4 1MΩ The value of capacitor C1 is chosen to maintain stability of the right leg drive loop. Proper safeguards, such as isolation, must be added to this circuit to protect the patient from possible harm. +3V PATIENT/CIRCUIT PROTECTION/ISOLATION C1 Furthermore, the low bias currents and low current noise, coupled with the low voltage noise of the AD620, improve the dynamic range for better performance. R3 24.9kΩ R2 24.9kΩ RG 8.25kΩ AD620A G=7 0.03Hz HIGHPASS FILTER G = 143 OUTPUT 1V/mV OUTPUT AMPLIFIER –3V Figure 41. A Medical ECG Monitor Circuit Rev. G | Page 15 of 20 00775-0-043 AD705J AD620 Precision V-I Converter INPUT AND OUTPUT OFFSET VOLTAGE The AD620, along with another op amp and two resistors, makes a precision current source (Figure 42). The op amp buffers the reference terminal to maintain good CMR. The output voltage, VX, of the AD620 appears across R1, which converts it to a current. This current, less only the input bias current of the op amp, then flows out to the load. The low errors of the AD620 are attributed to two sources, input and output errors. The output error is divided by G when referred to the input. In practice, the input errors dominate at high gains, and the output errors dominate at low gains. The total VOS for a given gain is calculated as Total Error RTI = input error + (output error/G) +VS VIN+ Total Error RTO = (input error × G) + output error 7 3 8 REFERENCE TERMINAL + VX – AD620 RG 6 The reference terminal potential defines the zero output voltage and is especially useful when the load does not share a precise ground with the rest of the system. It provides a direct means of injecting a precise offset to the output, with an allowable range of 2 V within the supply voltages. Parasitic resistance should be kept to a minimum for optimum CMR. R1 1 2 4 I –VS I L= Vx R1 = L AD705 [(V IN+ ) – (V IN– )] G R1 LOAD 00775-0-044 VIN– 5 Figure 42. Precision Voltage-to-Current Converter (Operates on 1.8 mA, ±3 V) GAIN SELECTION The AD620’s gain is resistor-programmed by RG, or more precisely, by whatever impedance appears between Pins 1 and 8. The AD620 is designed to offer accurate gains using 0.1% to 1% resistors. Table 4 shows required values of RG for various gains. Note that for G = 1, the RG pins are unconnected (RG = ∞). For any arbitrary gain, RG can be calculated by using the formula: RG = 49.4 kΩ INPUT PROTECTION The AD620 features 400 Ω of series thin film resistance at its inputs and will safely withstand input overloads of up to ±15 V or ±60 mA for several hours. This is true for all gains and power on and off, which is particularly important since the signal source and amplifier may be powered separately. For longer time periods, the current should not exceed 6 mA (IIN ≤ VIN/400 Ω). For input overloads beyond the supplies, clamping the inputs to the supplies (using a low leakage diode such as an FD333) will reduce the required resistance, yielding lower noise. RF INTERFERENCE G −1 To minimize gain error, avoid high parasitic resistance in series with RG; to minimize gain drift, RG should have a low TC—less than 10 ppm/°C—for the best performance. All instrumentation amplifiers rectify small out of band signals. The disturbance may appear as a small dc voltage offset. High frequency signals can be filtered with a low pass R-C network placed at the input of the instrumentation amplifier. Figure 43 demonstrates such a configuration. The filter limits the input signal according to the following relationship: Table 4. Required Values of Gain Resistors 1% Std Table Value of RG(Ω) 49.9 k 12.4 k 5.49 k 2.61 k 1.00 k 499 249 100 49.9 Calculated Gain 1.990 4.984 9.998 19.93 50.40 100.0 199.4 495.0 991.0 0.1% Std Table Value of RG(Ω ) 49.3 k 12.4 k 5.49 k 2.61 k 1.01 k 499 249 98.8 49.3 Calculated Gain 2.002 4.984 9.998 19.93 49.91 100.0 199.4 501.0 1,003.0 FilterFreq DIFF = FilterFreq CM = 1 2 πR(2C D + C C ) 1 2 πRC C where CD ≥10CC. CD affects the difference signal. CC affects the common-mode signal. Any mismatch in R × CC will degrade the AD620’s CMRR. To avoid inadvertently reducing CMRR-bandwidth performance, make sure that CC is at least one magnitude smaller than CD. The effect of mismatched CCs is reduced with a larger CD:CC ratio. Rev. G | Page 16 of 20 AD620 +15V +VS CD CC 100Ω +IN + AD620 499Ω –IN AD648 – VOUT RG 100Ω REF AD620 VOUT –VS REFERENCE 1 0µ F 0.1µ F –15V 00775-0-046 R CC 00775-0-045 R – INPUT 1 0µ F 0.1µ F + INPUT –VS Figure 44. Differential Shield Driver Figure 43. Circuit to Attenuate RF Interference COMMON-MODE REJECTION +VS Instrumentation amplifiers, such as the AD620, offer high CMR, which is a measure of the change in output voltage when both inputs are changed by equal amounts. These specifications are usually given for a full-range input voltage change and a specified source imbalance. – INPUT RG 2 100Ω AD548 RG 2 AD620 VOUT 00775-0-047 REFERENCE For optimal CMR, the reference terminal should be tied to a low impedance point, and differences in capacitance and resistance should be kept to a minimum between the two inputs. In many applications, shielded cables are used to minimize noise; for best CMR over frequency, the shield should be properly driven. Figure 44 and Figure 45 show active data guards that are configured to improve ac common-mode rejections by “bootstrapping” the capacitances of input cable shields, thus minimizing the capacitance mismatch between the inputs. + INPUT –VS Figure 45. Common-Mode Shield Driver GROUNDING Since the AD620 output voltage is developed with respect to the potential on the reference terminal, it can solve many grounding problems by simply tying the REF pin to the appropriate “local ground.” To isolate low level analog signals from a noisy digital environment, many data-acquisition components have separate analog and digital ground pins (Figure 46). It would be convenient to use a single ground line; however, current through ground wires and PC runs of the circuit card can cause hundreds of millivolts of error. Therefore, separate ground returns should be provided to minimize the current flow from the sensitive points to the system ground. These ground returns must be tied together at some point, usually best at the ADC package shown in Figure 46. ANALOG P.S. +15V C –15V 0.1µ F 0.1µ F DIGITAL P.S. C +5V 1µ F 1µ F 1µ F AD620 AD585 S/H AD574A ADC Figure 46. Basic Grounding Practice Rev. G | Page 17 of 20 DIGITAL DATA OUTPUT 00775-0-048 + AD620 GROUND RETURNS FOR INPUT BIAS CURRENTS +VS – INPUT Input bias currents are those currents necessary to bias the input transistors of an amplifier. There must be a direct return path for these currents. Therefore, when amplifying “floating” input sources, such as transformers or ac-coupled sources, there must be a dc path from each input to ground, as shown in Figure 47, Figure 48, and Figure 49. Refer to A Designer’s Guide to Instrumentation Amplifiers (free from Analog Devices) for more information regarding in-amp applications. AD620 RG VOUT LOAD REFERENCE + INPUT TO POWER SUPPLY GROUND +VS – INPUT 00775-0-050 –VS Figure 48. Ground Returns for Bias Currents with Thermocouple Inputs RG AD620 VOUT +VS – INPUT LOAD + INPUT REFERENCE –VS VOUT LOAD + INPUT Figure 47. Ground Returns for Bias Currents with Transformer-Coupled Inputs 100k Ω 100kΩ REFERENCE –VS TO POWER SUPPLY GROUND Figure 49. Ground Returns for Bias Currents with AC-Coupled Inputs Rev. G | Page 18 of 20 00775-0-051 TO POWER SUPPLY GROUND AD620 00775-0-049 RG AD620 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 1 4 5.00 (0.1968) 4.80 (0.1890) 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) PIN 1 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) MIN 0.015 (0.38) GAUGE PLANE 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX 0.005 (0.13) MIN 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 0.055 (1.40) MAX 8 5 0.310 (7.87) 0.220 (5.59) PIN 1 4 0.100 (2.54) BSC 0.320 (8.13) 0.290 (7.37) 0.405 (10.29) MAX 0.023 (0.58) 0.014 (0.36) 0.50 (0.0196) × 45° 0.25 (0.0099) 8° 0.25 (0.0098) 0° 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) Narrow Body (R-8) Dimensions shown in millimeters and (inches) Narrow Body (N-8). Dimensions shown in inches and (millimeters) 0.200 (5.08) 0.125 (3.18) 1.75 (0.0688) 1.35 (0.0532) Figure 52. 8-Lead Standard Small Outline Package [SOIC] Figure 50. 8-Lead Plastic Dual In-Line Package [PDIP] 0.200 (5.08) MAX 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MS-001-BA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. 1 4 COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 0.005 (0.13) MIN 5 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 8 4.00 (0.1574) 3.80 (0.1497) 1 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING 0.070 (1.78) PLANE 0.030 (0.76) 15° 0° 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 51. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters) Rev. G | Page 19 of 20 AD620 ORDERING GUIDE Model AD620AN AD620ANZ2 AD620BN AD620BNZ2 AD620AR AD620ARZ2 AD620AR-REEL AD620ARZ-REEL2 AD620AR-REEL7 AD620ARZ-REEL72 AD620BR AD620BRZ2 AD620BR-REEL AD620BRZ-RL2 AD620BR-REEL7 AD620BRZ-R72 AD620ACHIPS AD620SQ/883B 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −55°C to +125°C N = Plastic DIP; Q = CERDIP; R = SOIC. Z = Pb-free part. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00775–0–12/04(G) Rev. G | Page 20 of 20 Package Option1 N-8 N-8 N-8 N-8 R-8 R-8 13" REEL 13" REEL 7" REEL 7" REEL R-8 R-8 13" REEL 13" REEL 7" REEL 7" REEL Die Form Q-8