a FEATURES Enhanced Replacements for LF411 and TL081 AC PERFORMANCE Settles to 60.01% in 1.0 ms 16 V/ms min Slew Rate (AD711J) 3 MHz min Unity Gain Bandwidth (AD711J) Precision, Low Cost, High Speed, BiFET Op Amp AD711 CONNECTION DIAGRAMS TO-99 (H) Package Plastic Mini-DIP (N) Package Plastic Small Outline (R) and Cerdip (Q) Package DC PERFORMANCE 0.25 mV max Offset Voltage: (AD711C) 3 mV/8C max Drift: (AD711C) 200 V/mV min Open-Loop Gain (AD711K) 4 mV p-p max Noise, 0.1 Hz to 10 Hz (AD711C) Available in Plastic Mini-DIP, Plastic SO, Hermetic Cerdip, and Hermetic Metal Can Packages MIL-STD-883B Parts Available Available in Tape and Reel in Accordance with EIA-481A Standard Surface Mount (SOIC) Dual Version: AD712 Quad Version: AD713 PRODUCT DESCRIPTION The AD711 is a high speed, precision monolithic operational amplifier offering high performance at very modest prices. Its very low offset voltage and offset voltage drift are the results of advanced laser wafer trimming technology. These performance benefits allow the user to easily upgrade existing designs that use older precision BiFETs and, in many cases, bipolar op amps. The superior ac and dc performance of this op amp makes it suitable for active filter applications. With a slew rate of 16 V/µs and a settling time of 1 µs to ± 0.01%, the AD711 is ideal as a buffer for 12-bit D/A and A/D Converters and as a high-speed integrator. The settling time is unmatched by any similar IC amplifier. The combination of excellent noise performance and low input current also make the AD711 useful for photo diode preamps. Common-mode rejection of 88 dB and open loop gain of 400 V/mV ensure 12-bit performance even in high-speed unity gain buffer circuits. The AD711 is pinned out in a standard op amp configuration and is available in seven performance grades. The AD711J and AD711K are rated over the commercial temperature range of 0°C to +70°C. The AD711A, AD711B and AD711C are rated over the industrial temperature range of –40°C to +85°C. The AD711S and AD711T are rated over the military temperature range of –40°C to +125°C and are available processed to MILSTD-883B, Rev. C. Extended reliability PLUS screening is available, specified over the commercial and industrial temperature ranges. PLUS screening includes 168-hour burn-in, as well as other environmental and physical tests. The AD711 is available in an 8-pin plastic mini-DIP, small outline, cerdip, TO-99 metal can, or in chip form. PRODUCT HIGHLIGHTS 1. The AD711 offers excellent overall performance at very competitive prices. 2. Analog Devices’ advanced processing technology and with 100% testing guarantees a low input offset voltage (0.25 mV max, C grade, 2 mV max, J grade). Input offset voltage is specified in the warmed-up condition. Analog Devices’ laser wafer drift trimming process reduces input offset voltage drifts to 3 µV/°C max on the AD711C. 3. Along with precision dc performance, the AD711 offers excellent dynamic response. It settles to ± 0.01% in 1 µs and has a 100% tested minimum slew rate of 16 V/µs. Thus this device is ideal for applications such as DAC and ADC buffers which require a combination of superior ac and dc performance. 4. The AD711 has a guaranteed and tested maximum voltage noise of 4 µV p-p, 0.1 to 10 Hz (AD711C). 5. Analog Devices’ well-matched, ion-implanted JFETs ensure a guaranteed input bias current (at either input) of 25 pA max (AD711C) and an input offset current of 10 pA max (AD711C). Both input bias current and input offset current are guaranteed in the warmed-up condition. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD711–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (V = 615 V @ T = +258C unless otherwise noted) S Parameter Min INPUT OFFSET VOLTAGE1 Initial Offset TMIN to TMAX vs. Temp vs. Supply 76 TMIN to TMAX 76/76/76 Long-Term Stability INPUT BIAS CURRENT2 VCM = 0 V VCM = 0 V @ TMAX VCM = ± 10 V 7 95 10 3.0 16 4.0 200 20 1.0 0.0003 Min K/B/T Typ 0.2 2/1/1 3/2/2 20/20/20 5 100 80 80 Max Min 0.10 0.5 1.0 10 86 86 15 50 1.1/3.2/51 100 15 25 0.6/1.6/26 5 20 3.4 4.0 200 20 1.0 0.0003 18 1.2 C Typ 2 110 Max Units 0.25 0.45 5 mV mV µV/°C dB dB µV/Month 25 1.6 50 pA nA pA 10 0.65 pA nA 15 50 1.1/3.2/51 100 15 25 0.6/1.6/26 5 20 3.4 18 1.2 4.0 200 20 1.0 0.0003 1.2 MHz kHz V/µs µs % 3 × 1012i5.5 3 × 1012i5.5 3 × 1012i5.5 3 × 1012i5.5 3 × 1012i5.5 3 × 1012i5.5 ΩipF ΩipF ± 20 +14.5, –11.5 ± 20 +14.5, –11.5 ± 20 +14.5, –11.5 V –VS + 4 76 76/76/76 70 70/70/70 Max 15 20 INPUT IMPEDANCE Differential Common Mode INPUT VOLTAGE RANGE Differential3 Common-Mode Voltage4 TMIN to TMAX Common-Mode Rejection Ratio VCM = ± 10 V TMIN to TMAX VCM = ± 11 V TMIN to TMAX 0.3 15 INPUT OFFSET CURRENT VCM = 0 V VCM = 0 V @ TMAX FREQUENCY RESPONSE Small Signal Bandwidth Full Power Response Slew Rate Settling Time to 0.01% Total Harmonic Distortion J/A/S Typ A +VS – 2 88 84 84 80 –VS + 4 +VS – 2 88 84 84 80 80 80 76 74 +VS – 2 V –VS + 4 86 86 76 74 94 90 90 84 dB dB dB dB µV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz INPUT VOLTAGE NOISE 2 45 22 18 16 2 45 22 18 16 2 45 22 18 16 INPUT CURRENT NOISE 0.01 0.01 0.01 pA/√Hz 400 V/mV V/mV OPEN-LOOP GAIN 150 400 100/100/100 OUTPUT CHARACTERISTICS Voltage +13, –12.5 +13.9, –13.3 ± 12/± 12/612 +13.8, –13.1 Current 25 POWER SUPPLY Rated Performance Operating Range Quiescent Current 400 200 100 +13, –12.5 +13.9, –13.3 612 +13.8, –13.1 25 ± 15 64.5 2.5 200 100 +13, –12.5 +13.9, –13.3 612 +13.8, –13.1 25 ± 15 618 3.4 64.5 2.5 4 V V mA ± 15 618 3.0 64.5 2.5 618 2.8 V V mA NOTES 1 Input Offset Voltage specifications are guaranteed after 5 minutes of operation at T A = +25°C. 2 Bias Current specifications are guaranteed maximum at either input after 5 minutes of operation at T A = +25°C. For higher temperatures, the current doubles every 10°C. 3 Defined as voltage between inputs, such that neither exceeds ± 10 V from ground. 4 Typically exceeding –14.1 V negative common-mode voltage on either input results in an output phase reversal. Specifications subject to change without notice. –2– REV. A AD711 ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . . 500 mW Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS Storage Temperature Range (Q, H) . . . . . . . . –65°C to +150°C Storage Temperature Range (N) . . . . . . . . . . –65°C to +125°C Operating Temperature Range AD711J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C AD711A/B/C . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C AD711S/T . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C Model AD711AH AD711AQ AD711BH AD711BQ AD711CH AD711CQ AD711JN AD711JR AD711JR-REEL AD711JR-REEL7 AD711KN AD711KR AD711KR-REEL AD711KR-REEL7 AD711SCHIPS AD711SQ/883B AD711TQ/883B NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 8-Pin Plastic Package: θJC = 33°C/Watt; θJA = 100°C/Watt 8-Pin Cerdip Package: θJC = 22°C/Watt; θJA = 110°C/Watt 8-Pin Metal Can Package: θJC = 65°C/Watt; θJA = 150°C/Watt 3 For supply voltages less than ± 18 V, the absolute maximum input voltage is equal to the supply voltage. METALLIZATION PHOTOGRAPH Dimensions shown in inches and (mm) Contact factory for latest dimensions. REV. A –3– Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C –55°C to +125°C –55°C to +125°C –55°C to +125°C Package Description 8-Pin Metal Can 8-Pin Ceramic DIP 8-Pin Metal Can 8-Pin Ceramic DIP 8-Pin Metal Can 8-Pin Ceramic DIP 8-Pin Plastic DIP 8-Pin Plastic SOIC 8-Pin Plastic SOIC 8-Pin Plastic SOIC 8-Pin Plastic DIP 8-Pin Plastic SOIC 8-Pin Plastic SOIC 8-Pin Plastic SOIC Bare Die 8-Pin Ceramic DIP 8-Pin Ceramic DIP Package Option* H-08A Q-8 H-08A Q-8 H-08A Q-8 N-8 R-8 R-8 R-8 N-8 R-8 R-8 R-8 Q-8 Q-8 AD711–Typical Characteristics Figure 2. Output Voltage Swing vs. Supply Voltage Figure 3. Output Voltage Swing vs. Load Resistance Figure 4. Quiescent Current vs. Supply Voltage Figure 5. Input Bias Current vs. Temperature Figure 6. Output Impedance vs. Frequency Figure 7. Input Bias Current vs. Common Mode Voltage Figure 8. Short Circuit Current Limit vs. Temperature Figure 9. Unity Gain Bandwidth vs. Temperature Figure 1. Input Voltage Swing vs. Supply Voltage –4– REV. A AD711 Figure 10. Open-Loop Gain and Phase Margin vs. Frequency Figure 13. Common Mode Rejection vs. Frequency Figure 16. Total Harmonic Distortion vs. Frequency REV. A Figure 11. Open-Loop Gain vs. Supply Voltage Figure 14. Large Signal Frequency Response Figure 17. Input Noise Voltage Spectral Density –5– Figure 12. Power Supply Rejection vs. Frequency Figure 15. Output Swing and Error vs. Settling Time Figure 18. Slew Rate vs. Input Error Signal AD711 Figure 20. T.H.D. Test Circuit Figure 19. Slew Rate vs. Temperature Figure 21. Offset Null Configurations Figure 22a. Unity Gain Follower Figure 22b. Unity Gain Follower Pulse Response (Large Signal) Figure 22c. Unity Gain Follower Pulse Response (Small Signal) Figure 23a. Unity Gain Inverter Figure 23b. Unity Gain Inverter Pulse Response (Large Signal) Figure 23c. Unity Gain Inverter Pulse Response (Small Signal) –6– REV. A AD711 OPTIMIZING SETTLING TIME In addition to a significant improvement in settling time, the low offset voltage, low offset voltage drift, and high open-loop gain of the AD711 family assures 12-bit accuracy over the full operating temperature range. Most bipolar high-speed D/A converters have current outputs; therefore, for most applications, an external op amp is required for current-to-voltage conversion. The settling time of the converter/op amp combination depends on the settling time of the DAC and output amplifier. A good approximation is: The excellent high-speed performance of the AD711 is shown in the oscilloscope photos of Figure 25. Measurements were taken using a low input capacitance amplifier connected directly to the summing junction of the AD711 – both photos show the worst case situation: a full-scale input transition. The DAC’s 4 kΩ [10 kΩi8 kΩ = 4.4 kΩ] output impedance together with a 10 kΩ feedback resistor produce an op amp noise gain of 3.25. The current output from the DAC produces a 10 V step at the op amp output (0 to –10 V Figure 25a, –10 V to 0 V Figure 25b.) t S Total = (t S DAC )2 + (t S AMP )2 The settling time of an op amp DAC buffer will vary with the noise gain of the circuit, the DAC output capacitance, and with the amount of external compensation capacitance across the DAC output scaling resistor. Therefore, with an ideal op amp, settling to ± 1/2 LSB (± 0.01%) requires that 375 µV or less appears at the summing junction. This means that the error between the input and output (that voltage which appears at the AD711 summing junction) must be less than 375 µV. As shown in Figure 25, the total settling time for the AD711/AD565 combination is 1.2 microseconds. Settling time for a bipolar DAC is typically 100 to 500 ns. Previously, conventional op amps have required much longer settling times than have typical state-of-the-art DACs; therefore, the amplifier settling time has been the major limitation to a high-speed voltage-output D-to-A function. The introduction of the AD711/712 family of op amps with their 1 µs (to ± 0.01% of final value) settling time now permits the full high-speed capabilities of most modern DACs to be realized. Figure 24. ± 10 V Voltage Output Bipolar DAC b. (Full-Scale Positive Transition) a. (Full-Scale Negative Transition) Figure 25. Settling Characteristics for AD711 with AD565A REV. A –7– AD711 OP AMP SETTLING TIME— A MATHEMATICAL MODEL The design of the AD711 gives careful attention to optimizing individual circuit components; in addition, a careful tradeoff was made: the gain bandwidth product (4 MHz) and slew rate (20 V/µs) were chosen to be high enough to provide very fast settling time but not too high to cause a significant reduction in phase margin (and therefore stability). Thus designed, the AD711 settles to ± 0.01%, with a 10 V output step, in under 1 µs, while retaining the ability to drive a 100 pF load capacitance when operating as a unity gain follower. When RO and IO are replaced with their Thevenin VIN and RIN equivalents, the general purpose inverting amplifier of Figure 26b is created. Note that when using this general model, capacitance CX is EITHER the input capacitance of the op amp if a simple inverting op amp is being simulated OR it is the combined capacitance of the DAC output and the op amp input if the DAC buffer is being modeled. If an op amp is modeled as an ideal integrator with a unity gain crossover frequency of ωο/2π, Equation 1 will accurately describe the small signal behavior of the circuit of Figure 26a, consisting of an op amp connected as an I-to-V converter at the output of a bipolar or CMOS DAC. This equation would completely describe the output of the system if not for the op amp’s finite slew rate and other nonlinear effects. Equation 1. Figure 26b. Simplified Model of the AD711 Used as an Inverter VO –R = I IN R(C f = CX ) 2 GN s + + RC f s + 1 ωο ωο ωο where 2 =op amp’s unity gain frequency π R GN = “noise” gain of circuit 1 + R O In either case, the capacitance CX causes the system to go from a one-pole to a two-pole response; this additional pole increases settling time by introducing peaking or ringing in the op amp output. Since the value of CX can be estimated with reasonable accuracy, Equation 2 can be used to choose a small capacitor, CF, to cancel the input pole and optimize amplifier response. Figure 27 is a graphical solution of Equation 2 for the AD711 with R = 4 kΩ. This equation may then be solved for Cf: Equation 2. Cf = 2 − GN 2 RC X ω ο + (1 − GN ) + Rω ο Rω ο In these equations, capacitor CX is the total capacitor appearing the inverting terminal of the op amp. When modeling a DAC buffer application, the Norton equivalent circuit of Figure 26a can be used directly; capacitance CX is the total capacitance of the output of the DAC plus the input capacitance of the op amp (since the two are in parallel). Figure 27. Value of Capacitor CF vs. Value of CX The photos of Figures 28a and 28b show the dynamic response of the AD711 in the settling test circuit of Figure 29. Figure 26a. Simplified Model of the AD711 Used as a Current-Out DAC Buffer The input of the settling time fixture is driven by a flat-top pulse generator. The error signal output from the false summing node of A1 is clamped, amplified by A2 and then clamped again. The error signal is thus clamped twice: once to prevent overloading amplifier A2 and then a second time to avoid overloading the oscilloscope preamp. The Tektronix oscilloscope preamp type 7A26 was carefully chosen because it does not overload with these input levels. Amplifier A2 needs to be a very high speed FET-input op amp; it provides a gain of 10, amplifying the error signal output of A1. –8– REV. A AD711 Figure 28b. Settling Characteristics 0 to –10 V Step Upper Trace: Output of AD711 Under Test (5 V/Div) Lower Trace: Amplified Error Voltage (0.01%/Div) Figure 28a. Settling Characteristics 0 to +10 V Step Upper Trace: Output of AD711 Under Test (5 V/Div) Lower Trace: Amplified Error Voltage (0.01%/Div) Figure 29. Settling Time Test Circuit GUARDING D/A CONVERTER APPLICATIONS The low input bias current (15 pA) and low noise characteristics of the AD711 BiFET op amp make it suitable for electrometer applications such as photo diode preamplifiers and picoampere current-to-voltage converters. The use of a guarding technique such as that shown in Figure 30, in printed circuit board layout and construction is critical to minimize leakage currents. The guard ring is connected to a low impedance potential at the same level as the inputs. High impedance signal lines should not be extended for any unnecessary length on the printed circuit board. The AD711 is an excellent output amplifier for CMOS DACs. It can be used to perform both 2 quadrant and 4 quadrant operation. The output impedance of a DAC using an inverted R-2R ladder approaches R for codes containing many 1s, 3R for codes containing a single 1, and for codes containing all zero, the output impedance is infinite. For example, the output resistance of the AD7545 will modulate between 11 kΩ and 33 kΩ. Therefore, with the DAC’s internal feedback resistance of 11 kΩ, the noise gain will vary from 2 to 4/3. This changing noise gain modulates the effect of the input offset voltage of the amplifier, resulting in nonlinear DAC amplifier performance. The AD711K with guaranteed 500 µV offset voltage minimizes this effect to achieve 12-bit performance. Figures 31 and 32 show the AD711 and AD7545 (12-bit CMOS DAC) configured for unipolar binary (2-quadrant multiplication) or bipolar (4-quadrant multiplication) operation. Capacitor C1 provides phase compensation to reduce overshoot and ringing. Figure 30. Board Layout for Guarding Inputs REV. A –9– AD711 NOISE CHARACTERISTICS The random nature of noise, particularly in the 1/f region, makes it difficult to specify in practical terms. At the same time, designers of precision instrumentation require certain guaranteed maximum noise levels to realize the full accuracy of their equipment. The AD711C grade is specified at a maximum level of 4.0 µV p-p, in a 0.1 to 10 Hz bandwidth. Each AD711C receives a 100% noise test for two 10-second intervals; devices with any excursion in excess of 4.0 µV are rejected. The screened lot is then submitted to Quality Control for verification on an AQL basis. All other grades of the AD711 are sample-tested on an AQL basis to a limit of 6 µV p-p, 0.1 to 10 Hz. DRIVING THE ANALOG INPUT OF AN A/D CONVERTER Figure 31. Unipolar Binary Operation An op amp driving the analog input of an A/D converter, such as that shown in Figure 34, must be capable of maintaining a constant output voltage under dynamically changing load conditions. In successive-approximation converters, the input current is compared to a series of switched trial currents. The comparison point is diode clamped but may deviate several hundred millivolts resulting in high frequency modulation of A/D input current. The output impedance of a feedback amplifier is made artificially low by the loop gain. At high frequencies, where the loop gain is low, the amplifier output impedance can approach its open loop value. Most IC amplifiers exhibit a minimum open loop output impedance of 25 Ω due to current limiting resistors. A few hundred microamps reflected from the change in converter Figure 32. Bipolar Operation R1 and R2 calibrate the zero offset and gain error of the DAC. Specific values for these resistors depend upon the grade of AD7545 and are shown below. Table I. Recommended Trim Resistor Values vs. Grades of the AD7545 for VDD = +5 V TRIM RESISTOR JN/AQ/SD KN/BQ/TD LN/CQ/UD GLN/GCQ/GUD R1 R2 500 Ω 150 Ω 200 Ω 68 Ω 100 Ω 33 Ω 20 Ω 6.8 Ω Figures 33a and 33b show the settling time characteristics of the AD711 when used as a DAC output buffer for the AD7545. a. Full-Scale Positive Transition a. Full-Scale Positive Transition Figure 34. AD711 as ADC Unity Gain Buffer b. Full-Scale Negative Transition a. Source Current = 2 mA b. Full-Scale Negative Transition b. Sink Current = 1 mA Figure 35. ADC Input Unity Gain Buffer Recovery Times Figure 33. Settling Characteristics for AD711 with AD7545 –10– REV. A AD711 loading can introduce errors in instantaneous input voltage. If the A/D conversion speed is not excessive and the bandwidth of the amplifier is sufficient, the amplifier’s output will return to the nominal value before the converter makes its comparison. However, many amplifiers have relatively narrow bandwidth yielding slow recovery from output transients. The AD711 is ideally suited to drive high speed A/D converters since it offers both wide bandwidth and high open-loop gain. SECOND ORDER LOW PASS FILTER Figure 38 depicts the AD711 configured as a second order Butterworth low pass filter. With the values as shown, the corner frequency will be 20 kHz; however, the wide bandwidth of the AD711 permits a corner frequency as high as several hundred kilohertz. Equations for component selection are shown below. R1 = R2 = user selected (typical values: 10 kΩ – 100 kΩ) DRIVING A LARGE CAPACITIVE LOAD The circuit in Figure 36 employs a 100 Ω isolation resistor which enables the amplifier to drive capacitive loads exceeding 1500 pF; the resistor effectively isolates the high frequency feedback from the load and stabilizes the circuit. Low frequency feedback is returned to the amplifier summing junction via the low pass filter formed by the 100 Ω series resistor and the load capacitance, CL. Figure 37 shows a typical transient response for this connection. C1= 1.414 0.707 , C2 = (2 π)( f cutoff )(R1) (2 π)( f cutoff )(R1) Where C1 and C2 are in farads. Figure 38. Second Order Low Pass Filter An important property of filters is their out-of-band rejection. The simple 20 kHz low pass filter shown in Figure 38, might be used to condition a signal contaminated with clock pulses or sampling glitches which have considerable energy content at high frequencies. Figure 36. Circuit for Driving a Large Capacitive Load The low output impedance and high bandwidth of the AD711 minimize high frequency feedthrough as shown in Figure 39. The upper trace is that of another low-cost BiFET op amp showing 17 dB more feedthrough at 5 MHz. Figure 37. Transient Response RL = 2 kΩ, CL = 500 pF ACTIVE FILTER APPLICATIONS In active filter applications using op amps, the dc accuracy of the amplifier is critical to optimal filter performance. The amplifier’s offset voltage and bias current contribute to output error. Offset voltage will be passed by the filter and may be amplified to produce excessive output offset. For low frequency applications requiring large value input resistors, bias currents flowing through these resistors will also generate an offset voltage. Figure 39. 9-POLE CHEBYCHEV FILTER Figure 40 shows the AD711 and its dual counterpart, the AD712, as a 9-pole Chebychev filter using active frequency dependent negative resistors (FDNR). With a cutoff frequency of 50 kHz and better than 90 dB rejection, it may be used as an anti-aliasing filter for a 12-bit Data Acquisition System with 100 kHz throughput. In addition, at higher frequencies, an op amp’s dynamics must be carefully considered. Here, slew rate, bandwidth, and open-loop gain play a major role in op amp selection. The slew rate must be fast as well as symmetrical to minimize distortion. The amplifier’s bandwidth in conjunction with the filter’s gain will dictate the frequency response of the filter. As shown in Figure 40, the filter is comprised of four FDNRs The use of a high performance amplifier such as the AD711 will minimize both dc and ac errors in all active filter applications. REV. A (A, B, C, D) having values of 4.9395 3 10–15 and 5.9276 3 10–15 farad-seconds. Each FDNR active network provides a two-pole response; for a total of 8 poles. The 9th pole consists of a 0.001 µF capacitor and a 124 kΩ resistor at Pin 3 of amplifier A2. Figure 41 depicts the circuits for each FDNR with the –11– AD711 C1018b-20-3/88 proper selection of R. To achieve optimal performance, the 0.001 µF capacitors must be selected for 1% or better matching and all resistors should have 1% or better tolerance. Figure 40. 9-Pole Chebychev Filter Figure 41. FDNR for 9-Pole Chebychev Filter Figure 42. High Frequency Response for 9-Pole Chebychev Filter OUTLINE DIMENSIONS Mini-DIP (N) Package Cerdip (Q) Package TO-99 (H) Package Small Outline (R) Package –12– PRINTED IN U.S.A. Dimensions shown in inches and (mm). REV. A