a FEATURES Dual Supply ⴞ5 V High-Speed Fully Buffered Inputs and Outputs 600 MHz Bandwidth (–3 dB) 200 mV p-p 500 MHz Bandwidth (–3 dB) 2 V p-p 1600 V/s Slew Rate, G = +1 1350 V/s Slew Rate, G = +2 Fast Settling Time: 4 ns Low Supply Current: <30 mA Excellent Video Specifications (RL = 150 ⍀): Gain Flatness of 0.1 dB to 50 MHz 0.01% Differential Gain Error 0.01ⴗ Differential Phase Error “All Hostile“ Crosstalk –80 dB @ 10 MHz –50 dB @ 100 MHz High “OFF” Isolation of 90 dB @ 10 MHz Low Cost Fast Output Disable Feature 500 MHz, G = +1 and +2 Triple Video Buffers with Disable AD8074/AD8075 FUNCTIONAL BLOCK DIAGRAM AD8074 /AD8075 OE 1 16 VCC 15 VCC DGND 2 IN2 3 G= +1/+2 AGND 4 IN1 5 13 VEE G= +1/+2 VEE 8 12 OUT1 11 VCC AGND 6 IN0 7 14 OUT2 G= +1/+2 10 OUT0 9 VEE APPLICATIONS RGB Buffer in LCD and Plasma Displays RGB Driver Video Routers Table I. Truth Table PRODUCT DESCRIPTION The AD8074/AD8075 are high-speed triple video buffers with G = +1 and +2 respectively. They have a –3 dB full signal bandwidth in excess of 450 MHz, along with slew rates in excess of 1400 V/µs. With better than –80 dB of all hostile crosstalk and 90 dB isolation, they are useful in many high-speed applications. The differential gain and differential phase error are 0.01% and 0.01°. Gain flatness of 0.1 dB up to 50 MHz makes the AD8074/AD8075 ideal for RGB buffering or driving. They consume less than 30 mA on a ± 5 V supply. OE OUT0, 1, 2 0 1 IN0, IN1, IN2 High Z Both devices offer a high-speed disable feature that allows the outputs to be put into a high impedance state. This allows the building of larger input arrays while minimizing “OFF” channel output loading. The AD8074/AD8075 are offered in a 16-lead TSSOP package. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 AD8074/AD8075–SPECIFICATIONS (T = 25ⴗC, V = ⴞ5 V, unless otherwise noted.) A Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth (Small Signal) –3 dB Bandwidth (Large Signal) 0.1 dB Bandwidth Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Differential Gain Differential Phase All Hostile Crosstalk OFF Isolation Voltage Noise DC PERFORMANCE Voltage Gain Error Input Offset Voltage S Conditions Min Typ VIN = 200 mV p-p, CL = 5 pF VIN = 200 mV p-p, RL = 150 Ω VIN = 2 V p-p, CL = 5 pF VIN = 2 V p-p, RL = 150 Ω VIN = 200 mV p-p, CL = 5 pF VIN = 200 mV p-p, RL = 150 Ω 2 V Step, RL = 1 kΩ/150 Ω 2 V Step, RL = 1 kΩ/150 Ω 330/310 250/230 330/300 250/230 600/550 400/400 500/500 350/350 70/65 70/65 1600/1350 4/7.5 MHz MHz MHz MHz MHz MHz V/µs ns V = 3.58 MHz, 150 Ω V = 3.58 MHz, 150 Ω V = 10 MHz, RL = 1 kΩ V = 100 MHz, RL = 1 kΩ V = 10 MHz, RL = 150 Ω V = 10 kHz to 100 MHz 0.01 0.01 –80/–74 –50/–44 90 19.5/22 % Degrees dB dB dB nV/√Hz No Load ± 0.1/± 0.2 2.5 3 10 5 TMIN to TMAX Input Offset Drift Input Bias Current INPUT CHARACTERISTICS Input Resistance Input Capacitance Channel Enabled Channel Disabled Input Voltage Range OUTPUT CHARACTERISTICS Output Voltage Swing RL = 1 kΩ +VS – 1.95 –VS + 2.1 +VS – 2.35 –VS + 2.30 RL = 150 Ω Short Circuit Current (Protected) Output Resistance Output Capacitance POWER SUPPLY Operating Range Power Supply Rejection Ratio Quiescent Current Enabled Disabled Disabled 3.5 +PSRR: +VS = +4.5 V to +5.5 V, –VS = –5 V –PSRR: –VS = –4.5 V to –5.5 V, +VS = +5 V All Channels “ON” All Channels “OFF” TMIN to TMAX ± 4.5 60 56 DIGITAL INPUT Logic “1” Voltage Logic “0” Voltage Logic “1” Input Current Logic “0” Input Current OE Input OE Input OE = 4 V OE = 0.4 V 2.0 OPERATING TEMPERATURE RANGE Temperature Range θJA θJC Operating (Still Air) Operating (Still Air) Operating –40 Max ± 0.15/± 0.65 27/40 9.5/10 Unit % mV mV µV/°C µA 10 1.5 1.5 ± 2.8/± 1.4 MΩ pF pF V +VS – 1.8 –VS + 1.8 +VS – 2.2 –VS + 2.2 70 0.5 7.5 2.2 V V V V mA Ω MΩ pF ± 5.5 74 64 21.5/24 3/4 23/26 30 5.5 0.8 100 1 +85 150.4 27.6 V dB dB mA mA mA V V nA µA °C °C/W °C/W Specifications subject to change without notice. –2– REV. A AD8074/AD8075 ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.0 V Internal Power Dissipation 2, 3 AD8074/AD8075 16-Lead TSSOP (RU) . . . . . . . . . . . . . 1 W Input Voltage IN0, IN1, IN2 . . . . . . . . . . . . . . . . . . . . . . . . . VEE ≤ VIN ≤ VCC OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND ≤ VIN ≤ VCC Output Short Circuit Duration . . . . . . . . . . . . . . . . . . Indefinite3 Storage Temperature Range . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . . 300°C ORDERING GUIDE Model AD8074ARU AD8075ARU AD8074-EVAL AD8075-EVAL Temperature Range Package Description Package Option –40°C to +85°C –40°C to +85°C 16-Lead Plastic TSSOP 16-Lead Plastic TSSOP Evaluation Board Evaluation Board RU-16 RU-16 PIN CONFIGURATION NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air (T A = 25°C). 3 16-lead plastic TSSOP; θJA = 150.4°C/W. Maximum internal power dissipation (P D) should be derated for ambient temperature (T A ) such that PD < (150°C – T A)/θJA. AD8074 /AD8075 OE 1 16 VCC 15 VCC DGND 2 IN2 3 G= +1/+2 14 OUT2 AGND 4 IN1 5 13 VEE G= +1/+2 12 OUT1 11 VCC AGND 6 IN0 7 G= +1/+2 10 OUT0 9 VEE VEE 8 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8074/AD8075 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. MAXIMUM POWER DISSIPATION WARNING! ESD SENSITIVE DEVICE 1.5 TJ = 150ⴗC MAXIMUM POWER DISSIPATION – Watts The maximum power that can be safely dissipated by the AD8074/ AD8075 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. While the AD8074/AD8075 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figure 1. 1.0 0.5 0 –50 –30 –10 0 10 30 50 70 90 AMBIENT TEMPERATURE – ⴗC Figure 1. Maximum Power Dissipation vs. Temperature REV. A –3– AD8074/AD8075–Typical Performance Characteristics 1 0.4 GAIN 0.3 0 –1 0.2 –1 –2 0.1 –4 –0.1 –5 –0.2 2V p-p 0.3 0.2 2V p-p –2 0.1 FLATNESS –3 200mV p-p 0 –4 –0.1 –5 –0.2 –6 –0.3 –7 –0.4 –7 –0.4 –8 –0.5 –8 –0.5 –9 0.1 1 10 FREQUENCY – MHz –6 100 –9 0.1 2 0.5 1 0.4 0 –1 0.3 –1 –2 0.2 2V p-p –3 FLATNESS 0.1 0 –0.1 –5 200mV p-p 2V p-p –0.2 200mV p-p –7 FLATNESS – dB GAIN NORMALIZED GAIN – dB 0.6 –6 10 100 –0.6 1000 TPC 4. AD8075 Frequency Response; RL = 150 Ω 1 –4 1 FREQUENCY – MHz 2 0 –0.3 2V p-p –0.6 1000 TPC 1. AD8074 Frequency Response; RL = 150 Ω GAIN – dB GAIN –0.3 0.6 0.5 GAIN 0.4 0.3 2V p-p –2 2V p-p –4 0.2 0.1 –3 FLATNESS 0 –0.1 –5 –0.2 –6 –7 200mV p-p –0.3 –8 –0.4 –8 –0.4 –9 –0.5 –9 –0.5 –10 0.1 1 10 FREQUENCY – MHz 100 –0.6 1000 –10 0.1 TPC 2. AD8074 Frequency Response; RL = 1 kΩ, CL = 5 pF 1 GAIN – dB NORMALIZED GAIN – dB 0 –1 CL = 0pF –2 CL = 5pF –3 –4 VIN VOUT CL 75⍀ 1k⍀ –7 0 –1 CL = 0pF –2 CL = 5pF –3 –4 –5 –6 VIN VOUT CL 75⍀ 150k⍀ –7 –8 –10 0.1 CL = 10pF 2 1 –9 –0.6 1000 3 CL = 10pF 2 –6 10 100 FREQUENCY – MHz TPC 5. AD8075 Frequency Response; RL = 1 kΩ, CL = 5 pF 3 –5 1 NORMALIZED FLATNESS – dB GAIN – dB 0 FLATNESS – dB 200mV p-p FLATNESS –3 NORMALIZED GAIN – dB 0 NORMALIZED FLATNESS – dB 0.4 1 –8 VOUT = 2V p-p 1 –9 10 FREQUENCY – MHz 100 –10 0.1 1000 TPC 3. AD8074 Frequency Response vs. Capacitive Load VOUT = 2V p-p 1 10 FREQUENCY – MHz 100 1000 TPC 6. AD8075 Frequency Response vs. Capacitive Load –4– REV. A AD8074/AD8075 0 0 VOUT = 2V p-p (ACTIVE CHANNEL(s)) RL = 1k⍀ RT = 37.5⍀ –10 –20 –20 –30 CROSSTALK – dB –30 CROSSTALK – dB VOUT = 2V p-p (ACTIVE CHANNEL(s)) RL = 150⍀ RT = 37.5⍀ –10 –40 –50 –60 ALL-HOSTILE –70 –40 –50 ALL-HOSTILE –60 –70 –80 –80 ADJACENT ADJACENT –90 –90 –100 –100 –110 –110 0.1 1 10 0.1 1000 100 1 TPC 7. AD8074 Crosstalk vs. Frequency (All Hostile and Adjacent RL = 1 kΩ) 1000 0 VOUT = 2V p-p RL = 150⍀ RT = 37.5⍀ –10 –20 –20 DISTORTION – dBc –40 –50 SECOND HARMONIC –60 VOUT = 2V p-p RL = 150⍀ RT = 37.5⍀ –10 –30 DISTORTION – dBc 100 TPC 9. AD8075 Crosstalk vs. Frequency (All Hostile and Adjacent RL = 150 Ω) 0 –70 –80 –30 –40 SECOND HARMONIC –50 –60 –70 THIRD HARMONIC –80 THIRD HARMONIC –90 –90 –100 –100 1 10 100 1 1000 10 100 1000 FUNDAMENTAL FREQUENCY – MHz FUNDAMENTAL FREQUENCY – MHz TPC 8. AD8074 Distortion vs. Frequency REV. A 10 FREQUENCY – MHz FREQUENCY – MHz TPC 10. AD8075 Distortion vs. Frequency –5– –20 –20 –30 –30 –40 –40 OFF ISOLATION – dB OFF ISOLATION – dB AD8074/AD8075 –50 –60 –70 RL = 1k⍀ –80 –90 –50 –60 RL = 1k⍀ –70 –80 RL = 150⍀ –90 RL = 150⍀ –100 –100 –110 –110 0.1 1 10 100 1000 0.1 1 1000 TPC 14. AD8075 Off Isolation vs. Frequency 10 20 0 10 0 –PSRR –10 PSRR – dB –20 PSRR – dB 100 TPC 11. AD8074 Off Isolation vs. Frequency –10 –30 +PSRR –40 +PSRR –20 –PSRR –30 –50 –40 –60 –50 –70 –60 –80 –70 1 0.1 10 100 1000 1 0.1 FREQUENCY – MHz 100 1000 TPC 15. AD8075 PSRR vs. Frequency 400 300 350 VOLTAGE NOISE – nV/ Hz 350 250 200 150 100 50 0 10 FREQUENCY – MHz TPC 12. AD8074 PSRR vs. Frequency VOLTAGE NOISE – nV/ Hz 10 FREQUENCY – MHz FREQUENCY – MHz 300 250 200 150 100 50 10 100 1k 10k FREQUENCY – Hz 100k 0 10 1M 100 1k 10k FREQUENCY – Hz 100k 1M TPC 16. AD8075 Voltage Noise vs. Frequency TPC 13. AD8074 Voltage Noise vs. Frequency –6– REV. A AD8074/AD8075 1000 1000 INPUT IMPEDANCE – k⍀ 10000 INPUT IMPEDANCE – k⍀ 10000 100 10 1 100 10 1 0.1 0.1 0.01 0.01 0.1 1 10 100 1000 0.1 1 FREQUENCY – MHz 100 100 OUTPUT IMPEDANCE – ⍀ 1000 OUTPUT IMPEDANCE – ⍀ 1000 10 1 1000 10 1 0.1 0.1 0.1 1 10 100 0.1 1000 1 10 100 1000 FREQUENCY – MHz FREQUENCY – MHz TPC 21. AD8075 Output Impedance vs. Frequency; Enabled TPC 18. AD8074 Output Impedance vs. Frequency; Enabled 1000 1000 100 100 OUTPUT IMPEDANCE – k⍀ OUTPUT IMPEDANCE – k⍀ 100 TPC 20. AD8075 Input Impedance vs. Frequency TPC 17. AD8074 Input Impedance vs. Frequency 10 1 0.1 10 1 0.1 0.01 0.01 0.001 0.001 0.1 1 10 100 0.1 1000 1 10 100 1000 FREQUENCY – MHz FREQUENCY – MHz TPC 22. AD8075 Output Impedance vs. Frequency; Disabled TPC 19. AD8074 Output Impedance vs. Frequency; Disabled REV. A 10 FREQUENCY – MHz –7– AD8074/AD8075 0.15 0.15 VO = 200mV STEP VO = 200mV STEP 0.10 0.10 0.05 0.05 0 0 –0.05 –0.05 –0.10 –0.10 2ns 2ns –0.15 –0.15 TPC 23. AD8074 Small Signal Pulse Response (RL = 1 kΩ, CL = 5 pF) TPC 26. AD8075 Small Signal Pulse Response (RL = 150 kΩ) 0.8 0.8 0.7 0.7 VO = 700mV STEP 0.6 VO = 700mV STEP 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 2ns –0.1 0 –0.2 –0.1 2ns TPC 24. AD8074 Video Amplitude Pulse Response (RL = 1 kΩ, CL = 5 pF) TPC 27. AD8075 Video Amplitude Pulse Response (RL = 150 Ω) 1.5 1.5 VO = 2V STEP VO = 2V STEP 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 2ns 2ns –1.5 –1.5 TPC 28. AD8075 Large Signal Pulse Response (RL = 150 Ω) TPC 25. AD8074 Large Signal Pulse Response (RL = 1 kΩ, CL = 5 pF) –8– REV. A AD8074/AD8075 THEORY OF OPERATION The AD8074 (G = +1) and AD8075 (G = +2) are triple-channel, high-speed buffers with TTL-compatible output enable control. Optimized for buffering RGB (red, green, blue) video sources, the devices have high peak slew rates, maintaining their bandwidth for large signals. Additionally, the buffers are compensated for high phase margin, minimizing overshoot for good pixel resolution. The buffers also have video specifications that are suitable for buffering NTSC or PAL composite signals. The buffers are organized as three independent channels, each with an input transconductance stage and an output transimpedance stage. Each channel is characterized by low input capacitance and high input impedance. The transconductance stages, NPN differential pairs, source signal current into the folded cascode output stages. Each output stage contains a compensating network and emitter follower output buffer. Internal voltage feedback sets the gain, the AD8074 being configured as a unity gain follower, and the AD8075 as a gain-of-two amplifier with a feedback network. The architecture provides drive for a reverseterminated video load (150 Ω) with low differential gain and phase error for relatively low power consumption. Careful chip design and layout allow excellent crosstalk isolation between channels. One logic pin, OE, controls whether the three outputs are enabled, or disabled to a high-impedance state. The high impedance disable allows larger matrices to be built when busing the outputs together. When disabled, the AD8074 and AD8075 consume a fifth the power as when enabled. In the case of the AD8075 (G = +2), a feedback isolation scheme is used so that the impedance of the gain-of-two feedback network does not load the output. Full power bandwidth for an undistorted sinusoid is often calculated using peak slew rate from the equation: Full Power Bandwidth = Peak Slew Rate 2 × π × Sinusoidal Amplitude Peak slew rate is not the same as average slew rate (25% to 75%) which is typically specified. For a natural response, peak slew rate may be 2.7 times larger than average slew rate. Therefore, calculating a full power bandwidth with a specified average slew rate will give a pessimistic result. The primary cause of overshoot in these amplifiers is the presence of large reactive loads at the output and insufficient series isolation of the load. However, it is possible to overdrive these amplifiers with 1 V, subnanosecond input-pulse edges. The ensuing dynamics may give rise to subnanosecond overshoot. To reduce these effects, an edge-rate limiting network at the input should be considered for input transition times less than 0.5 ns. REV. A APPLICATIONS Response Tuning It has been mentioned in passing that the primary cause of overshoot for the AD8074 and AD8075 is the presence of large reactive loads at the output. If the system exhibits excessive ringing while settling, a 10 Ω–50 Ω series resistor may be used at the output to isolate the emitter-follower output buffer from the reactive load. If the output exhibits an overdamped response, the system designer may add a few pF shunt capacitance at the output to tune for a faster edge transition. A system with a small degree of overshoot will settle faster than an overdamped system. 2.0 RS = 10⍀ CL = 10pF 1.5 1.0 RS = 0⍀ CL = 5pF 0.5 RS = 20⍀ CL = 15pF 0 –0.5 –1.0 RS VIN –1.5 75⍀ CL VOUT 1k⍀ 2ns –2.0 Figure 2. Driving Capacitive Loads Single Supply Operation The AD8074 and AD8075 may be operated from a single 10 V supply. In this configuration, the AD8075’s AGND pins must be tied near midsupply, as AGND provides the reference for the ground buffer, to which the internal gain network is terminated. Logic is referenced to DGND. The buffers are disabled in single supply operation for VOE > V DGND + ~2.0 V and enabled for VOE < VDGND + 0.8 V. TTL logic levels are expected. The following restrictions are placed upon the digital ground potential: 3.5 V ≤ VAVCC – VDGND ≤ 12 V VDGND ≥ VAVEE The architecture of the output buffer is such that the output voltage can swing to within ~2.3 V of either rail. For example, if the output need swing only 2 V, then the buffers could be operated on dual 3.5 V or single 7 V supplies. It is cautioned that saturation effects may become noticeable when the output swings within 2.6 V of either rail. The system designer may opt to use this characteristic to his or her advantage by using the soft-saturation regime, (2.2 V–2.6 V from the supply rails), to tame excessive overshoot. The designer is cautioned that a charge storage associated time delay of several nanoseconds is incurred when recovering from soft-saturation. This effect results in longer settling tails. –9– AD8074/AD8075 can be connected to the same signal, as is done in some studiotype TV monitors. RGB Buffer for Second Monitor The RGB signals for PC monitors are driven through coax cables whose characteristic impedance is 75 Ω. The graphics chip will generally have current-source output drivers that should be double terminated with a 75 Ω shunt termination at each end. On the transmit end, the shunt terminations are provided to ground close to the graphics IC, while the monitor terminates its end via internal termination resistors. While this scheme works well and is virtually foolproof for a single monitor, it leaves no means for passively connecting a second monitor to the same source. A way around this problem is to connect the first monitor to the RGB channels in the standard fashion, and then to provide a triple gain-of-two buffer to drive the second monitor. The AD8075 is designed to provide this function and also provide excellent high-frequency performance for high-resolution graphics signals. Figure 3 shows a schematic of this circuit. The outputs of the AD8075 are low impedance voltage sources and are therefore series-terminated with 75 Ω resistors. The internal resistors in Monitor #2 provide the terminations at its end. The overall effect of this type of termination scheme is to divide the signal amplitude by two. This is compensated by the gain of two provided by the AD8075. A second monitor that is connected simply in parallel will provide an extra set of terminations that will upset the signal levels. To keep costs low, most computer monitors do not have the ability to open-circuit the terminations in order that an additional monitor MONITOR #1 PC GRAPHICS IC R CURRENT SOURCE OUTPUT DRIVERS 75⍀ 75⍀ 75⍀ 75⍀ 75⍀ 75⍀ G INTERNAL TERMINATIONS B +5V 25F + +5V 0.1F +5V 0.1F 0.1F MONITOR #2 75⍀ 75⍀ AD8075 75⍀ 75⍀ INTERNAL TERMINATIONS 75⍀ 75⍀ 25F 0.1F + –5V 0.1F –5V 0.1F –5V Figure 3. Buffer –10– REV. A AD8074/AD8075 Triple Video Multiplexer and the amplifier output are disabled to a high impedance to provide a high-impedance disabled state. The AD8074 and AD8075 each have an output-enable function that can be used to disable the outputs and put them in a highimpedance state. Usually, for a unity-gain device, it is relatively easy to provide high disabled impedance, because the feedback path is from the output to a high-impedance input. However, for a non-unity-gain part, the feedback provides a resistive path to ground. This will usually dominate the disabled output impedance, and make it a much lower value than the unity-gain device. To construct a multiplexer, the outputs from one or more devices are connected in parallel and only one device is enabled at a time while all of the others are disabled. The two sets of inputs are applied individually to each of the separate device inputs. Figure 4 shows the circuit details for this function. The first RGB Source 1 is input to the first AD8075. Each of the individual signals is terminated to ground with 75 Ω to provide proper termination for the input cables. In a similar fashion, the Source 2 signals are input to the second AD8075. The AD8075 has an internal buffer that provides a low-impedance, ground level output that terminates the feedback path during enabled operation. In the disabled state, both this buffer output +5V 25F + +5V 0.1F +5V 0.1F 0.1F 75⍀ R R 75⍀ AD8075 75⍀ SOURCE 1 G G 75⍀ 75⍀ B B 75⍀ OE 25F 0.1F + –5V 0.1F –5V 0.1F –5V SEL1/SEL2 +5V 25F + +5V 0.1F +5V 0.1F 0.1F OE 75⍀ R 75⍀ AD8075 75⍀ SOURCE 2 G 75⍀ 75⍀ B 75⍀ 25F 0.1F + –5V 0.1F –5V Figure 4. Mux REV. A –11– 0.1F –5V OUTPUT AD8074/AD8075 Each of the six outputs has a 75 Ω series resistor that is used to reverse-terminate the output transmission line. The corresponding outputs are then wired in parallel and delivered to the output cable. The termination resistors in this position help to isolate the off capacitance of the disabled device’s outputs from loading the enabled device’s outputs. The gain-of-two of the AD8075 compensates for the signal halving that occurs as a result of the output terminations. A select signal is provided directly to the OE of the second AD8075 and an inverted version is used to drive the other device’s OE. This will ensure that only one device is active at a time. Since there is a total of 150 Ω in series between any two outputs, it is not essential to be overly concerned about the exact timing of the making and breaking of the enable signals. A major area of focus should be the power distribution system. There should be a full ground plane that provides the reference and return paths for both the inputs and outputs. The ground also provides isolation between the input signals to minimize the crosstalk. This ground plane should cover as wide an area as possible and be minimally interrupted in order to keep its impedance to a minimum. The power planes should also be as broad as possible to provide minimal inductance, which is required for high-slew-rate signals. These power planes layers should be spaced closely to the ground plane to increase the interplane capacitance between the supplies and ground. Each supply pin should be bypassed with a low inductance 0.1 µF ceramic capacitance with minimal excess circuit length to minimize the series impedance. A 25 µF tantalum electrolytic capacitor will supply a charge reservoir for lower frequency, high-amplitude transitions. Additional inputs can easily be added to the circuit shown to make wider multiplexers. The outputs of all of the devices will be wired in parallel, and the logic must allow that only one output be enabled at a time. If it is desired to make a triple 3:1 multiplexer, a triple 2:1 multiplexer, like the AD8185 can be used along with the AD8075. The same general guidelines for input and output treatment should be followed and the logic must perform the proper function. If it is desired to design such a multiplexer at unity gain, the AD8074 should be used. For a triple 3:1 multiplexer, an AD8183 (triple 2:1 mux) can be combined with an AD8074 to provide this function. Layout and Grounding The AD8074 and AD8075 are extreme bandwidth, high-slew-rate devices that are designed to drive up to the highest resolution monitors and provide excellent resolution. To realize their full performance potential, it is essential to adhere to the best practices of high-speed PCB layout. The input and output signals should be run as directly as possible in order to minimize the effects of parasitics. If they must run over a longer distance of more than a few centimeters, controlled impedance PCB traces should be used to minimize the effect of reflections due to mismatches in impedance and the proper termination should be provided. To avoid excess crosstalk, the above recommendations should be followed carefully. The power system and signal routing are the most important aspects of preventing excess crosstalk. Beyond these techniques, shielding can be provided by ground traces between adjacent signals, especially those that travel parallel over long distances. –12– REV. A AD8074/AD8075 TP2 VEE P1 DO NOT INSTALL VEE VEE 50⍀ IMPEDANCE LINE 1 C2 10F + TP3 TP4 AGND AGND AGND VCC AGND AGND R16 20k⍀ P1 AGND 2 TP1 W2 VCC TP5 P1 3 DO NOT INSTALL VCC + C1 10F AGND VCC 50⍀ IMPEDANCE LINE 50⍀ IMPEDANCE LINE DISOUT AGND DISOUT R11 50⍀ DO NOT INSTALL AGND IN2 75⍀ IMPEDANCE LINE IN2 C3 0.1F DO NOT INSTALL R1 75⍀ AGND DUT AGND IN1 75⍀ IMPEDANCE LINE AGND AGND R2 75⍀ AGND AGND IN0 75⍀ IMPEDANCE LINE IN0 AGND 3 IN2 C13 0.01F C6 0.1F AGND C8 0.01F R6 150⍀ DO NOT INSTALL AGND R8 75⍀ VEE 13 OUT1 12 6 AGND VCC 11 AGND AGND VEE C11 0.01F AGND C12 0.01F 75⍀ IMPEDANCE LINE OUT1 DO NOT INSTALL AGND AGND R9 75⍀ 75⍀ IMPEDANCE LINE OUT0 DO NOT INSTALL AGND Figure 5. Evaluation Board Schematic –13– OUT1 AGND R12 150⍀ REV. A OUT2 R10 150⍀ VCC OUT0 10 VEE 9 AD8074 75⍀ IMPEDANCE LINE OUT2 AGND OUT2 14 5 IN1 R7 75⍀ VEE VCC 16 VCC 15 4 AGND 7 IN0 8 VEE VEE R3 75⍀ 1 OE 2 DGND AGND C7 0.1F AGND IN1 VCC C14 0.01F C15 0.01F AGND OUT0 AD8074/AD8075 Figure 6. Component Side Figure 8. Silkscreen Top Figure 7. Circuit Side Figure 9. Silkscreen Bottom Figure 10. Internal 2 –14– REV. A AD8074/AD8075 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Controlling Dimension: Metric, shown in parentheses. 16-Lead TSSOP (RU-16) 0.201 (5.10) 0.193 (4.90) 16 9 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 8 PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PLANE REV. A 0.0433 (1.10) MAX 0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) –15– 8ⴗ 0ⴗ 0.028 (0.70) 0.020 (0.50) AD8074/AD8075 Revision History Location Page Data Sheet changed from REV. 0 to REV. A. PRINTED IN U.S.A. C02391–0–10/01(A) Addition to equation in SINGLE SUPPLY OPERATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 –16– REV. A