G = 0.2, Level Translation, 16-Bit ADC Driver AD8275 PIN CONFIGURATION Translates ±10 V to +4 V Drives 16-bit SAR ADCs Small MSOP package Input overvoltage: +40 V to −35 V (VS = 5 V) Fast settling time: 450 ns to 0.001% Rail-to-rail output Wide supply operation: +3.3 V to +15 V High CMRR: 80 dB Low gain drift: 1 ppm/°C Low offset drift: 2.5 μV/°C REF1 1 –IN 2 +IN 3 TOP VIEW (Not to Scale) –VS 4 8 REF2 7 +VS 6 OUT 5 SENSE Figure 1. TYPICAL APPLICATION +5V 0.1µF 7 2 APPLICATIONS 50kΩ +2.048V 10kΩ –IN 5 3 50kΩ 20kΩ +IN 20kΩ REF2 REF1 33Ω 6 VDD IN+ AD7685 2.7nF IN– REF GND 8 1 VREF 4.096V 10µF –VS 4 07546-002 AD8275 +0.048V SENSE OUT –10V VIN 0.1µF +4.048V +VS +10V Level translator ADC driver Instrumentation amplifier building block Automated test equipment AD8275 07546-001 FEATURES Figure 2. Translating ±10 V to 4.096 V ADC Full Scale GENERAL DESCRIPTION The AD8275 is a G = 0.2 difference amplifier that can be used to translate ±10 V signals to a +4 V level. It solves the problem typically encountered in industrial and instrumentation applications where ±10 V signals must be interfaced to a single-supply 4 V or 5 V ADC. The AD8275 interfaces the two signal levels, simplifying design. The AD8275 has fast settling time of 450 ns and low distortion, making it suitable for driving medium speed successive approximation (SAR) ADCs. Its wide input voltage range and rail-torail outputs make it an easy to use building block. Single-supply operation reduces the power consumption of the amplifier and helps to protect the ADC from overdrive conditions. Internal, matched, precision laser-trimmed resistors ensure low gain error, low gain drift of 1 ppm/°C (maximum), and high common-mode rejection of 80 dB. Low offset and low offset drift, combined with its fast settling time, make the AD8275 suitable for a variety of data acquisition applications where accurate and quick capture is required. The AD8275 can be used as an analog front end, or it can follow buffers to level translate high voltages to a voltage range accepted by the ADC. In addition, the AD8275 can be configured for differential outputs if used with a differential ADC. The AD8275 is available in a space-saving, 8-lead MSOP and is specified for performance over the −40°C to +85°C temperature range. Table 1. Difference Amplifiers by Category Low Distortion AD8270 AD8273 AD8274 AD8275 AMP03 High Voltage AD628 AD629 Single-Supply Current Sense AD8202 AD8203 AD8205 AD8206 AD8216 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. AD8275 TABLE OF CONTENTS Features .............................................................................................. 1 Reference ..................................................................................... 12 Applications ....................................................................................... 1 Common-Mode Input Voltage Range ..................................... 12 Pin Configuration ............................................................................. 1 Input Protection ......................................................................... 12 Typical Application........................................................................... 1 Configurations ............................................................................ 13 General Description ......................................................................... 1 Applications Information .............................................................. 14 Revision History ............................................................................... 2 Driving a Single-Ended ADC ................................................... 14 Specifications..................................................................................... 3 Differential Outputs ................................................................... 14 Absolute Maximum Ratings............................................................ 4 Increasing Input Impedance ..................................................... 15 Maximum Power Dissipation ..................................................... 4 AC Coupling ............................................................................... 15 ESD Caution .................................................................................. 4 Pin Configuration and Function Descriptions ............................. 5 Using the AD8275 as a Level Translator in a Data Acquisition System .......................................................................................... 15 Typical Performance Characteristics ............................................. 6 Outline Dimensions ....................................................................... 16 Theory of Operation ...................................................................... 11 Ordering Guide .......................................................................... 16 Basic Connection........................................................................ 11 Power Supplies ............................................................................ 12 REVISION HISTORY 10/08—Revision 0: Initial Version Rev. 0 | Page 2 of 16 AD8275 SPECIFICATIONS VS = 5 V, G = 0.2, REF1 connected to GND and REF2 connected to 5 V, RL = 2 kΩ connected to VS/2, TA = 25°C, unless otherwise noted. Specifications referred to output unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Small Signal Bandwidth Slew Rate Settling Time to 0.01% Settling Time to 0.001% Overload Recovery Time NOISE/DISTORTION 1 THD + N Voltage Noise Spectral Noise Density GAIN Gain Error Gain Drift Gain Nonlinearity OFFSET AND CMRR Offset 2 vs. Temperature vs. Power Supply Reference Divider Accuracy Common-Mode Rejection Ratio 3 INPUT CHARACTERISTICS Input Voltage Range 4 Impedance 5 Differential Common Mode OUTPUT CHARACTERISTICS Output Swing Capacitive Load 6 Short-Circuit Current Limit POWER SUPPLY Specified Voltage Range Operating Voltage Range Supply Current Over Temperature TEMPERATURE RANGE Specified Performance Test Conditions/Comments Min −3 dB 4 V step 4 V step on output, CL = 100 pF 4 V step on output, CL = 100 pF 50% overdrive 10 20 f = 1 kHz, VOUT = 4 V p-p, 22 kHz band pass filter f = 0.1 Hz to 10 Hz, referred to output f = 1 kHz, referred to output VREF2 = 4.096 V, REF1 and RL connected to GND, (VIN+) − (VIN−) = −10 V to +10 V A Grade Typ Max 15 25 350 450 300 Min 10 20 106 1 40 0.2 −40°C to +85°C VOUT = 4 V p-p, RL = 600 Ω, 2 kΩ, 10 kΩ 1 2.5 Referred to output, VS = ±2.5 V, reference and input pins grounded −40°C to +85°C VS = 3.3 V to 5 V 300 90 VCM = ±10 V, referred to output 80 B Grade Typ 15 25 350 450 300 4 1 40 0.2 0.024 3 700 −12.3 μV p-p nV/√Hz V/V 0.3 2.5 0.024 1 3 % ppm/°C ppm 150 500 μV 2.5 7 μV/°C dB % dB 0.024 86 +12 −12.3 108||2 27.5||2 −VS + 0.048 −VS + 0.048 100 30 IO = 0 mA, VS = ±2.5 V, reference and input pins grounded IO = 0 mA, VS = ±2.5 V, reference and input pins grounded, −40°C to +85°C −40 1 +VS − 0.1 1.9 2.1 2.7 +85 1.9 15 2.3 V V mA 2.1 2.7 mA +85 °C 3.3 −40 V pF mA 5 15 2.3 V kΩ||pF kΩ||pF 100 30 5 3.3 +12 108||2 27.5||2 +VS − 0.1 MHz V/μs ns ns ns dB 100 96 Unit 4 0.024 VREF2 = 4.096 V, REF1 and RL connected to GND, RL = 2 kΩ 450 550 106 2.5 VCM = VS/2 Max Includes amplifier voltage and current noise, as well as noise of internal resistors. Includes input bias and offset current errors. 3 See Figure 7 for CMRR vs. temperature. 4 The input voltage range is a function of the voltage supplies, reference voltage, and ESD diodes. When operating on other supply voltages, see the Absolute Maximum Ratings section, Figure 11, and Table 5 for more information. 5 Internal resistors are trimmed to be ratio matched but have ±20% absolute accuracy. 6 See Figure 25 to Figure 28 in the Typical Performance Characteristics section for more information. 2 Rev. 0 | Page 3 of 16 AD8275 ABSOLUTE MAXIMUM RATINGS Table 3. The difference between the total drive power and the load power is the drive power dissipated in the package. PD = Quiescent Power + (Total Drive Power − Load Power) ⎛V V PD = (VS × I S ) + ⎜⎜ S × OUT RL ⎝ 2 3 mA ⎞ VOUT 2 ⎟– ⎟ RL ⎠ In single-supply operation with RL referenced to –VS, the worst case is VOUT = VS/2. −65°C to +130°C −40°C to +85°C 135°C/W 140°C Airflow increases heat dissipation, effectively reducing θJA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces θJA. 2 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature on a 4-layer JEDEC standard board. 2.00 MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8275 package is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 140°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8275. Exceeding a junction temperature of 140°C for an extended period can result in changes in silicon devices, potentially causing failure. The still air thermal properties of the package and PCB (θJA), the ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature is calculated as follows: 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 –40 07546-003 Voltage at +IN, −IN Pins Voltage at REFx, +VS, − VS, SENSE, and OUT Pins Current into REFx, +IN, −IN, SENSE, and OUT Pins Storage Temperature Range Specified Temperature Range Thermal Resistance (θJA) Package Glass Transition Temperature (TG) ESD Human Body Model Rating 18 V See derating curve (Figure 3) −VS + 40 V, +VS − 40 V −VS − 0.5 V, +VS + 0.5 V MAXIMUM POWER DISSIPATION (W) Parameter Supply Voltage Output Short-Circuit Current midsupply, the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some of which is dissipated in the load (VOUT × IOUT). –20 0 20 40 60 80 100 120 AMBIENT TEMPERATURE (°C) Figure 3. Maximum Power Dissipation vs. Ambient Temperature ESD CAUTION TJ = TA + (PD × θJA) The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to Rev. 0 | Page 4 of 16 AD8275 REF1 1 –IN 2 +IN 3 –VS 4 AD8275 TOP VIEW (Not to Scale) 8 REF2 7 +VS 6 OUT 5 SENSE 07546-001 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic REF1 −IN +IN −VS SENSE OUT +VS REF2 Description Reference Pin. Sets the output voltage level (see the Reference section). Negative Input Pin. Positive Input Pin. Negative Supply Pin. Sense Output Pin. Tie this pin to the OUT pin. Output Pin (Force Output). Positive Supply Pin. Reference Pin. Sets the output voltage level (see the Reference section). Rev. 0 | Page 5 of 16 AD8275 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, G = 0.2, REF1 connected to GND and REF2 connected to 5 V, RL = 2 kΩ connected to VS/2, TA = 25°C, unless otherwise noted. 300 250 14 200 OFFSET VOLTAGE (µV) 12 8 6 4 100 50 0 –50 –100 –150 –200 07546-004 2 0 –600 –400 –200 0 200 400 07546-007 HITS 10 150 –250 NORMALIZED AT 25°C, REPRESENTATIVE SAMPLES –300 –40 –20 0 20 40 60 80 100 600 120 TEMPERATURE (°C) OFFSET VOLTAGE (µV) Figure 5. Typical Distribution of System Offset Voltage, Referred to Output Figure 8. Offset Voltage vs. Temperature, Normalized at 25°C, Referred to Output 50 70 40 60 30 GAIN ERROR (µV/V) 50 HITS 40 30 20 20 10 0 –10 –20 –40 07546-005 0 –60 –40 –20 0 20 40 07546-008 –30 10 GAIN ERROR NORMALIZED AT 25°C –50 –45 –30 –15 0 15 30 45 60 75 60 90 105 120 TEMPERATURE (°C) CMRR (µV/V) Figure 6. Typical Distribution of CMRR, Referred to Output Figure 9. Gain Error vs. Temperature, Normalized at 25°C 5 60 QUIESCENT CURRENT (mA) 40 0 –20 4 3 5V 3.3V 2 –60 –40 –20 0 20 40 60 80 100 1 –50 120 TEMPERATURE (°C) 07546-009 –40 07546-006 CMRR (µV/V) 20 –25 0 25 50 75 100 TEMPERATURE (°C) Figure 7. CMRR vs. Temperature, Normalized at 25°C Figure 10. Quiescent Current vs. Temperature Rev. 0 | Page 6 of 16 125 AD8275 35 120 20 15 10 5 0 –5 –10 –15 –20 –25 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 100 80 60 40 20 0 07546-013 POWER SUPPLY REJECTION (dB) 25 07546-010 INPUT COMMON-MODE VOLTAGE (V) 30 –20 100 5.5 1k Figure 11. Input Common-Mode Voltage vs. Output Voltage, No Load –15 –20 –25 –30 07546-011 –35 1k 10k 100k 1M 10M 5 4 3 2 1 0 100 100M 07546-014 MAXIMUM OUTPUT VOLTAGE (V p-p) GAIN (dB) –10 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 15. Maximum Output Voltage vs. Frequency Figure 12. Gain vs. Frequency 100 20 15 GAIN NONLINEARITY (ppm) 90 80 70 60 50 1k 10k 100k 1M 10 5 0 –5 –10 –20 10M 07546-015 –15 07546-012 COMMON-MODE REJECTION (dB) 1M 6 –5 40 100 100k Figure 14. Power Supply Rejection vs. Frequency, Referred to Output 0 –40 100 10k FREQUENCY (Hz) OUTPUT VOLTAGE (V) 0 1 2 3 OUTPUT VOLTAGE (V) FREQUENCY (Hz) Figure 16. Gain Nonlinearity, RL = 600 Ω, 2 kΩ, 10 kΩ Figure 13. Common-Mode Rejection vs. Frequency, Referred to Input Rev. 0 | Page 7 of 16 4 AD8275 60 +VS 50 +VS – 0.4 3.3V SOURCE CURRENT (mA) 20 10 0 –10 –20 3.3V SINK –30 –40 5V SINK –70 –50 –25 0 25 50 75 100 +VS – 1.6 +VS – 2.0 –VS + 2.0 –VS + 1.6 –VS + 1.2 –VS + 0.8 +25°C –VS + 0.4 –VS 125 Figure 17. Short-Circuit Current vs. Temperature, VS = 3.3 V, 5 V 2 14 +VS – 0.8 +VS – 1.0 –VS + 1.0 –VS + 0.8 +125°C –VS + 0.6 +85°C –VS + 0.4 +25°C –40°C 100 100 1k 10k 07546-019 VOLTAGE NOISE DENSITY (nV/√Hz) +VS – 0.6 07546-017 OUTPUT VOLTAGE SWING (V) (REFERRED TO SUPPLY RAILS) 12 +25°C +85°C +125°C –VS + 0.2 10 1 100k RLOAD (Ω) 10 100 1k 10k 100k FREQUENCY (Hz) Figure 18. Output Voltage Swing vs. RLOAD, VS = 5 V +VS Figure 21. Voltage Noise Density vs. Frequency, Referred to Output –40°C +25°C +VS – 0.4 +125°C +85°C VOLTAGE NOISE (1µV/DIV) +VS – 0.8 +VS – 1.2 +VS – 1.6 +VS – 2.0 –VS + 2.0 –VS + 1.6 –VS + 1.2 +25°C –VS + 0.4 +85°C +125°C –40°C 0 2 4 6 8 10 OUTPUT CURRENT (mA) 12 14 Figure 19. Output Voltage Swing vs. Output Current, VS = 3.3 V 07546-020 –VS + 0.8 07546-018 OUTPUT VOLTAGE SWING (V) (REFERRED TO SUPPLY RAILS) 6 8 10 OUTPUT CURRENT (mA) 1k +VS – 0.2 –VS 4 Figure 20. Output Voltage Swing vs. Output Current, VS = 5 V –40°C +VS – 0.4 –VS +85°C +125°C –40°C 0 TEMPERATURE (°C) +VS +25°C +VS – 1.2 07546-016 –50 –60 +125°C +85°C +VS – 0.8 OUTPUT VOLTAGE SWING (V) (REFERRED TO SUPPLY RAILS) 5V SOURCE 30 TIME (1s/DIV) Figure 22. 0.1 Hz to 10 Hz Voltage Noise, Referred to Output Rev. 0 | Page 8 of 16 07546-119 40 –40°C AD8275 40 60 35 50 30 OVERSHOOT (%) SLEW RATE (V/µs) +SR 25 –SR 20 15 40 3.3V 30 5V 20 10 07546-021 0 –40 –20 0 20 40 60 80 100 0 120 07546-024 10 5 0 20 40 TEMPERATURE (°C) 100 120 140 160 60 2kΩ NO LOAD 50 OVERSHOOT (%) 600Ω 40 3.3V 30 5V 20 10 07546-022 10kΩ 0 1µs/DIV 07546-025 20mV/DIV 80 Figure 26. Small Signal Overshoot vs. Capacitive Load, No Resistive Load Figure 23. Slew Rate vs. Temperature CLOAD = 47pF 60 CAPACITANCE (pF) 0 20 40 60 80 100 120 140 160 CAPACITANCE (pF) Figure 27. Small Signal Overshoot vs. Capacitive Load, 600 Ω in Parallel with Capacitive Load Figure 24. Small Signal Step Response for Various Resistive Loads (Step Responses Staggered for Clarity) 60 NO RESISTIVE LOAD 100pF 50 OVERSHOOT (%) 20mV/DIV NO CAP 40 3.3V 30 5V 20 10 07546-023 47pF 0 1µs/DIV 07546-026 20pF 0 20 40 60 80 100 120 140 CAPACITANCE (pF) Figure 28. Small Signal Overshoot vs. Capacitive Load, 2 kΩ in Parallel with Capacitive Load Figure 25. Small Signal Pulse Response for Various Capacitive Loads (Step Responses Staggered for Clarity) Rev. 0 | Page 9 of 16 160 AD8275 1.0 VOUT = 4V p-p 0.1 THD + N (%) 10V/DIV 0.01 RL = 600Ω 10mV/DIV 0.001 RL = 10kΩ 0.0001 10 100 1k 10k FREQUENCY (Hz) Figure 29. Large Signal Pulse Response and Settling Time, RL = 2 kΩ Figure 30. THD + N vs. Frequency, VOUT = 4 V p-p Rev. 0 | Page 10 of 16 07546-029 07546-027 2µs/DIV RL = 2kΩ 100k AD8275 THEORY OF OPERATION The AD8275 level translates ±10 V signals at its inputs to 4 V at its output. It does this by attenuating the input signal by 5. A subtractor network performs the attenuation, the level shifting, and the differential-to-single-ended conversion. One benefit of the subtractor topology is that it can accept input signals beyond its supply voltage. The subtractor is composed of tightly matched resistors. By integrating the resistors and trimming the resistor ratios, the AD8275 achieves 80 dB CMRR and 0.024% gain error. +VS –IN INPUT ESD 50kΩ 10kΩ SENSE +VS –VS –VS +VS +VS 7kΩ BASIC CONNECTION The basic configurations for the AD8275 are shown in Figure 33 and Figure 34. In Figure 33, REF1 and REF2 are tied together. A voltage, VREF, applied to the tied REF1 and REF2 pins, sets the output voltage level to VREF. For example, in Figure 33, if VREF = 2 V and the inputs are tied to ground, the output remains at 2 V. +5V OUT 7kΩ 2.5V The AD8275 employs a balanced, high gain, linear output stage that adaptively generates current as required, eliminating the dynamic errors found in other amplifiers. This is useful when driving SAR ADCs, which can deliver kickback current into the output of the amplifier. The result is a design that achieves low distortion, consistent bandwidth, and high slew rate. 0.1µF –VS –VS 7 +VS –VS –VS +VS +VS 20kΩ VINN 2 REF2 10kΩ 50kΩ –IN 5 SENSE –VS OUT INPUT ESD REF1 50kΩ –VS VINP 3 50kΩ VREF 20kΩ +IN 20kΩ Figure 31. AD8275 Simplified Schematic REF2 REF1 To achieve a wider input voltage range, the AD8275 uses an internal 2.5 V voltage bias tied to –VS and two 7 kΩ resistors, as shown in Figure 31. The resistors help to set the common mode of the internal amplifier. The benefit of this circuit is that it extends the input range without causing crossover distortion typical of amplifiers that have rail-to-rail complementary transistor inputs. The input range of the internal op amp is +VS − 0.9 V to −VS + 1.35 V. 600 AD8275 VOUT = (VINP) – (VINN) 5 VOUT 6 8 1 –VS 4 07546-031 +IN 20kΩ 07546-030 +VS + VREF Figure 33. Basic Configuration 1: Shared Reference In contrast, Figure 34 shows REF1 tied to ground and REF2 tied to VREF. In this example, the two 20 kΩ resistors serve as a resistor divider, and VREF is divided by 2. For example, if both inputs of the AD8275 are grounded and VREF = 5 V, the output is 2.5 V. 400 +5V 0.1µF 7 +VS 0 VINN 2 50kΩ 10kΩ –IN 5 SENSE –200 OUT 07546-132 –600 –10 –8 –6 –4 –2 0 2 4 6 8 VINP 3 50kΩ VREF 20kΩ +IN 20kΩ 10 REF2 REF1 COMMON-MODE VOLTAGE (V) AD8275 Figure 32. AD8275 Does Not Have Crossover Distortion Typical of Rail-to-Rail Input Amplifiers VOUT = VOUT 6 –400 8 1 –VS 4 (VINP) – (VINN) 5 + VREF + 0V 2 07546-032 OFFSET (µV) 200 Figure 34. Basic Configuration 2: Split Reference Rev. 0 | Page 11 of 16 AD8275 POWER SUPPLIES COMMON-MODE INPUT VOLTAGE RANGE Use a stable dc voltage to power the AD8275. Noise on the supply pins can adversely affect performance. Place a bypass capacitor of 0.1 μF between each supply pin and ground, as close to each pin as possible. A tantalum capacitor of 10 μF should also be used between each supply and ground. It can be farther away from the AD8275 and typically can be shared by other precision integrated circuits. The common-mode voltage range is a function of the input voltage range of the internal op amp, the supply voltage, and the reference voltage. REFERENCE Equation 2 expresses the minimum common-mode voltage range. The reference terminals are used to provide a bias level for the output. For example, in a single-supply 5 V operation, the reference terminals can be set so that the output is biased at 2.5 V. This ensures that the output can swing positive or negative around a 2.5 V level. Figure 33 and Figure 34 illustrate two different ways to set the reference voltage. See the Basic Connection section for the differences between the two settings. The allowable reference voltage range is a function of the common-mode input and supply voltages. The REF1 and REF2 pins should not exceed either +VS or −VS by more than 0.5 V. The REFx terminals should be driven by low source impedance because parasitic resistance in series with REF1 and REF2 can adversely affect CMRR and gain accuracy. INCORRECT +VS +VS 7 7 10kΩ SENSE 50kΩ 5 –IN OUT 3 20kΩ REF2 50kΩ +IN 20kΩ REF1 AD8275 2 NSE 10kΩ SENSE 50kΩ 50 5 –IN OUT O 6 VREF 3 8 R 20kΩ 0kΩ REF2 50kΩ 0kΩ +IN 20kΩ REF1 1 AD8275 –VS 4 +VS 7 50kΩ 10kΩ SENSE 5 20kΩ REF2 50kΩ +IN AD8275 20kΩ REF1 –VS 4 2 50kΩ 50 8 R 20kΩ 0kΩ REF2 50kΩ 0kΩ 20kΩ REF1 1 AD8275 –VS 4 Figure 35. REF1 and REF2 Pin Guidelines (2) The voltage range of the internal op amp varies depending on temperature. The equations reflect a typical input voltage range of +VS − 0.9 V and −VS + 1.35 V over temperature. Table 5 lists expected common-mode ranges for typical configurations. Table 5. Expected Common-Mode Voltage Range for Typical Configurations +VS (V)1 5 5 5 3.3 3.3 5 5 5 5 5 5 5 1 VREF1 (V) 5 2.5 4.096 3.3 2.5 5 4.096 3 2.5 2.048 1.25 0 VREF2 (V) 0 0 0 0 0 5 4.096 3 2.5 2.048 1.25 0 VCM+ (V) 23.5 29.8 25.8 5.4 7.4 11.0 15.5 21.0 23.5 25.8 29.8 36.0 VCM− (V) −12.6 −6.4 −10.4 −8.4 −6.4 −25.1 −20.6 −15.1 −12.6 −10.4 −6.4 −0.1 –VS = 0 V. INPUT PROTECTION 1 5 +IN VCM_NEG ≥ 6(–VS) – 5((REF1 + REF2)/2) – 0.11 8 NSE 10kΩ SENSE OUT 3 VCM_POS ≤ 13.14(+VS) – 7.14(–VS) – 5((REF1 + REF2)/2) – 29.69 (1) The inputs of the AD8275, +IN and −IN, are protected by ESD diodes that clamp 40 V above −VS and 40 V below +VS. When operating on a single +5 V supply, the ESD diode conducts at input voltages less than −35 V and greater than +40 V. –IN 6 VREF VREF 4 7 –IN 6 –VS +VS OUT 3 2 6 VREF 8 1 07546-033 2 CORRECT Equation 1 expresses the maximum positive common-mode voltage range. If the input voltage is expected to exceed the maximum ratings of the AD8275, use external transorbs. Adding series resistors to the inputs of the AD8275 is not recommended because the internal resistor ratios are matched to provide optimal CMRR and gain accuracy. Adding external series resistors to the input degrades the performance of the AD8275. All other pins are protected by ESD diodes that clamp 0.5 V beyond either supply rail. For example, the voltage range of the REF1 and REF2 pins on a 5 V supply is −0.5 V to +5.5 V. Rev. 0 | Page 12 of 16 AD8275 CONFIGURATIONS Figure 36 and Figure 37, along with Table 6 and Table 7, provide examples of the possible input and output ranges for various supplies and reference voltages. Note that Table 6 and Table 7 list the typical voltage range of the AD8275; these values do not reflect variation over process or temperature. +5V +5V 0.1µF LINEAR VIN RANGE HI VINN 2 HI 7 10kΩ –IN 5 LINEAR VIN RANGE HI VINN 2 +SWING +VS 50kΩ 0.1µF USEFUL VOUT –SWING LO SENSE OUT MID 6 +SWING +VS 50kΩ 10kΩ –IN 5 OUT 6 VOUT VREF VINP 3 50kΩ 20kΩ +IN 20kΩ REF2 REF1 8 VINP 3 20kΩ +IN 20kΩ –VS 4 AD8275 Linear Differential VIN Range High: +12 V Mid: 0 V Low: −12.3 V +VS1 5V VREF 5V 5V 2.5 V 1.25 V High: +18.3 V Mid: 0 V Low: −6 V 5V 4.096 V 2.048 V High: +14.3 V Mid: 0 V Low: −10 V 3.3 V 3.3 V 1.65 V High: +8 V Mid: 0 V Low: −8 V 3.3 V 2.5 V 1.25 V High: +10 V Mid: 0 V Low: −6 V 8 1 –VS 4 Figure 37. Shared Reference Table 6. Input and Output Relationships for Split Reference Configuration in Figure 36 VOUT for VIN = 0 V 2.5 V REF2 REF1 Figure 36. Split Reference 1 50kΩ 1 07546-136 AD8275 VREF LO 07546-137 LO –SWING LO SENSE MID VOUT USEFUL VOUT HI 7 Useful VOUT Ranges High: +4.95 V Swing: +2.45 V, −2.455 V Low: +0.045 V High: +4.95 V Swing: +3.7 V, −1.205 V Low: +0.045 V High: +4.95 V Swing: +2.902 V, −2.003 V Low: +0.045 V High: +3.24 V Swing: +1.59 V, −1.605 V Low: +0.045 V High: +3.24 V Swing: +1.99 V, −1.205 V Low: +0.045 V Table 7. Input and Output Relationships for Shared Reference Configuration in Figure 37 Linear Differential VIN Range High: −0.1 V Mid: 0 V Low: −24.7 V High: +4.4 V Mid: 0 V Low: −20.2 V +VS1 5V VREF 5V VOUT for VIN = 0 V 5V 5V 4.096 V 4.096 V 5V 3V 3V High: +9.5 V Mid: 0 V Low: −14.8 V 5V 2.5 V 2.5 V High: +12 V Mid: 0 V Low: −12.3 V 5V 2.048 V 2.048 V High: +14.3 V Mid: 0 V Low: −10 V 5V 1.25 V 1.25 V +18.3 V to −6 V 0V 0V 0V 24.5 V to 0.2 V −VS = 0 V. 1 −VS = 0 V. Rev. 0 | Page 13 of 16 Useful VOUT Ranges High: +4.98 V Swing: −4.94 V Low: +0.06 V High: +4.98 V Swing: +0.884 V to −4.03 V Low: +0.06 V High: +4.95 V Swing: +1.9 V, −2.955 V Low: +0.045 V High: +4.95 V Swing: +2.45 V, −2.455 V Low: +0.045 V High: +4.95 V Swing: +2.902 V, −2.003 V Low: +0.045 V High: +4.95 V Swing: +3.7 V, −1.205 V Low: +0.045 V High: 4.95 V Swing: 4.95 V Low: 0.045 V AD8275 DRIVING A SINGLE-ENDED ADC ADC FULL SCALE (dB) The AD8275 provides the common-mode rejection that SAR ADCs often lack. In addition, it enables designers to use costeffective, precision, 16-bit ADCs such as the AD7685, yet still condition ±10 V signals. One important factor in selecting an ADC driver is its ability to settle within the acquisition window of the ADC. The AD8275 is able to drive medium speed SAR ADCs. In Figure 38, the 2.7 nF capacitor serves to store and deliver necessary charge to the switched capacitor input of the ADC. The 33 Ω series resistor reduces the burden of the 2.7 nF load from the amplifier and isolates it from the kickback current injected from the switched capacitor input of the AD7685. The output impedance of the amplifier can affect the THD of the ADC. In this case, the combined impedance of the 33 Ω resistor and the output impedance of the AD8275 provides extremely low THD of −112 dB. Figure 39 shows the ac response of the AD8275 driving the AD7685. 10kΩ OUT 20kΩ +IN 20kΩ REF2 REF1 AD8275 –VS VDD IN+ IN– REF GND 8 1 VREF (ADR444, ADR445) 10µF 4 Figure 38. Driving a Single-Ended ADC 8 9 10 When using this circuit to drive a differential ADC, VREF can be set using a resistor divider from the ADC reference to make the output ratiometric with the ADC. +5V 0.1µF 7 +VS 2 10kΩ 50kΩ SENSE –IN OUT 5 +10V 3 50kΩ 6 AD8275 20kΩ +2.5V +0.5V AD8655 VREF = 2.5V 20kΩ +IN +4.5V +VOUT 2kΩ –10V 7 Figure 40 shows how to configure the AD8275 to output a differential signal. The AD8655 op amp is used in an inverting topology to create a differential voltage. VREF sets the output midpoint. Errors from the op amp are common to both outputs and are thus common mode. Likewise, errors from using mismatched resistors cause a common-mode dc offset error. Such errors are rejected in differential signal processing by differential input ADCs or by instrumentation amplifiers. AD7685 2.7nF 07546-034 VIN 3 50kΩ 33Ω 6 4 5 6 FREQUENCY (kHz) In certain applications, it is necessary to create a differential signal. For example, high resolution ADCs often require a differential input. In other cases, transmission over a long distance can require differential signals for better immunity to interference. 5 SENSE 3 REF2 REF1 8 1 8.2µF 2kΩ +5V 0.1µF +4.5V –VS +2.5V 4 –VOUT +0.5V Figure 40. AD8275 Configured for Differential Output (for Driving a Differential ADC) Rev. 0 | Page 14 of 16 07546-035 –IN 2 DIFFERENTIAL OUTPUTS 0.1µF +VS 2 1 The AD8275 can condition signals for higher resolution ADCs such as 18-bit SAR converters, provided that a narrower bandwidth is sampled to limit noise. 7 50kΩ 0 Figure 39. FFT of AD8275 Directly Driving the AD7685 Using the 5 V Reference of the Evaluation Board (Input = 20 V p-p, 1 kHz, THD = −112 dB) +5V 0.1µF 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 07546-139 APPLICATIONS INFORMATION AD8275 INCREASING INPUT IMPEDANCE USING THE AD8275 AS A LEVEL TRANSLATOR IN A DATA ACQUISITION SYSTEM In applications where a high input impedance is needed, low input bias current op amps can be used to buffer the AD8275. In Figure 41, an AD8620 is used to provide high input impedance. Input bias current is limited to 10 pA. Signal size varies dramatically in some data acquisition applications. Instrumentation amplifiers, such as the AD8253, AD8228, or AD8221, are often used at the inputs to provide CMRR and high input impedance. However, the instrumentation amplifiers output ±10 V signals and the ADC full scale is 5 V or 4.096 V. In Figure 43, the AD8275 serves as a level translator between the in-amp and the ADC. The AD8275, along with the AD8228 and the AD8253, have very low gain drift because all gain setting resistors are internal and laser-trimmed. +5V 0.1µF 8 INVERTING INPUT 7 2 +VS 0.1µF 3 1 AD8620 50kΩ 2 10kΩ SENSE –IN 1/2 OUT AD8620 7 2/2 5 NONINVERTING INPUT 0.1µF 4 50kΩ 3 +IN AD8275 –13V 20kΩ REF2 20kΩ REF1 +5V VOUT 6 0.1µF VREF +VS 1 2 –VS 4 OUT When a signal exceeds fHIGH-PASS, the AD8275 outputs the conditioned input signal. +5V VOUT 0.1µF 7 10kΩ 50kΩ –IN OUT 3 fHIGH-PASS = 5 SENSE 50kΩ 20kΩ +IN 20kΩ REF2 REF1 AD8275 1 2πRC VOUT 6 C 8 R 1 OP AMP –VS 4 0.1µF +5V VREF 07546-037 2 50kΩ 20kΩ +IN 20kΩ REF2 REF1 –15V Figure 42. AC-Coupled Level Translator Rev. 0 | Page 15 of 16 0.1µF 33Ω AD8275 VCC +IN ADC 6 2.7nF 3 AC COUPLING 5 SENSE 0.1µF IN-AMP An integrator can be tied to the AD8275 in feedback to create a high-pass filter as shown in Figure 42. This circuit can be used to reject dc voltages and offsets. At low frequencies, the impedance of the capacitor, C, is high. Thus, the gain of the integrator is high. DC voltage at the output of the AD8275 is inverted and gained by the integrator. The inverted signal is injected back into the REFx pins, nulling the output. In contrast, at high frequencies, the integrator has low gain because the impedance of C is low. Voltage changes at high frequencies are inverted but at a low gain. The signal is injected into the REFx pins but it is not enough to null the output. High frequency signals are, therefore, allowed to pass. 10kΩ 50kΩ –IN +15V Figure 41. Adding Op Amp Buffers for High Input Impedance +VS 0.1µF 7 8 07546-036 6 5 –IN REF GND 8 1 VREF 10µF –VS 4 Figure 43. Level Translation in a Data Acquisition System 07546-143 +13V AD8275 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5 5.15 4.90 4.65 4 PIN 1 0.65 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.00 0.38 0.22 COPLANARITY 0.10 0.23 0.08 8° 0° 0.80 0.60 0.40 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 44. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model AD8275ARMZ 1 AD8275ARMZ-R71 AD8275ARMZ-RL1 AD8275BRMZ1 AD8275BRMZ-R71 AD8275BRMZ-RL1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead MSOP 8-Lead MSOP, Tape and Reel 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP 8-Lead MSOP, Tape and Reel 8-Lead MSOP, 13" Tape and Reel Z = RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07546-0-10/08(0) Rev. 0 | Page 16 of 16 Package Option RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 Branding Y13 Y13 Y13 Y1V Y1V Y1V