AD AD8656

Low Noise,
Precision CMOS Amplifier
AD8655/AD8656
NC 1
–IN 2
AD8655
+IN 3
TOP VIEW
(Not to Scale)
V– 4
8
NC
OUT A 1
7
V+
–IN A 2
6
OUT
+IN A 3
5
NC
NC = NO CONNECT
Figure 1. AD8655
8-Lead MSOP (RM-8)
V– 4
AD8656
TOP VIEW
(Not to Scale)
8
V+
7
OUT B
6
–IN B
5
+IN B
05304-059
Low noise: 2.7 nV/√Hz @ f = 10 kHz
Low offset voltage: 250 μV max over VCM
Offset voltage drift: 0.4 μV/°C typ and 2.3 μV/°C max
Bandwidth: 28 MHz
Rail-to-rail input/output
Unity gain stable
2.7 V to 5.5 V operation
−40°C to +125°C operation
PIN CONFIGURATIONS
05304-048
FEATURES
Figure 2. AD8656
8-Lead MSOP (RM-8)
NC 1
–IN 2
+IN 3
AD8655
TOP VIEW
V– 4 (Not to Scale)
8
NC
OUT A 1
7
V+
–IN A 2
6
OUT
+IN A 3
5
NC
NC = NO CONNECT
Figure 3. AD8655
8-Lead SOIC (R-8)
05304-049
ADC and DAC buffers
Audio
Industrial controls
Precision filters
Digital scales
Strain gauges
PLL filters
AD8656
8
V+
7
OUT B
6 –IN B
TOP VIEW
V– 4 (Not to Scale) 5 +IN B
05304-060
APPLICATIONS
Figure 4. AD8656
8-Lead SOIC (R-8)
GENERAL DESCRIPTION
The AD8655/AD8656 are the industry’s lowest noise, precision
CMOS amplifiers. They leverage the Analog Devices DigiTrim®
technology to achieve high dc accuracy.
The AD8655/AD8656 provide low noise (2.7 nV/√Hz @ 10 kHz),
low THD + N (0.0007%), and high precision performance
(250 μV max over VCM) to low voltage applications. The ability
to swing rail-to-rail at the input and output enables designers
to buffer analog-to-digital converters (ADCs) and other wide
dynamic range devices in single-supply systems.
The high precision performance of the AD8655/AD8656
improves the resolution and dynamic range in low voltage
applications. Audio applications, such as microphone pre-amps
and audio mixing consoles, benefit from the low noise, low
distortion, and high output current capability of the AD8655/
AD8656 to reduce system level noise performance and maintain
audio fidelity. The high precision and rail-to-rail input and
output of the AD8655/AD8656 benefit data acquisition, process
controls, and PLL filter applications.
The AD8655/AD8656 are fully specified over the −40°C to
+125°C temperature range. The AD8655/AD8656 are available
in Pb-free, 8-lead MSOP and SOIC packages.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD8655/AD8656
TABLE OF CONTENTS
Specifications..................................................................................... 3
Driving Capacitive Loads.......................................................... 16
Absolute Maximum Ratings............................................................ 5
Layout, Grounding, and Bypassing Considerations .................. 18
ESD Caution.................................................................................. 5
Power Supply Bypassing ............................................................ 18
Typical Performance Characteristics ............................................. 6
Grounding ................................................................................... 18
Theory of Operation ...................................................................... 15
Leakage Currents........................................................................ 18
Applications..................................................................................... 16
Outline Dimensions ....................................................................... 19
Input Overvoltage Protection ................................................... 16
Ordering Guide .......................................................................... 19
Input Capacitance....................................................................... 16
REVISION HISTORY
6/05—Rev. 0 to Rev. A
Added AD8656 ...................................................................Universal
Added Figure 2 and Figure 4........................................................... 1
Changes to Specifications ................................................................ 3
Changed Caption of Figure 12 and Added Figure 13 .................. 7
Replaced Figure 16 ........................................................................... 7
Changed Caption of Figure 37 and Added Figure 38 ................ 11
Replaced Figure 47 ......................................................................... 13
Added Figure 55.............................................................................. 14
Changes to Ordering Guide .......................................................... 18
4/05—Revision 0: Initial Version
Rev. A | Page 2 of 20
AD8655/AD8656
SPECIFICATIONS
VS = 5.0 V, VCM = VS/2, TA = 25°C, unless otherwise specified.
Table 1.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Conditions
VOS
VCM = 0 V to 5 V
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Bias Current
ΔVOS/ΔT
IB
Input Offset Current
IOS
Min
Typ
Max
Unit
50
250
550
2.3
10
500
10
500
5
μV
μV
μV/°C
pA
pA
pA
pA
V
dB
dB
dB
0.4
1
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Output Current
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
0
85
100
95
CMRR
AVO
VCM = 0 V to 5 V
VO = 0.2 V to 4.8 V, RL = 10 kΩ, VCM = 0 V
−40°C ≤ TA ≤ +125°C
VOH
VOL
IOUT
IL = 1 mA; −40°C ≤ TA ≤ +125°C
IL = 1 mA; −40°C ≤ TA ≤ +125°C
VOUT = ±0.5 V
4.97
PSRR
ISY
VS = 2.7 V to 5.0 V
VO = 0 V
−40°C ≤ TA ≤ +125°C
88
INPUT CAPACITANCE
Differential
Common-Mode
NOISE PERFORMANCE
Input Voltage Noise Density
CIN
Total Harmonic Distortion + Noise
FREQUENCY RESPONSE
Gain Bandwidth Product
Slew Rate
Settling Time
Phase Margin
THD + N
en
GBP
SR
ts
100
110
4.991
8
±220
105
3.7
30
4.5
5.3
V
mV
mA
dB
mA
mA
9.3
16.7
pF
pF
f = 1 kHz
f = 10 kHz
G = 1, RL = 1 kΩ, f = 1 kHz, VIN = 2 V p-p
4
2.7
0.0007
nV/√Hz
nV/√Hz
%
RL = 10 kΩ
To 0.1%, VIN = 0 V to 2 V step, G = +1
CL = 0 pF
28
11
370
69
MHz
V/μs
ns
degrees
Rev. A | Page 3 of 20
AD8655/AD8656
VS = 2.7 V, VCM = VS/2, TA = 25°C, unless otherwise specified.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Conditions
VOS
VCM = 0 V to 2.7 V
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Bias Current
ΔVOS/ΔT
IB
Input Offset Current
IOS
Min
Typ
Max
Unit
44
250
550
2.0
10
500
10
500
2.7
μV
μV
μV/°C
pA
pA
pA
pA
V
dB
dB
dB
0.4
1
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Output Current
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
0
80
98
90
CMRR
AVO
VCM = 0 V to 2.7 V
VO = 0.2 V to 2.5 V, RL = 10 kΩ, VCM = 0 V
−40°C ≤ TA ≤ +125°C
VOH
VOL
IOUT
IL = 1 mA; −40°C ≤ TA ≤ +125°C
IL = 1 mA; −40°C ≤ TA ≤ +125°C
VOUT = ±0.5 V
2.67
PSRR
ISY
VS = 2.7 V to 5.0 V
VO = 0 V
−40°C ≤ TA ≤ +125°C
88
INPUT CAPACITANCE
Differential
Common-Mode
NOISE PERFORMANCE
Input Voltage Noise Density
CIN
Total Harmonic Distortion + Noise
FREQUENCY RESPONSE
Gain Bandwidth Product
Slew Rate
Settling Time
Phase Margin
THD + N
en
GBP
SR
ts
98
2.688
10
±75
105
3.7
30
4.5
5.3
V
mV
mA
dB
mA
mA
9.3
16.7
pF
pF
f = 1 kHz
f = 10 kHz
G = 1, RL = 1kΩ, f = 1 kHz, VIN = 2 V p-p
4.0
2.7
0.0007
nV/√Hz
nV/√Hz
%
RL = 10 kΩ
To 0.1%, VIN = 0 to 1 V step, G = +1
CL = 0 pF
27
8.5
370
54
MHz
V/μs
ns
degrees
Rev. A | Page 4 of 20
AD8655/AD8656
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage
Output Short-Circuit Duration
to GND
Electrostatic Discharge (HBM)
Storage Temperature Range
R, RM Packages
Junction Temperature Range
R, RM Packages
Lead Temperature
(Soldering, 10 sec)
Rating
6V
VSS − 0.3 V to VDD + 0.3 V
±6 V
Indefinite
3.0 kV
−65°C to +150°C
−65°C to +150°C
260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Package Type
θJA1
θJC
Unit
8-Lead MSOP (RM)
8-Lead SOIC (R)
210
158
45
43
°C/W
°C/W
1
θJA is specified for worst-case conditions; that is, θJA is specified for a device
soldered in the circuit board for surface-mount packages.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 20
AD8655/AD8656
TYPICAL PERFORMANCE CHARACTERISTICS
60
20
VS = ±2.5V
VS = ±2.5V
10
40
VOS (μV)
30
20
10
0
–10
05304-001
–20
0
–150
–100
–50
0
50
VOS (μV)
100
05304-004
NUMBER OF AMPLIFIERS
50
–30
150
0
Figure 5. Input Offset Voltage Distribution
1
2
3
4
COMMON-MODE VOLTAGE (V)
5
6
Figure 8. Input Offset Voltage vs. Common-Mode Voltage
150.0
250
VS = ±2.5V
VS = ±2.5V
100.0
200
50.0
IB (pA)
VOS (μV)
150
0.0
100
–50.0
05304-002
–150.0
–50
0
50
TEMPERATURE (°C)
100
05304-005
50
–100.0
0
150
0
Figure 6. Input Offset Voltage vs. Temperature
40
60
80
100
TEMPERATURE (°C)
120
140
Figure 9. Input Bias Current vs. Temperature
60
4.0
VS = ±2.5V
VS = ±2.5V
3.5
SUPPLY CURRENT (mA)
50
40
30
20
3.0
2.5
2.0
1.5
1.0
10
05304-003
0
0
0.2
0.4
0.6
0.8
1.0
1.2
|TCVOS| (μV/°C)
1.4
0.5
05304-006
NUMBER OF AMPLIFIERS
20
0
1.6
0
1
2
3
4
SUPPLY VOLTAGE (V)
5
Figure 10. Supply Current vs. Supply Voltage
Figure 7. |TCVOS | Distribution
Rev. A | Page 6 of 20
6
AD8655/AD8656
4.5
4.996
VS = ±2.5V
VS = ±2.5V
LOAD CURRENT = 1mA
4.994
4.992
3.5
VOH (V)
SUPPLY CURRENT (mA)
4.0
3.0
4.990
4.988
4.986
2.5
2.0
–50
0
50
TEMPERATURE (°C)
100
4.982
–50
150
Figure 11. Supply Current vs. Temperature
0
50
TEMPERATURE (°C)
100
12
LOAD CURRENT = 1mA
VS = ±2.5V
VS = ±2.5V
10
1500
8
VOL (mV)
2000
VOH
1000
6
VOL
500
0
50
100
150
CURRENT LOAD (mA)
200
05304-010
05304-008
4
0
2
–50
250
0
50
TEMPERATURE (°C)
100
150
Figure 15. Output Voltage Swing Low vs. Temperature
Figure 12. AD8655 Output Voltage to Supply Rail vs. Current Load
120
10000
VS = ±2.5V
VIN = 28mV
RL = 1MΩ
CL = 47pF
VS = ±2.5V
100
1000
CMRR (dB)
80
100
60
40
10
VOL
VOH
1
0.1
1
10
CURRENT LOAD (mA)
100
0
100
1000
Figure 13. AD8656 Output Swing vs. Current Load
05304-011
20
05304-056
DELTA SWING FROM SUPPLY (mV)
150
Figure 14. Output Voltage Swing High vs. Temperature
2500
DELTA SWING FROM SUPPLY (mV)
05304-009
05304-007
4.984
1k
10k
100k
FREQUENCY (Hz)
Figure 16. CMRR vs. Frequency
Rev. A | Page 7 of 20
1M
10M
AD8655/AD8656
100
VOLTAGE NOISE DENSITY (nV/√Hz 1/2)
VS = ±2.5V
VCM = 0V
107.00
CMRR (dB)
104.00
101.00
98.00
05304-012
95.00
92.00
–50
0
50
TEMPERATURE (°C)
100
VS = ±2.5V
10
05304-019
110.00
1
1
150
10
100
1k
FREQUENCY (Hz)
10k
100k
Figure 20. Voltage Noise Density vs. Frequency
Figure 17. Large Signal CMRR vs. Temperature
100
+PSRR
–PSRR
VS = ±2.5V
Vn (p-p) = 1.23μV
60
500nV/DIV
PSRR (dB)
80
VS = ±2.5V
VIN = 50mV
RL = 1MΩ
CL = 47pF
40
1
1k
10k
100k
1M
FREQUENCY (Hz)
10M
05304-020
0
100
05304-013
20
100M
1s/DIV
Figure 21. Low Frequency Noise (0.1 Hz to 10 Hz).
Figure 18. Small Signal PSSR vs. Frequency
110.00
VS = ±2.5V
VIN
108.00
VS = ±2.5V
CL = 50pF
GAIN = +1
1V/DIV
106.00
104.00
2
102.00
0
50
TEMPERATURE (°C)
100
150
05304-021
100.00
–50
05304-014
PSRR (dB)
VOUT
T
20μs/DIV
Figure 22. No Phase Reversal
Figure 19. Large Signal PSSR vs. Temperature
Rev. A | Page 8 of 20
AD8655/AD8656
–45
120
6
100
5
PHASE MARGIN = 69°
PHASE SHIFT (Degrees)
–90
60
40
–135
20
–180
0
4
OUTPUT (V)
80
GAIN (dB)
VS = ±2.5V
VIN = 5V
G = +1
VS = ±2.5V
CLOAD = 11.5pF
3
2
1
100k
1M
FREQUENCY (Hz)
–225
100M
10M
05304-018
–40
10k
05304-015
–20
0
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 26. Maximum Output Swing vs. Frequency
Figure 23. Open-Loop Gain and Phase vs. Frequency
140.00
VS = ±2.5V
RL = 10kΩ
130.00
120.00
VOUT (1V/DIV)
AVO (dB)
T
VS = ±2.5V
CL = 100pF
GAIN = +1
VIN = 4V
110.00
2
90.00
–50
0
50
TEMPERATURE (°C)
100
05304-022
05304-016
100.00
150
TIME (10μs/DIV)
Figure 24. Large Signal Open-Loop Gain vs. Temperature
Figure 27. Large Signal Response
50
VS = ±2.5V
CL = 100pF
G = +1
VOUT (100mV/DIV)
30
20
10
2
0
–10
10k
100k
1M
FREQUENCY (Hz)
10M
05304-023
–20
1k
05304-017
CLOSED-LOOP GAIN (dB)
T
VS = ±2.5V
RL = 1MΩ
CL = 47pF
40
100M
TIME (1μs/DIV)
Figure 25. Closed-Loop Gain vs. Frequency
Figure 28. Small Signal Response
Rev. A | Page 9 of 20
AD8655/AD8656
30
100
OUTPUT IMPEDANCE (Ω)
25
OVERSHOOT %
VS = ±2.5V
VS = ±2.5V
VIN = 200mV
20
–OS
15
10
+OS
G = +100
G = +1
G = +10
10
1
0
0
50
100
150
200
250
CAPACITANCE (pF)
300
0.1
100
350
Figure 29. Small Signal Overshoot vs. Load Capacitance
05304-027
05304-024
5
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
Figure 32. Output Impedance vs. Frequency
80
VS = ±1.35V
T
70
300mV
NUMBER OF AMPLIFIERS
VIN
0V 1
0V 2
VS = ±2.5V
VIN = 300mV
GAIN = –10
RECOVERY TIME = 240ns
40
30
20
10
05304-025
–2.5V
50
05304-028
VOUT
60
0
–150 –125 –100 –75 –50 –25 0 25
VOS (μV)
400ns/DIV
Figure 30. Negative Overload Recovery Time
50
75 100 125 150
Figure 33. Input Offset Voltage Distribution
60
T
VS = ±1.35V
0V 1
VIN
40
–300mV
VOS (μV)
VS = ±2.5V
VIN = 300mV
GAIN = –10
RECOVERY TIME = 240ns
2.5V
VOUT
20
0
–20
–40
–50
400ns/DIV
05304-029
05304-026
0V 2
0
50
TEMPERATURE (°C)
100
Figure 34. Input Offset Voltage vs. Temperature
Figure 31. Positive Overload Recovery Time
Rev. A | Page 10 of 20
150
AD8655/AD8656
80
10000
VS = ±1.35V
VS = ±1.35V
50
40
30
20
05304-030
10
0
0
0.2
0.4
0.6
0.8
1.0
1.2
|TCVOS| (μV/°C)
1.4
1000
100
VOL
10
05304-057
60
DELTA OUTPUT FROM SUPPLY (mV)
NUMBER OF AMPLIFIERS
70
VOH
1
0.1
1.6
Figure 35. |TCVOS| Distribution
1
10
CURRENT LOAD (mA)
100
Figure 38. AD8656 Output Swing vs. Current Load
4.5
2.698
VS = ±1.35V
2.694
2.690
3.5
VOH (V)
2.686
3.0
2.682
2.5
05304-031
2.678
2.0
–50
0
50
TEMPERATURE (°C)
100
2.674
–50
150
05304-032
SUPPLY CURRENT (mA)
4.0
VS = ±1.35V
LOAD CURRENT = 1mA
0
50
TEMPERATURE (°C)
100
150
Figure 39. Output Voltage Swing High vs. Temperature
Figure 36. Supply Current vs. Temperature
14
1400
VS = ±1.35V
LOAD CURRENT = 1mA
VS = ±1.35V
1200
12
10
VOH
VOL (mV)
800
600
6
VOL
400
8
4
05304-050
200
0
0
20
40
60
80
LOAD CURRENT (mA)
100
2
–50
120
05304-033
(VSY-VOUT) (mV)
1000
0
50
TEMPERATURE (°C)
100
Figure 40. Output Voltage Swing Low vs. Temperature
Figure 37. AD8655 Output Voltage to Supply Rail vs. Load Current
Rev. A | Page 11 of 20
150
AD8655/AD8656
35
T
VS = ±1.35V
G = +1
CL = 50pF
VIN
VS = ±1.35V
VIN = 200mV
30
–OS
OVERSHOOT %
25
1V/DIV
VOUT
2
20
15
+OS
10
05304-044
05304-047
5
0
0
20μs/DIV
100
150
200
250
CAPACITANCE (pF)
300
350
Figure 44. Small Signal Overshoot vs. Load Capacitance
Figure 41. No Phase Reversal
T
T
VS = ±1.35V
CL = 50pF
GAIN = +1
50
200mV
VIN
2
0V 2
VOUT
–1.35V
05304-042
VS = ±1.35V
VIN = 200mV
GAIN = –10
RECOVERY TIME = 180ns
400ns/DIV
TIME (10μs/DIV)
Figure 42. Large Signal Response
Figure 45. Negative Overload Recovery Time
T
T
VS = ±1.35V
CL = 100pF
GAIN = +1
0V 1
VIN
VS = ±1.35V
VIN = 200mV
GAIN = –10
RECOVERY TIME = 200ns
–200mV
2
1.35V
VOUT
05304-046
0V 2
05304-043
VOUT (100mV/DIV)
05304-045
VOUT (500mV/DIV)
0V 1
400ns/DIV
TIME (1μs/DIV)
Figure 43. Small Signal Response
Figure 46. Positive Overload Recovery Time
Rev. A | Page 12 of 20
AD8655/AD8656
120
120
VS = ±1.35V
VIN = 28mV
RL = 1MΩ
CL = 47pF
100
PHASE MARGIN = 54°
80
60
GAIN (dB)
CMRR (dB)
–90
80
PHASE SHIFT (Degrees)
100
–45
VS = ±1.35V
CLOAD = 11.5pF
60
40
–135
20
40
–180
0
20
0
100
1k
10k
FREQUENCY (Hz)
100k
–40
10k
1M
100k
1M
FREQUENCY (Hz)
05304-036
05304-034
–20
–225
100M
10M
Figure 50. Open-Loop Gain and Phase vs. Frequency
Figure 47. CMRR vs. Frequency
130.00
102.00
VS = ±1.35V
RL = 10kΩ
VS = ±1.35V
120.00
AVO (dB)
CMRR (dB)
98.00
94.00
110.00
100.00
90.00
86.00
–50
0
50
TEMPERATURE (°C)
100
80.00
–50
150
0
50
TEMPERATURE (°C)
100
150
Figure 51. Large Signal Open-Loop Gain vs. Temperature
Figure 48. Large Signal CMRR vs. Temperature
50
100
80
VS = ±1.35V
VIN = 50mV
RL = 1MΩ
CL = 47pF
VS = ±1.35V
RL = 1MΩ
CL = 47pF
40
CLOSED-LOOP GAIN (dB)
+PSRR
–PSRR
60
40
30
20
10
0
20
1k
10k
100k
1M
FREQUENCY (Hz)
10M
–20
1k
100M
Figure 49. Small Signal PSSR vs. Frequency
05304-038
0
100
–10
05304-040
PSRR (dB)
05304-037
05304-035
90.00
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 52. Closed-Loop Gain vs. Frequency
Rev. A | Page 13 of 20
100M
AD8655/AD8656
3.0
0
2.5
–20
CHANNEL SEPERATION (dB)
1.5
1.0
0.5
100k
1M
FREQUENCY (Hz)
G = +100
G = +10
G = +1
1
05304-041
OUTPUT IMPEDANCE (Ω)
100
10k
100k
1M
FREQUENCY (Hz)
10M
VOUT
B
V+
–2.5V
–80
–100
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 55. Channel Separation vs. Frequency
VS = ±1.35V
1k
V–
–60
10
1000
0.1
100
A
–140
10M
Figure 53. Maximum Output Swing vs. Frequency
10
+
–
–120
05304-039
0
10k
V–
V+
VIN
50mV p-p
–40
VS = ±2.5V
VIN = 50mV
R2
100Ω
05304-058
OUTPUT (V)
2.0
VS = 1.35V
VIN = 2.7V
G = +1
NO LOAD
R1
10kΩ
+2.5V
100M
Figure 54. Output Impedance vs. Frequency
Rev. A | Page 14 of 20
100M
AD8655/AD8656
THEORY OF OPERATION
The AD8655/AD8656 amplifiers are voltage feedback, rail-torail input and output precision CMOS amplifiers, which operate
from 2.7 V to 5.0 V of power supply voltage. These amplifiers
use the Analog Devices DigiTrim technology to achieve a
higher degree of precision than is available from most CMOS
amplifiers. DigiTrim technology, used in a number of ADI
amplifiers, is a method of trimming the offset voltage of the
amplifier after it is packaged. The advantage of post-package
trimming is that it corrects any offset voltages caused by the
mechanical stresses of assembly.
The AD8655/AD8656 can be used in any precision op amp
application. The amplifier does not exhibit phase reversal for
common-mode voltages within the power supply. The
AD8655/AD8656 are great choices for high resolution data
acquisition systems with voltage noise of 2.7 nV/√Hz and
THD + Noise of –103 dB for a 2 V p-p signal at 10 kHz. Their
low noise, sub-pA input bias current, precision offset, and high
speed make them superb preamps for fast filter applications.
The speed and output drive capability of the AD8655/AD8656
also make them useful in video applications.
The AD8655/AD8656 are available in standard op amp pinouts,
making DigiTrim completely transparent to the user. The input
stage of the amplifiers is a true rail-to-rail architecture, allowing
the input common-mode voltage range of the amplifiers to
extend to both positive and negative supply rails. The openloop gain of the AD8655/AD8656 with a load of 10 kΩ is
typically 110 dB.
Rev. A | Page 15 of 20
AD8655/AD8656
APPLICATIONS
INPUT OVERVOLTAGE PROTECTION
The internal protective circuitry of the AD8655/AD8656 allows
voltages exceeding the supply to be applied at the input. It is
recommended, however, not to apply voltages that exceed the
supplies by more than 0.3 V at either input of the amplifier. If a
higher input voltage is applied, series resistors should be used to
limit the current flowing into the inputs. The input current
should be limited to less than 5 mA.
One simple technique for compensation is a snubber that
consists of a simple RC network. With this circuit in place,
output swing is maintained, and the amplifier is stable at all
gains. Figure 57 shows the implementation of a snubber, which
reduces overshoot by more than 30% and eliminates ringing.
Using a snubber does not recover the loss of bandwidth
incurred from a heavy capacitive load.
VS = ±2.5V
AV = 1
CL = 500pF
VOLTAGE (100mV/DIV)
The extremely low input bias current allows the use of larger
resistors, which allows the user to apply higher voltages at the
inputs. The use of these resistors adds thermal noise, which
contributes to the overall output voltage noise of the amplifier.
For example, a 10 kΩ resistor has less than 12.6 nV/√Hz of
thermal noise and less than 10 nV of error voltage at room
temperature.
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground.
For circuits with resistive feedback network, the total capacitance,
whether it is the source capacitance, stray capacitance on the
input pin, or the input capacitance of the amplifier, causes a
breakpoint in the noise gain of the circuit. As a result, a
capacitor must be added in parallel with the gain resistor to
obtain stability. The noise gain is a function of frequency and
peaks at the higher frequencies, assuming the feedback capacitor is selected to make the second-order system critically
damped. A few picofarads of capacitance at the input reduce
the input impedance at high frequencies, which increases the
amplifier’s gain, causing peaking in the frequency response or
oscillations. With the AD8655/AD8656, additional input
damping is required for stability with capacitive loads greater
than 200 pF with direct input to output feedback. See the
Driving Capacitive Loads section.
05304-051
INPUT CAPACITANCE
TIME (2μs/DIV)
Figure 56. Driving Heavy Capacitive Loads Without Compensation
VCC
+
–
V–
V+
200Ω
–
200mV
VEE
500pF
05304-052
500pF
+
Figure 57. Snubber Network
Although the AD8655/AD8656 can drive capacitive loads up to
500 pF without oscillating, a large amount of ringing is present
when operating the part with input frequencies above 100 kHz.
This is especially true when the amplifiers are configured in
positive unity gain (worst case). When such large capacitive
loads are required, the use of external compensation is highly
recommended. This reduces the overshoot and minimizes
ringing, which, in turn, improves the stability of the
AD8655/AD8656 when driving large capacitive loads.
TIME (10μs/DIV)
05304-053
VOLTAGE (100mV/DIV)
DRIVING CAPACITIVE LOADS
VS = ±2.5V
AV = 1
RS = 200Ω
CS = 500pF
CL = 500pF
Figure 58. Driving Heavy Capacitive Loads Using a Snubber Network
Rev. A | Page 16 of 20
AD8655/AD8656
1.0
THD Readings vs. Common-Mode Voltage
0.5
Total harmonic distortion of the AD8655/AD8656 is well below
0.0007% with a load of 1 kΩ. This distortion is a function of the
circuit configuration, the voltage applied, and the layout, in
addition to other factors.
0.1
%
0.02
0.01
0.005
0.002
VOUT
AD8655
0.001
RL
05304-054
–2.5V
SWEEP 2
0.0005
SWEEP 1
0.0002
0.0001
Figure 59. THD + N Test Circuit
05304-055
–
VIN
SWEEP 2:
VIN = 2V p-p
RL = 1kΩ
0.05
+2.5V
+
SWEEP 1:
VIN = 2V p-p
RL = 10kΩ
0.2
20
50
100 200 500
1k
Hz
2k
5k
10k 20k 50k 80k
Figure 60. THD + Noise vs. Frequency
Rev. A | Page 17 of 20
AD8655/AD8656
LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS
POWER SUPPLY BYPASSING
LEAKAGE CURRENTS
Power supply pins can act as inputs for noise, so care must be
taken to apply a noise-free, stable dc voltage. The purpose of
bypass capacitors is to create low impedances from the supply
to ground at all frequencies, thereby shunting or filtering most
of the noise. Bypassing schemes are designed to minimize the
supply impedance at all frequencies with a parallel combination
of capacitors with values of 0.1 μF and 4.7 μF. Chip capacitors
of 0.1 μF (X7R or NPO) are critical and should be as close as
possible to the amplifier package. The 4.7 μF tantalum capacitor
is less critical for high frequency bypassing, and, in most cases,
only one is needed per board at the supply inputs.
Poor PC board layout, contaminants, and the board insulator
material can create leakage currents that are much larger than
the input bias current of the AD8655/AD8656. Any voltage
differential between the inputs and nearby traces creates leakage
currents through the PC board insulator, for example, 1 V/100
GΩ = 10 pA. Similarly, any contaminants on the board can
create significant leakage (skin oils are a common problem).
GROUNDING
A ground plane layer is important for densely packed PC
boards to minimize parasitic inductances. This minimizes
voltage drops with changes in current. However, an understanding of where the current flows in a circuit is critical to
implementing effective high speed circuit design. The length
of the current path is directly proportional to the magnitude
of parasitic inductances, and, therefore, the high frequency
impedance of the path. Large changes in currents in an
inductive ground return create unwanted voltage noise.
To significantly reduce leakage, put a guard ring (shield) around
the inputs and input leads that are driven to the same voltage
potential as the inputs. This ensures there is no voltage potential
between the inputs and the surrounding area to create any
leakage currents. To be effective, the guard ring must be driven
by a relatively low impedance source and should completely
surround the input leads on all sides, above and below, by using
a multilayer board.
The charge absorption of the insulator material itself can also
cause leakage currents. Minimizing the amount of material
between the input leads and the guard ring helps to reduce the
absorption. Also, using low absorption materials, such as
Teflon® or ceramic, may be necessary in some instances.
The length of the high frequency bypass capacitor leads is
critical, and, therefore, surface-mount capacitors are recommended. A parasitic inductance in the bypass ground trace
works against the low impedance created by the bypass
capacitor. Because load currents flow from the supplies, the
ground for the load impedance should be at the same physical
location as the bypass capacitor grounds. For larger value
capacitors intended to be effective at lower frequencies, the
current return path distance is less critical.
Rev. A | Page 18 of 20
AD8655/AD8656
OUTLINE DIMENSIONS
3.00
BSC
5.00 (0.1968)
4.80 (0.1890)
8
4.00 (0.1574)
3.80 (0.1497) 1
5
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
8
6.20 (0.2440)
3.00
BSC
4 5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
COPLANARITY
SEATING 0.31 (0.0122)
0.10
PLANE
0.50 (0.0196)
× 45°
0.25 (0.0099)
1
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 61. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
4.90
BSC
4
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
5
0.38
0.22
COPLANARITY
0.10
0.23
0.08
0.80
0.60
0.40
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 62. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8655ARZ 1
AD8655ARZ-REEL1
AD8655ARZ-REEL71
AD8655ARMZ-REEL1
AD8655ARMZ-R21
AD8656ARZ1
AD8656ARZ-REEL1
AD8656ARZ-REEL71
AD8656ARMZ-REEL1
AD8656ARMZ-R21
1
Temperature
Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
Z = Pb-free part.
Rev. A | Page 19 of 20
Package Option
R-8
R-8
R-8
RM-8
RM-8
R-8
R-8
R-8
RM-8
RM-8
Branding
A0D
A0D
A0S
A0S
AD8655/AD8656
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05304–0–6/05(A)
Rev. A | Page 20 of 20