Avalanche Photodiode Bias Controller and Wide Range (5 nA to 5 mA) Current Monitor ADL5317 FUNCTIONAL BLOCK DIAGRAM FEATURES Accurately sets avalanche photodiode (APD) bias voltage Wide bias range from 6 V to 75 V 3 V-compatible control interface Monitors photodiode current (5:1 ratio) over six decades Linearity 0.25% from 10 nA to 1 mA, 0.5% from 5 nA to 5 mA Overcurrent protection and overtemperature shutdown Miniature 16-lead chip scale package (LFCSP 3 mm × 3 mm) 16 15 14 13 COMM COMM COMM COMM ADL5317 FALT 1 OVERCURRENT PROTECTION CURRENT MIRROR 5:1 THERMAL PROTECTION NC 12 30 × VSET 2 Optical power monitoring and biasing in APD systems Wide dynamic range voltage sourcing and current monitoring in high voltage systems IPDM 29 × R 11 IAPD 5 3 VPLV 4 VPHV VPHV 5 R NC 10 IAPD VCLH GARD 6 GARD 9 VAPD 7 8 05456-001 APPLICATIONS VSET Figure 1. GENERAL DESCRIPTION The ADL5317 is a high voltage, wide dynamic range, biasing and current monitoring device optimized for use with avalanche photodiodes. When used with a stable high voltage supply (up to 80 V), the bias voltage at the VAPD pin can be varied from 6 V to 75 V using the 3 V-compatible VSET pin. The current sourced from the VAPD pin over a range of 5 nA to 5 mA is accurately mirrored with an attenuation of 5 and sourced from the IPDM monitor output. In a typical application, the monitor output drives a current input logarithmic amplifier to produce an output representing the optical power incident upon the photodiode. The photodiode anode can be connected to a high speed transimpedance amplifier for the extraction of the data stream. A signal of 0.2 V to 2.5 V with respect to ground applied at the VSET pin is amplified by a fixed gain of 30 to produce the 6 V to 75 V bias at Pin VAPD. The accuracy of the bias control interface of the ADL5317 allows for straightforward calibration, thereby maintaining a constant avalanche multiplication factor of the photodiode over temperature. The current monitor output, IPDM, maintains its high linearity vs. photodiode current over the full range of APD bias voltage. The current ratio of 5:1 remains constant as VSET and VPHV are varied. The ADL5317 also offers a supply tracking mode compatible with adjustable high voltage supplies. The VAPD pin accurately follows 2.0 V below the VPHV supply pin when VSET is tied to a voltage from 3.0 V to 5.5 V (or higher with a current limiting resistor), and the VCLH pin is open. Protection from excessive input current at VAPD as well as excessive die temperature is provided. The voltage at VAPD falls rapidly from its setpoint when the input current exceeds 18 mA nominally. A die temperature in excess of 140°C will cause the bias controller and monitor to shut down until the temperature falls below 120°C. Either overstress condition will trigger a logic low at the FALT pin, an open collector output loaded by an external pull-up to an appropriate logic supply (1 mA max). The ADL5317 is available in a 16-lead LFCSP package and is specified for operation from −40°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. ADL5317 TABLE OF CONTENTS Features .............................................................................................. 1 VCLH Interface .......................................................................... 10 Applications....................................................................................... 1 Noise Performance..................................................................... 10 Functional Block Diagram .............................................................. 1 Response Time............................................................................ 10 General Description ......................................................................... 1 Device Protection ....................................................................... 10 Specifications..................................................................................... 3 Applications..................................................................................... 11 Absolute Maximum Ratings............................................................ 4 Supply Tracking Mode............................................................... 11 ESD Caution.................................................................................. 4 Translinear Log Amp Interfacing............................................. 11 Pin Configuration and Function Descriptions............................. 5 Characterization Methods ........................................................ 12 Typical Performance Characteristics ............................................. 6 Evaluation Board ............................................................................ 14 Theory of Operation ........................................................................ 9 Outline Dimensions ....................................................................... 16 Bias Control Interface .................................................................. 9 Ordering Guide .......................................................................... 16 GARD Interface ............................................................................ 9 REVISION HISTORY 7/05—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADL5317 SPECIFICATIONS VPHV = 78 V, VPLV = 5 V, VAPD = 60 V, IAPD = 5 μA, TA = 25°C, unless otherwise noted. Table 1. Parameter CURRENT MONITOR OUTPUT Current Gain from VAPD to IPDM Min Typ Max Unit Conditions IPDM (Pin 11) 0.198 0.193 0.200 0.202 0.207 1.6 3.0 A/A TA = 25°C −40°C < TA < +85°C 10 nA < IAPD < 1 mA 5 nA < IAPD < 5 mA IAPD = 5 nA, VPHV = 60 V, VAPD = 30 V IAPD = 5 μA, VPHV = 60 V, VAPD = 30 V IAPD = 5 μA, CGRD = 2 nF, BW = 10 MHz, VPHV = 40 V, VAPD = 30 V VAPD > 3 × VPLV VAPD < 3 × VPLV VSET (Pin 2), VAPD (Pin 8) 10 V < VPHV < 41 V 41 V < VPHV < 76.5 V 76.5 V < VPHV < 80 V Nonlinearity 0.25 0.5 2 2 10 Small-Signal Bandwidth Wideband Noise at IPDM Output Voltage Range APD BIAS CONTROL Specified VAPD Voltage Operating Range VAPD to GARD Offset Specified Input Current Range, IAPD VSET to VAPD Incremental Gain VSET Input Referred Offset, 1σ VSET Voltage Range Incremental Input Resistance at VSET Input Bias Current at VSET VAPD Settling Time, 5% VAPD Supply Tracking Offset (Below VPHV) OVERSTRESS PROTECTION VAPD Current Compliance Limit Thermal Shutdown Trip Point Thermal Hysteresis FALT Output Low Voltage POWER SUPPLIES Low Voltage Supply Quiescent Current High Voltage Supply Quiescent Current 1 % % kHz MHz nA 0 0 VPLV VAPD / 3 V V 6 VPHV − 35 VPHV − 35 VPHV − 1.5 VPHV − 1.5 75 100 0.3 20 V V V mV A V/V mV V MΩ μA μsec 100 μsec 3 5n 29.7 30 0.5 0.2 5m 30.3 5.5 1.90 2.0 2.15 V 14 18 140 20 21 0.8 mA °C °C V 6 0.84 80 2.9 4.5 V mA V mA mA 4 0.7 10 2.3 3.6 Tested 1.5 V < VSET < 2.5 V, guaranteed operation 0.2 V < VSET < 2.5 V. Rev. 0 | Page 3 of 16 Flows from VAPD pin 0.2 V < VSET < 2.5 V 1 VSET = 2.0 V VSET = 2.0 V, flows from VSET pin VSET = 1.6 V to 2.4 V, CGRD = 2 nF, VPHV = 60 V, VAPD = 30 V VSET = 2.4 V to 1.6 V, CGRD = 2 nF, VPHV = 60 V, VAPD = 30 V VSET = 5.0 V, 10 V < VPHV < 77 V FALT (Pin 1) VSET = 2.0 V, VAPD deviation of 500 mV Die temperature rising Fault condition, load current < 1 mA VPHV (Pin 4, Pin 5), VPLV (Pin 3) VPLV Independent of IAPD VPHV IAPD = 5 μA, VAPD = 60 V IAPD = 1 mA, VAPD = 60 V ADL5317 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Input Current at VAPD Internal Power Dissipation θJA (Soldered Exposed Paddle) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec) Rating 80 V 25 mA 615 mW 65°C/W 125°C −40°C to +85°C −65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 4 of 16 ADL5317 12 NC 11 IPDM 10 NC 14 COMM NC = NO CONNECT 05456-002 9 GARD VAPD 8 GARD 7 TOP VIEW (Not to Scale) VPHV 5 VPHV 4 ADL5317 VCLH 6 VPLV 3 13 COMM PIN 1 INDICATOR FALT 1 VSET 2 15 COMM 16 COMM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 4, 5 6 7, 9 Mnemonic FALT VSET VPLV VPHV VCLH GARD 8 10, 12 11 13 to 16 VAPD NC IPDM COMM Description Open Collector (Active Low) Logic Output. Indicates an overcurrent or overtemperature condition. APD Bias Voltage Setting Input. Short to VPLV for supply tracking mode. Low Voltage Supply, 4 V to 6 V. High Voltage Supply, 10 V to 80 V. Can be shorted to VPHV for extended linear operating range. No connect for supply tracking mode. Guard pin tracks VAPD pin and filters setpoint buffer noise (with External Capacitor CGRD to COMM). Optional shielding of VAPD trace. Capacitive load only. APD Bias Voltage Output and Current Input. Sources current only. Optional shielding of IPDM trace. No connection to die. Photodiode Monitor Current Output. Sources current only. Current at this node is equal to IAPD/5. Analog Ground. Rev. 0 | Page 5 of 16 ADL5317 TYPICAL PERFORMANCE CHARACTERISTICS VPHV = 78 V, VPLV = 5 V, VAPD = 60 V, IAPD = 5 μA, TA = 25°C, unless otherwise noted. 1m 2.0 10m 1.5 1m 1.0 100μ IPDM (Amperes) 10μ 0.5 1μ 0 100n –0.5 10n IPDM (Amperes) –40°C +25°C IPDM LINEARITY (%) +85°C 100μ 2.0 VPHV = 78V, VAPD = 60V VPHV = 45V, VAPD = 32V VPHV = 10V, VAPD = 6V 1.5 1.0 VPHV = 78V, VAPD = 60V VPHV = 45V, VAPD = 32V 10μ 0.5 0 1μ 100n –0.5 VPHV = 10V, VAPD = 6V –1.0 10n –1.0 –1.5 1n –1.5 IPDM LINEARITY (%) 10m +85°C +25°C –40°C 10n 100n 1μ 10μ 100μ –2.0 10m 1m 100p 1n 05456-003 100p 1n IAPD (Amperes) 10n 100n 1μ 10μ 100μ 1m –2.0 10m 05456-004 1n IAPD (Amperes) Figure 6. IPDM Linearity for Multiple Values of VAPD and VPHV, Normalized to IAPD = 5 μA, VPHV =78 V, VAPD = 60 V Figure 3. IPDM Linearity for Multiple Temperatures, Normalized to IAPD = 5 μA, 25°C 31.0 80 VPHV = 45V, +85°C VPHV = 45V, +25°C VPHV = 45V, –40°C 30.8 70 VPHV = 78V, +85°C VPHV = 78V, +25°C VPHV = 78V, –40°C 30.6 60 VPHV = 78V, +85°C VPHV = 78V, –40°C 40 30 30.2 GAIN (V/V) VAPD (V) 30.4 VPHV = 78V, +25°C 50 30.0 29.8 VPHV = 45V, –40°C 29.6 20 VPHV = 45V, +85°C VPHV = 45V, +25°C 0 0.5 1.0 1.5 2.0 29.2 29.0 0 3.0 2.5 0.5 1.0 70 2.150 78/60 +25°C 45/32 +25°C 10/6 +25°C 2.125 60 2.100 –40°C 3.0 2.5 +25°C 78/60 –40°C 45/32 –40°C 10/6 –40°C 78/60 +85°C 45/32 +85°C 10/6 +85°C VPHV = 78V, VAPD = 60V; +85°C, +25°C, –40°C 0.030 0.020 50 0.010 40 0 2.050 2.025 VAPD (V) VPHV – VAPD (V) 2.0 Figure 7. Incremental Gain from VSET to VAPD vs. VSET for Multiple Temperatures, IAPD = 5 μA, VPHV = 78 V and 45 V Figure 4. VAPD vs. VSET for Multiple Temperatures, VPHV = 78 V and VPHV = 45 V, IAPD = 5 μA 2.075 1.5 VSET (V) VSET (V) 2.000 1.975 +85°C 30 –0.010 VPHV = 45V, VAPD = 32V; +85°C, +25°C, –40°C 1.950 1.925 20 –0.020 10 –0.030 VAPD VARIATION (V) 0 05456-007 05456-006 29.4 10 1.875 1.850 0 10 20 30 40 50 60 70 80 0 1n 90 VPHV (V) VPHV = 10V, VAPD = 6V; +85°C, +25°C, –40°C 10n 100n 1μ 10μ IAPD (Amperes) Figure 5. VAPD Supply Tracking Offset vs. VPHV for Multiple Temperatures 100μ 1m –0.040 10m 05456-008 05456-005 1.900 Figure 8. VAPD vs. IAPD for Multiple Temperatures and Values of VPHV and VAPD Rev. 0 | Page 6 of 16 ADL5317 3 3 +85°C +25°C –40°C +85°C +25°C –40°C 2 IPDM LINEARITY (%) 1 0 –1 –3 1n 0 –1 –2 05456-010 –2 1 10n 100n 1μ 10μ 100μ –3 1n 10m 1m 05456-011 IPDM LINEARITY (%) 2 10n 100n 1μ IAPD (Amperes) Figure 9. IPDM Linearity for Multiple Temperatures and Devices VPHV =75 V, VAPD = 60 V, Normalized to IAPD = 5 μA, 25°C 10m 4.0 500μA 3.5 50μA 3.0 5μA 1pA 500nA (%) 2.0 50nA 100fA 2.5 1.5 0.5 05456-035 1fA 1k 1.0 5nA 10fA 10k 100k 1M 05456-036 (AMPERES rms/√Hz) 1m 4.5 5mA 0 1n 10M 10n 100n Figure 10. Output Current Noise Density vs. Frequency for Multiple Values of IAPD, CGARD = 2 nF, VPHV = 40 V, VAPD = 30 V 10μ 100μ 1m Figure 13. Output Wideband Current Noise as a Percentage of IPDM vs. IPDM, CGARD = 2 nF, VPHV = 40 V, VAPD = 30 V, BW = 10 MHz 30 10 +3 SIGMA 0 –10 –3 SIGMA –40 –40 –30 –20 –10 05456-042 –30 0 10 20 30 40 50 60 70 80 0 5μA –5 5nA –15 –20 50nA –25 –30 10 90 TEMPERATURE (°C) 500nA –10 05456-043 NORMALIZED RESPONSE (dB) AVERAGE –20 50μA 5 20 10 1μ IPDM (Amperes) FREQUENCY (Hz) VAPD DRIFT (mV) 100μ Figure 12. IPDM Linearity for Multiple Temperatures and Devices VPHV = 45 V, VAPD = 32 V, Normalized to IAPD = 5 μA, 25°C 100pA 10pA 10μ IAPD (Amperes) 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 11. Temperature Drift of VAPD, 3 σ to Either Side of Mean Figure 14. Small Signal AC Response from IAPD to IPDM, for IAPD in Decades from 5 nA to 50 μA, VPHV = 60 V, VAPD = 30 V Rev. 0 | Page 7 of 16 ADL5317 75 10m 1m 70 100μA TO 1mA: T-RISE = <0.5μs, T-FALL = <0.5μs 10μA TO 100μA: T-RISE = <0.5μs, T-FALL = <0.5μs 1μA TO 10μA: T-RISE = <0.5μs, T-FALL = <0.5μs 1μ 100nA TO 1μA: T-RISE = <1μs, T-FALL = <1.5μs 100n 10nA TO 100nA: T-RISE = <10μs, T-FALL = <15μs 65 60 5mA 55 500μA 10n 50μA 1nA TO 10nA: T-RISE = <100μs, T-FALL = <150μs 05456-016 1n 10n 0 50 100 150 200 250 500nA 50nA 5nA 50 300 350 05456-017 10μ VAPD, VOLTAGE (V) IPDM (Amperes) 100μ 5μA 45 400 0 TIME (μs) 50 100 150 200 250 300 350 400 TIME (μs) Figure 15. Pulse Response from IAPD to IPDM for IAPD in Decades from 5 nA to 5 mA, VPHV = 60 V, VAPD = 30 V Figure 17. Pulse Response from VSET to VAPD (VSET Pulsed 1.6 V to 2.4 V) for IAPD in Decades from 5 nA to 5 mA, CGARD = 2 nF, VPHV = 60 V, VAPD = 30 V N = 2029 MEAN = 0.200035 SD = 0.000454209 N = 2021 MEAN = 29.959 SD = 0.0316714 30 20 25 15 (%) (%) 20 15 10 10 05456-038 0 29.7 05456-039 5 5 29.8 29.9 30.0 30.1 30.2 0 0.1980 0.1985 0.1990 0.1995 0.2000 0.2005 0.2010 0.2015 0.2020 30.3 IPDM/IAPD (A/A) SLOPE (V/V) Figure 16. Distribution of Incremental Gain from VSET to VAPD for VSET from 1.5 V to 2.4 V, IAPD = 5 μA Figure 18. Distribution of IPDM/IAPD at VPHV = 60 V, VSET = 1.0 V, IAPD = 50 μA Rev. 0 | Page 8 of 16 ADL5317 THEORY OF OPERATION The ADL5317 is designed to address the need for high voltage bias control and precision optical power monitoring in optical systems using avalanche photodiodes. It is optimized for use with the Analog Devices, Inc. family of translinear logarithmic amplifiers that take advantage of the wide input current range of the ADL5317. This arrangement allows the anode of the photodiode to connect directly to a transimpedance amplifier for the extraction of the data stream without need for a separate optical power monitoring tap. Figure 19 shows the basic connections for the ADL5317. 3 0Ω 4 0.1μF 0.01μF COMM COMM COMM IPDM ADL5317 VPLV NC VPHV GARD 5 6 7 8 12 11 MIRROR CURRENT OUTPUT 10 9 0.01μF 0.01μF 0Ω 0.1μF APD 1kΩ ADL5317 1nF HIGH VOLTAGE SUPPLY 05456-021 IAPD GARD X30 20kΩ Figure 19. Basic Connections CGRD VSET AMPLIFIER At the heart of the ADL5317 is a precision attenuating current mirror with a voltage following characteristic that provides precision biasing at the monitor input. This architecture uses a JFET-input amplifier to drive the bipolar mirror and maintain stable VAPD voltage, while offering very low leakage current at the VAPD pin. The mirror attenuates the current sourced through VAPD by a factor of 5 to limit power dissipation under high voltage operation and delivers the mirrored current to the IPDM monitor output pin. Proprietary mirroring and cascoding techniques maintain the linearity vs. the input current and stability of the mirror ratio over a very wide range of supply and VAPD voltages. BIAS CONTROL INTERFACE In the linear operating mode, the voltage at VAPD is referenced to ground, and follows the simplified equation VAPD = 30 × VSET GARD is driven to the same potential as VAPD for use in shielding the highly sensitive VAPD pin from leakage currents. The GARD and VAPD pins are clamped to within approximately 40 V below the VPHV supply to prevent internal device breakdowns, and VAPD is clamped to within a volt of GARD. VAPD RCOMP CCOMP 05456-022 LOW VOLTAGE SUPPLY VSET NC GARD INTERFACE The GARD pins primarily shield the VAPD trace from leakage currents and filter noise from the bias control interface. GARD is driven by the VSET amplifier through a 20 kΩ resistor. This resistor forms an RC network with an external capacitor from GARD to ground that filters the thermal noise of the amplifier’s feedback network and provides additional power supply rejection. The series components, RCOMP and CCOMP, shown in Figure 20, are necessary to ensure essential high frequency compensation at the VAPD input pin over the full operating range of the ADL5317. 13 VAPD VSET FALT 14 GARD 2 VCLH 10kΩ 15 VPHV 1 FALT COMM 16 The VAPD adjustment range for a given high voltage supply, VPHV, is limited to approximately 33 V (or less, for VPHV < 41 V). For example, VAPD is specified from 40 V to 73.5 V for a 75 V supply, and 6 V (the minimum allowed) to 28.5 V for a 30 V supply. When VAPD is driven to its lower clamp voltage via the VSET pin, the mirror can continue to operate, but the VAPD bias voltage no longer responds to incremental changes in VSET. Figure 20. Filtering VAPD Using the GARD Interface The cutoff frequency of the GARD interface for small signals and noise is defined by F3dB = 1 2π × 20 kΩ × CGRD where: F3dB is the cutoff frequency of the low-pass filter formed by the on-board 20 kΩ and CGRD. CGRD is the filter capacitor installed from GARD to ground. A larger value for CGRD (up to approximately 0.01 μF) provides superior noise performance at the lowest input current levels, but also slows the response time to changes in VSET. The pull-up of the VSET amplifier is limited to approximately 2.5 mA, resulting in a slew limited region for large signals, followed by an RC decay for the final 700 mV. This decay corresponds to the above single-pole equation. The pull-down of the VSET amplifier is largely resistive, equivalent to approximately 90 kΩ in parallel with 70 μA to ground. Rev. 0 | Page 9 of 16 ADL5317 For small input currents, this pull-down must discharge not only CGRD but also CCOMP at the VAPD pin (through the GARD and VAPD diodes). The final 700 mV of settling for lower input currents is dominated by the input current discharge of CCOMP. For larger input currents, the VSET amplifier pull-down discharges only CGRD, since IAPD is capable of discharging CCOMP quickly (see Figure 17). Any dc load on GARD alters the gain from VSET to VAPD due to the 20 kΩ source impedance. Note that the load presented by a multimeter or oscilloscope probe is sufficient to alter the VSET to VAPD gain, and must be taken into account. The GARD pin is internally clamped to approximately 40 V below VPHV to prevent device breakdown, and VAPD is clamped to within 1 V of GARD. For this reason, any shortcircuit to ground from GARD or VAPD must be avoided for VPHV voltages above 36 V, or device damage results. components on VAPD, minimizes the amount of voltage noise at VAPD that is converted to current noise at IPDM. RESPONSE TIME The response time for changes in signal current is fundamentally a function of signal current, with small-signal bandwidth increasing roughly in proportion to signal current. The value of the external compensating capacitor on VAPD strongly affects response time, although the value must be chosen to maintain stability and prevent noise peaking. Response time for changes in VSET voltage is primarily a function of the filter capacitance at the GARD pin. See the GARD Interface section for further details. Figure 15 and Figure 17 show the response of the ADL5317 to pulsed input current and VSET voltage, respectively. DEVICE PROTECTION VCLH INTERFACE The voltage clamp high-side pin (VCLH) is typically connected to VPHV for linear operation of the VSET interface and left open for supply tracking mode (see the Supply Tracking Mode section for more details). The voltage at VCLH represents a high-side clamp above which the VSET amplifier output (and VAPD) is not allowed to rise. The voltage is internally set to a temperature stable 2.0 V below VPHV through a 25 kΩ resistor. When VSET is pulled up to 3 V or higher and VCLH is open, VAPD follows 2.0 V below VPHV as VPHV is varied. This bypasses the linear VSET interface for applications where an adjustable high voltage supply is preferred (see the Applications section). The 25 kΩ source resistance allows VCLH to be shorted to VPHV, removing the 2.0 V high-side clamp for extended linear operating range (up to VPHV − 1.5 V) in linear mode. VCLH can be left open in linear mode if a fixed clamp point is desired. NOISE PERFORMANCE The noise performance for the ADL5317, defined as the rms noise current as a fraction of the output dc current, improves with increasing signal current. This partially results from the relationship between quiescent collector current and shot noise in bipolar transistors. At lower signal current levels, the noise contribution from the VSET amplifier and other noise sources appearing at VAPD dominate the noise behavior. Filtering the VSET interface noise through an external capacitor from GARD to ground, as well as selecting optimal external compensation Thermal and overcurrent protection are provided with fault detection. The FALT pin is an open collector logic output (active low) designed to assert when an overtemperature or overcurrent condition is detected. A pull-up resistor to an appropriate logic supply is required, and its value should be chosen such that no more than 1 mA output current is used when active. When the die temperature of the ADL5317 exceeds 140°C (typical), the current mirror shuts down, causing the bias voltage at VAPD to be pulled down, and FALT asserts. FALT remains asserted until the temperature falls below the trigger temperature minus the thermal hysteresis (20°C typical), after which the mirror and biaser again power up. The cycle may repeat until the cause of the fault is removed. When the input current, IAPD, exceeds 18 mA (typical), the current mirror and biaser attempt to maintain the threshold current by allowing the VAPD voltage to fall to a point of equilibrium. In other words, the threshold current represents the compliance of the bias voltage; in this case, the current at which VAPD falls 500 mV below its midrange current value. FALT asserts, but is not guaranteed to remain asserted, as VAPD is pulled down toward ground. If VAPD falls below ~3 V, as in the case of a momentary short-circuit or being driven by a programmable current source exceeding the threshold current, bias current generators critical to device operation become saturated. This causes FALT to deassert and the mirror to shut down. The mirror does not power up until the input current falls below the current limit of the VSET amplifier (approximately 2.5 mA), allowing VAPD to be pulled up to its normal operating level. The FALT pin can be grounded if the logic signal is not used. Rev. 0 | Page 10 of 16 ADL5317 APPLICATIONS The ADL5317 is primarily designed for wide dynamic range applications simplifying APD bias circuit architecture. Accurate control of the bias voltage across the APD becomes critical to maintain the proper avalanche multiplication factor as the temperature and input power vary. Figure 21 shows how to use the ADL5317 with an external temperature sensor to monitor the ambient temperature of the APD. Using a look-up table and DAC to drive VSET, it is possible to apply the correct VAPD for the conditions. Note that Pin 9, Pin 10, and Pin 12 to Pin 15 were removed for simplification. SUPPLY TRACKING MODE Some applications for the ADL5317 require a variable dc-to-dc converter or alternative variable biasing sources to supply VPHV. For these applications, it is necessary to configure the ADL5317 for supply tracking mode, shown in Figure 22. In this mode, the VSET interface is bypassed. However, the full functionality of the precision current mirror remains available. 5V 16 1 LOGIC SUPPLY COMM OVERCURRENT PROTECTION THERMAL PROTECTION 14 30 × VSET 29 × R TRANSLINEAR LOG AMP TEMPERATURE SENSOR IPDM 3 GARD VPLV 4 5 10V TO 77V CGRD VARIABLE DC SUPPLY GARD 9 DATA VCLH 6 GARD 7 VAPD 8 8V TO 75V BIAS ACROSS APD TIA 05456-023 TIA RECEIVER RSSI NC 10 VPHV VPHV VAPD APD R 4V TO 6V IAPD VCLH LOG 11 OPTICAL POWER IAPD 5 R VPLV 75V FROM DC–DC CONVERTER 30 × VSET 3V TO 5.5V IPDM VPHV VSET NC 12 DATA OUT 05456-024 VSET 2 13 CURRENT MIRROR 5:1 THERMAL PROTECTION CURRENT MIRROR 5:1 29 × R 5V 15 COMM COMM COMM COMM OVERCURRENT PROTECTION FALT LOOK-UP TABLE AND DAC FALT Figure 22. Supply Tracking Mode Figure 21. Typical APD Biasing Application Using the ADL5317 In this application, the ADL5317 is operating in linear mode. The bias voltage to the APD, delivered at Pin VAPD, is controlled by the voltage (VSET) at Pin VSET. The bias voltage at VAPD is equal to 30 × VSET. The range of voltages available at VAPD for a given high voltage supply is limited to approximately 33 V (or less, for VAPD < 41 V). This is because the GARD and VAPD pins are clamped to within ~40 V below VPHV, preventing internal device breakdowns. The input current, IAPD, is divided down by a factor of 5 and precisely mirrored to Pin IPDM. This interface is optimized for use with any of the Analog Devices translinear logarithmic amplifiers (for example, the AD8304 or AD8305) to offer a precise, wide dynamic range measurement of the optical power incident upon the APD. If a voltage output is preferred at IPDM, a single external resistor to ground is all that is necessary to perform the conversion. Voltage compliance at IPDM is limited to VPLV or VAPD/3, whichever is lower. In supply tracking mode, the VSET amplifier is pulled up beyond its linear operating range and effectively placed into a controlled saturation. This is done by applying 3.0 V to 5.5 V at the VSET pin. It is also necessary to remove the connection from VCLH, which defines the saturation point, to VPHV. Once the ADL5317 is placed into supply tracking mode, VAPD is clamped to 2.0 V below VPHV. For those designs where it is desirable to drive VSET from the VPLV supply, it is necessary to place a 100 kΩ resistor between VSET and VPLV for VPLV > 5.5 V. This is due to input current limitations on the VSET pin. TRANSLINEAR LOG AMP INTERFACING The monitor current output, IPDM, of the ADL5317 is designed to interface directly to an Analog Devices translinear logarithmic amplifier, such as the AD8304, AD8305, or ADL5306. Figure 23 shows the basic connections necessary for interfacing the ADL5317 to the AD8305. In this configuration, the designer is can use the full current mirror range of the ADL5317 for high accuracy power monitoring. Rev. 0 | Page 11 of 16 ADL5317 AD8305 INPUT COMPENSATION NETWORK COMM 3 12 4.7nF 2kΩ 11 GARD 6 7 8 4 COMM COMM COMM IREF BFIN INPT VLOG IPDM 10nA TO 1mA 9 5 6 7 8 0.1μF 0.01μF SCAL AD8305 VPOS COMM NC VPHV 5 VREF VOUT VNEG 0.01μF NC VPLV VAPD 0.1μF 4 GARD 0Ω VRDZ 200kΩ 10 VCLH VP_LOW 2 1kΩ IPDM ADL5317 1 2.5V 13 VNEG VSET 3 1nF 13 14 15 VSUM 2 VSET 14 VPHV 10kΩ FALT 15 COMM 1 COMM 16 COMM 16 12 11 OUTPUT VOUT = 0.2 × LOG10 (IPDM/1nA) 10 9 3V TO 12V 0.01μF IAPD 0Ω 1kΩ APD 1nF 0.1μF TIA 05456-025 VP_HIGH DATA PATH Figure 23. Interfacing the ADL5317 to the AD8305 for High Accuracy APD Power Monitoring Measured rms noise voltage at the output of the AD8305 vs. input current is shown in Figure 24 for the AD8305 by itself and in cascade with the ADL5317. The relatively low noise produced by the ADL5317, combined with the additional noise filtering inherent in the frequency response characteristics of the AD8305, result in minimal degradation to the noise performance of the AD8305. 5.5m 5.0m 4.5m 4.0m AD8305 AND ADL5317 (V rms) 3.5m 3.0m 2.5m To minimize leakage on the characterization board, the guard pins are connected to traces that buffer VAPD and IPDM from ground. The triax guard connector is also connected to the GARD pin of the device to provide buffering along the cabling. Figure 25 shows the primary characterization setup. The data gathered is used directly, or with calculation, for all the static measurements, including mirror error between IAPD and IPDM , supply tracking offset, incremental gain, and VAPD vs. IAPD. Component selection is very similar to that of the evaluation board, except that triax connectors are used in place of the SMA connectors. To measure the pulse response, output noise, and bandwidth measurements, more specialized test setups are used. 2.0m AD8305 ONLY ADL5317 1.5m 05456-034 0.5m KEITHLEY 236 100n 1μ 10μ 100μ IPDM KEITHLEY 236 1m FALT (A) VPHV VPLV VSET VCLH TRIAX CONNECTORS: SIGNAL - VAPD AND IPDM PINS GUARD - GUARD PIN SHIELD - GROUND Figure 24. Measured RMS Noise of AD8305 vs. AD8305 Cascaded with ADL5317 DC SUPPLIES/DMM CHARACTERIZATION METHODS During characterization, the ADL5317 was treated as a high voltage 5:1 precision current mirror. To make accurate measurements throughout the entire current range, calibrated Keithley 236 current sources were used to create and measure the test currents. Measurements at low current and high voltage are very susceptible to leakage to the ground plane. Rev. 0 | Page 12 of 16 Figure 25. Primary Characterization Setup 05456-026 0 10n VAPD CHARACTERIZATION BOARD 1.0m ADL5317 ALKALINE D CELL + – 604Ω 1kΩ 83nF HP89410A ADL5317 TDS5104 VECTOR SIGNAL ANALYZER EVALUATION BOARD VAPD VPHV VPLV VSET VAPD ALKALINE + D CELLS – + – + – + – IPDM +9V– RL GE 273 Q1 +12V FALT VPHV VPLV IPDM FET BUFFER 20kΩ –12V DC SUPPLIES/DMM 05456-041 33μF Figure 26. Configuration for Noise Spectral Density and Wideband Current Noise Figure 28. Configuration for Pulse Response from VSET to VAPD NETWORK ANALYZER OUTPUT EVALUATION BOARD R A 60V VPHV B IPDM AD8067 + 05456-027 RC DC SUPPLIES/DMM ADL5317 POWER SPLITTER TDS5104 FALT VPHV VPLV VSET VCLH – VSET EVAL BOARD + RF IPDM EVAL BOARD COMM AD8138 RF VPLV VAPD RC VAPD 5V AD8045 1V – 50Ω Figure 27. Configuration for Pulse Response from IAPD to IPDM 05456-040 1pF ADL5317 AGILENT 33250A VCLH RC LNA – +9V + R1 Q1 AGILENT 33250A VSET + ADL5317 05456-037 ALKALINE + D CELLS – + – DP 8200 + DC POWER SUPPLY – Figure 29. Configuration for Small Signal AC Response The setup in Figure 26 is used to measure the output current noise of the ADL5317. Batteries are used in numerous places to minimize introduced noise and remove the uncertainty resulting from the use of multiple dc supplies. In application, properly bypassed dc supplies provide similar results. The load resistor is chosen for each current to maximize signal-to-noise ratio while maintaining measurement system bandwidth (when combined with the low capacitance JFET buffer). The custom LNA is used to overcome noise floor limitations in the HP89410A signal analyzer. Figure 27 shows the configuration used to measure the IAPD pulse response. To create the test current pulse, Q1 is used in a common base configuration with the Agilent 33250A, generating a negative biased square wave with an amplitude that results in a one decade current step on IPDM. RC is chosen according to what current range is desired. Only one cable is used between the Agilent 33250A and RC, while everything else is connected with SMA connectors. A FET scope probe connects the output of the AD8067 to the TDS5104 input. The configuration in Figure 28 is used to measure VAPD while VSET is pulsed. Q1 and RC are used to generate the operating current on the VAPD pin. An Agilent 33250A pulse generator is used on the VSET pin to create a 1.6 V to 2.4 V square wave. The capacitance on the GARD pin is 2 nF for this test. The setup in Figure 29 is used to measure the frequency response from IAPD to IPDM. The AD8138 differential op amp delivers a −1.250 V dc offset to bias the NPN transistor and to have a 500 mV drop across RF. This voltage is modulated to a depth of 5% of full scale over frequency. The voltage across RF sets the dc operating point of IAPD. RF values are chosen to result in decade changes in IAPD. The output current at the IPDM pin is fed into an AD8045 op amp configured to operate as a transimpedance amplifier. The Feedback Resistor, RF, is the same value as that on the output of the AD8138. Note that any noise at the VSET input is amplified by the ADL5317 with a gain of 30. This noise shows up on VAPD and causes errors when measuring nanoamp current levels. This noise can be filtered by use of the GARD pin. See the GARD Interface section for more details. Rev. 0 | Page 13 of 16 ADL5317 EVALUATION BOARD Table 4. Evaluation Board Configuration Options Component VPHV, VPLV, GND Function High and Low Voltage Supply and Ground Pins. Default Condition Not Applicable VSET APD Bias Voltage Setting Pin. The dc voltage applied to VSET determines the APD bias voltage at VAPD. VAPD = 30 × VSET. Not Applicable R11, C8 APD Input Compensation. Provides essential high frequency compensation at the VAPD input pin. C8 = 1 nF (size 0603) R11 = 1 kΩ (size 0603) VAPD, L1, C9 Input Interface. The evaluation board is configured to accept an input current at the SMA connector labeled VAPD. Filtering of this current can be done using L1 and C9. L1 = 0 Ω (size 0805) C9 = open (size 0805) IPDM, R1 Mirror Interface. The output current at the SMA connector labeled IPDM is 1/5 the value at VAPD. R1 allows a resistor to be installed for applications where a scaled voltage referenced to IAPD instead of a current is desirable. R1 = open (size 1206) R7, R8, R9, R10, C6, C7, C10 Guard Options. By populating R9 and/or R10, the shell of the VAPD SMA connector is set to the GARD potential. R7 and R8 are installed so that the guard potential can be driven by an external source, such as the VSUM potential of the Analog Devices optical log amps. C7 filters noise from the VSET interface and provides a high frequency ac path to ground. Additional filtering is possible by installing a capacitor at C10. C10 should equal C7. R7 = R8 = 0 Ω (size 0402) R9 = R10 = open (size 0402) C7 = 0.01 μF (size 0805) C6 = C10 = open (size 0402) VPLV, W1, W2, R3 Optional Supply Tracking Mode. Connecting Jumper W2 and opening Jumper W1 places the ADL5317 into supply tracking mode. In this mode, the voltage at VAPD is typically 2 V below VPHV. R3 = 100 kΩ for VPLV > 5.5 V. R3 = 0 Ω (size 0402) W1 = open W2 = closed VCLH, W1, C4, R6 Extended Linear Operating Range. Closing W1 connects Pin VPHV and Pin VCLH. This allows for an extended linear control range of VAPD using VSET. W1 = closed C4 = open (size 0805) R6 = 0 Ω (size 0402) FALT, R2 FALT Interface. R2 is a resistive pull-up that is used to create the logic signal at FALT. R2 = 10 kΩ (size 0603) C1, C2, C3, C5, R4, R5 Supply Filtering/Decoupling. C1 = C2 = 0.01 μF (size 0402) C3 = 0.1 μF (size 0603) C5 = 0.1 μF (size 1206) R4 = R5 = 0 Ω (size 0402) Rev. 0 | Page 14 of 16 ADL5317 NC VPHV GARD C2 0.01μF C1 0.01μF GND R5 0Ω C5 0.1μF COMM VPLV VAPD 0Ω 4 GARD C3 0.1μF W2 NC IPDM ADL5317 VCLH R4 VPLV 3 VSET VPHV R2 10kΩ R3 0Ω 13 5 6 7 8 W1 R6 0Ω C4 OPEN C10 OPEN 12 R8 0Ω 11 10 9 R1 OPEN IPDM OUTPUT R7 C6 0Ω OPEN R11 1kΩ L1 0Ω C8 1nF C7 0.01μF C9 OPEN R9 OPEN VPHV R10 OPEN 05456-030 2 VSET 14 COMM FALT COMM 1 FALT 15 COMM 16 VAPD 05456-031 05456-032 Figure 30. ADL5317 Evaluation Board Schematic Figure 32. ADL5317 Evaluation Board Silkscreen Figure 31. ADL5317 Evaluation Board Layout Rev. 0 | Page 15 of 16 ADL5317 Preliminary Technical Data OUTLINE DIMENSIONS 3.00 BSC SQ 0.60 MAX 13 12 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.80 MAX 0.65 TYP 12° MAX SEATING PLANE 16 PIN 1 INDICATOR *1.65 1 1.50 SQ 1.35 EXPOSED PAD 0.50 BSC 0.90 0.85 0.80 0.50 0.40 0.30 9 (BOTTOM VIEW) 4 8 5 0.25 MIN 1.50 REF 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 33. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm x 3 mm Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters ORDERING GUIDE Model ADL5317ACPZ-REEL7 1 ADL5317ACPZ-WP1 ADL5317-EVAL 1 Temperature Range –40°C to +85°C –40°C to +85°C Package Description 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board Z = Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05456-0-7/05(0) Rev. 0 | Page 16 of 16 Package Option CP-16-3 CP-16-3 Branding R00 R00 R00