Mobile I/O Expander and QWERTY Keypad Controller ADP5587 FEATURES FUNCTIONAL BLOCK DIAGRAM ADP5587 GND 19 VCC C9 21 18 SCL 23 CONTROL INTERFACE CONTROL REGISTERS SDA 22 C8 17 RST 20 16 08612-001 15 C7 14 C6 13 C5 12 C4 11 C3 10 C2 9 C1 8 C0 7 R0 6 R1 5 R3 4 R4 3 R5 2 R6 1 R2 INT 24 R7 18-GPIO port expander or 10 × 8 keypad matrix GPIOs configurable as GPIs, GPOs, and keypad rows or columns I2C interface with auto-increment 1.7 V to 3.6 V operation Keypad lock capability Open-drain interrupt output Key press and key release interrupts GPI interrupt with level programmability Programmable pull-ups Key event counter with overflow interrupt 275 μs debounce on the reset line and GPIs 1 μA typical idle current 55 μA typical polling current Small 4 mm × 4 mm LFCSP package Figure 1. APPLICATIONS Keypad and I/O expander designed for QWERTY type phones that require a large keypad matrix GENERAL DESCRIPTION The ADP5587 is an I/O port expander and keypad matrix designed for QWERTY type phones that require a large keypad matrix and expanded I/O lines. I/O expander ICs are used in mobile platforms as a solution to the limited number of GPIOs available in the main processor. In its small 4 mm × 4 mm package, the ADP5587 contains enough power to handle all key-scanning and decoding and to flag the processor of key presses and releases via the I2C interface and interrupt. The ADP5587 frees the main microprocessor from the need to monitor the keypad, thereby minimizing current drain and increasing processor bandwidth. The ADP5587 is also equipped with a buffer/FIFO and key event counter to handle and keep track of up to 10 unprocessed key or GPI events with overflow wrap and interrupt capability. The ADP5587 has keypad lock capability with an option to trigger or not trigger an interrupt at key presses and releases. All communication to the main processor is done using one interrupt line and two I2C-compatible interface lines. The ADP5587 can be configured as a keypad matrix of up to 8 rows × 10 columns (a maximum of 80 keys). When the ADP5587 is used for smaller keypad matrices, unused row and column pins can be reconfigured to act as generalpurpose inputs or outputs. R0 to R7 denote the row pins of the matrix, whereas C0 to C9 denote the column pins. At power-up, all rows and columns default to GPIs and must be programmed to function as part of the keypad matrix or as GPOs. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADP5587 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation .........................................................................7 Applications ....................................................................................... 1 Keypad Operation .........................................................................7 Functional Block Diagram .............................................................. 1 General-Purpose Inputs and Outputs ..................................... 11 General Description ......................................................................... 1 I C Programming and Digital Control ........................................ 13 Revision History ............................................................................... 2 Registers....................................................................................... 14 Specifications..................................................................................... 3 Register Descriptions ................................................................. 15 DC Characteristics ....................................................................... 3 Applications Information .............................................................. 20 AC Characteristics ........................................................................ 4 Applications Overview .............................................................. 20 Absolute Maximum Ratings ............................................................ 5 Keypad Current .......................................................................... 20 Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 22 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 22 2 Pin Configuration and Function Descriptions ............................. 6 REVISION HISTORY 12/09—Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADP5587 SPECIFICATIONS TA = TJ = −40°C to +85°C, unless otherwise noted. DC CHARACTERISTICS Table 1. General DC Electrical Characteristics Parameter SUPPLY VOLTAGE VCC Input Voltage Range Supply Current 1 With One Key Press With GPI Low (Pull-Up Enabled)2 With GPI Low (Pull-Up Disabled) With One GPO Active3 OSCILLATOR CURRENT Oscillator Current (Enabled) 1 2 3 Symbol Conditions VCC ICC ICC ICC ICC ICC ICC ICC Min Typ Max Unit VCC = 1.8 V to 3.0 V, TA = −40°C to +85°C VCC = 1.8 V, TA = −40°C to +85°C VCC = 3.0 V, TA = −40°C to +85°C VCC = 1.8 V to 3.0 V, TA = −40°C to +85°C VCC = 1.8 V to 3.0 V, TA = −40°C to +85°C VCC = 1.8 V, TA = −40°C to +85°C 1 55 100 20 2 3.6 10 90 200 50 10 50 V μA μA μA μA μA μA VCC = 1.8 V to 3.0 V 40 1.7 μA Operating current measured with I/Os defaulting as GPIs, with all pull-ups enabled and all inputs open. With one GPI low. Load = 100 kΩ. Table 2. I/O DC Electrical Characteristics Parameter INPUT LOGIC LEVELS (SCL, SDA, RST, C0 to C9, R0 to R7)1 Logic Low Input Voltage Logic High Input Voltage Schmitt Trigger Hysteresis Input Leakage Current OUTPUT LOGIC LEVELS (C0 to C9, R0 to R7) Logic Low Output Voltage Output High Voltage OUTPUT LOGIC LEVELS (INT, SDA) Output Low Voltage Symbol Conditions Min VIL VIH VHYST VI-LEAKAGE 1.8 V ≤ VIO ≤ 3.0 V 1.8 V ≤ VIO ≤ 3.0 V 0.7 × VCC 1.8 V ≤ VIO ≤ 3.0 V −1 VOL VOH ISINK = 1 mA ISOURCE = 1 mA VOL Output High Voltage Logic High Leakage Current PULL-UP RESISTANCE FOR GPIOs (C0 to C9, R0 to R7)2 VOH VO-LEAKAGE RPULL-UP ISINK = 3 mA, 1.8 V ≤ VCC ≤ 3.0 V 1.8 V ≤ VCC ≤ 3.0 V 1.8 V ≤ VCC ≤ 3.0 V 1 2 Typ Max Unit 0.3 × VCC V V V µA 0.10 +1 0.40 V V 0.40 V 1 V µA kΩ VCC − 0.3 V 0.7 × VCC 0.1 100 Power-up default current. All I/Os default to GPIs and are open; C8 and C9 default to GPIs; I2C is idle. GPIO internal pull-ups are approximately 100 k Ω. Table 3. Capacitance Loading1 Parameter I/O Input Capacitance I/O Output Loading Capacitance Capacitive Load for Each Bus Line 1 2 Symbol CIN COUT CB2 Guaranteed by design. CB = total capacitance of one bus line in picofarads. Rev. 0 | Page 3 of 24 Min Typ 1 Max 10 50 400 Unit pF pF pF ADP5587 AC CHARACTERISTICS Table 4. General AC Characteristics1 Parameter Delay from Reset Deassertion to I2C Access Keypad Unlock Timer Keypad Interrupt Mask Timer Debounce 1 Symbol RSTD TKUT TKIMT TD Min 60 Symbol fSCL tHIGH tLOW tSU, DAT tHD, DAT tSU, STA tHD, STA tBUF tSU, STO tR tF tSP Min Typ Max Unit μs sec sec μs Max 400 Unit kHz μs μs ns μs μs μs μs μs ns ns μs 7 31 275 Guaranteed by design. Table 5. I2C AC Electrical Characteristics1 Parameter SCL Clock Frequency SCL High Time SCL Low Time Data Setup Time Data Hold Time Setup Time for Repeated Start Hold Time for Start/Repeated Start Bus Free Time for Stop and Start Setup Time for Stop Condition Rise Time for SCL and SDA2 Fall Time for SCL and SDA2 Pulse Width of Suppressed Spike 2 0.6 1.3 100 0 0.6 0.6 1.3 0.6 20 + 0.1 CB 20 + 0.1 CB 0 0.9 300 300 50 Guaranteed by design. tR and tF are measured between 0.3 × VCC and 0.7 × VCC. SDA tLOW tR tF tSU, DAT tF tHD, STA tSP tBUF tR SCL S tHD, DAT tHIGH tSU, STA Sr tSU, STO P S 08612-002 1 Typ S = START CONDITION Sr = REPEATED START CONDITION P = STOP CONDITION Figure 2. I2C Interface Timing Diagram Rev. 0 | Page 4 of 24 ADP5587 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter VCC R0 to R7, C0 to C9 SCL SDA RST INT GND Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range ESD Machine Model ESD Human Body Model ESD Charged Device Model Soldering Condition Rating −0.3 V to + 4.0 V −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.3 V −0.3 V to +0.3 V −40°C to +85°C −40°C to +125°C −65°C to +150°C ±200 V ±2000 V ±1000 V JEDEC J-STD-020 θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance Package Type 24-Lead LFCSP_VQ Maximum Power ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 5 of 24 θJA 57.8 600 θJC 9.4 Unit °C/W mW ADP5587 24 23 22 21 20 19 INT SCL SDA VCC RST GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 PIN 1 INDICATOR ADP5587 TOP VIEW (Not to Scale) 18 17 16 15 14 13 C9 C8 C7 C6 C5 C4 NOTES 1. EXPOSED PAD MUST BE CONNECTED TO GROUND. 08612-003 R1 R0 C0 C1 C2 C3 7 8 9 10 11 12 R7 R6 R5 R4 R3 R2 Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic R7 R6 R5 R4 R3 R2 R1 R0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 GND RST 21 22 23 24 VCC SDA SCL INT EP EPAD Description GPIO, Row 7 in the Keypad Matrix. GPIO, Row 6 in the Keypad Matrix. GPIO, Row 5 in the Keypad Matrix. GPIO, Row 4 in the Keypad Matrix. GPIO, Row 3 in the Keypad Matrix. GPIO, Row 2 in the Keypad Matrix. GPIO, Row 1 in the Keypad Matrix. GPIO, Row 0 in the Keypad Matrix. GPIO, Column 0 in the Keypad Matrix. GPIO, Column 1 in the Keypad Matrix. GPIO, Column 2 in the Keypad Matrix. GPIO, Column 3 in the Keypad Matrix. GPIO, Column 4 in the Keypad Matrix. GPIO, Column 5 in the Keypad Matrix. GPIO, Column 6 in the Keypad Matrix. GPIO, Column 7 in the Keypad Matrix. GPIO, Column 8 in the Keypad Matrix. GPIO, Column 9 in the Keypad Matrix. Ground. Hardware Reset (Active Low). This pin resets the device to the power default conditions. The reset pin must be driven low for a minimum of 50 μs to be valid and to prevent false resets due to ESD glitches or noise in the system. If not used, RST must be tied high with a pull-up resistor. Supply Voltage, 1.7 V to 3.6 V. I2C Serial Data (Open Drain Requires External Pull-Up Resistor). I2C Clock. Processor Interrupt, Active Low, Open Drain. This pin can be pulled up to 2.7 V or 1.8 V for selection flexibility in the processor GPIO supply group. Exposed Pad. The exposed pad must be connected to ground. Rev. 0 | Page 6 of 24 ADP5587 THEORY OF OPERATION 8 9 10 11 12 13 14 15 16 C7 7 C6 6 C5 5 C4 4 C3 3 C2 2 C1 1 C0 24 R0 RST INT C8 17 R1 SCL SDA C9 CONTROL INTERFACE 20 R2 INT CONTROL REGISTERS 22 R3 RST 18 23 R4 SDA 21 R5 SCL R6 VCC ADP5587 19 R7 GND VCC A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0 G7 G6 G5 G4 G3 G2 G1 G0 H7 H6 H5 H4 H3 H2 H1 H0 I6 I5 I4 I3 I2 I1 I0 08612-009 I7 J7 J6 J5 J4 J3 J2 J1 J0 Figure 4. Typical Operating Circuit The ADP5587 is a GPIO expander that can be configured either as an 18 I/O port expander or as a 10 column × 8 row keypad matrix (80 keys maximum). It is ideal for cellular phone designs and other portable devices that require a large extended keypad and/or expanded I/Os. When smaller size keypads are required, unused GPIOs in the keypad matrix can be used as I/Os (GPOs and GPIs). All GPIOs (rows and columns) default to GPIs at power-up with pull-ups and debounce enabled. KEYPAD OPERATION Any number of rows and columns, up to 10 columns × 8 rows, can be configured to be part of the keypad matrix. The rows and columns that make up the keypad matrix must be configured by setting the corresponding bits in Register 0x1D to Register 0x1F. Key presses and releases appear in the key event table/registers with a decimal value of 1 (0x01 hexadecimal or 0000001 binary) through a decimal value of 80 (0x50 hexadecimal or 1010000 binary). See Table 9 for key event number assignments. The keypad, in idle mode, is configured with columns driven low and rows as inputs configured high with pull-up resistors. Table 9. Key Event Number Assignment Table Row R0 R1 R2 R3 R4 R5 R6 R7 C0 1 11 21 31 41 51 61 71 C1 2 12 22 32 42 52 62 72 C2 3 13 23 33 43 53 63 73 C3 4 14 24 34 44 54 64 74 C4 5 15 25 35 45 55 65 75 C5 6 16 26 36 46 56 66 76 C6 7 17 27 37 47 57 67 77 C7 8 18 28 38 48 58 68 78 C8 9 19 29 39 49 59 69 79 C9 10 20 30 40 50 60 70 80 When one key press or multiple key presses (short between column and row) occur, the internal state machine checks the row pins to determine which one is driven low and then triggers an internal interrupt. The state machine then starts a key scan cycle to determine which columns are involved in the key press. After a key has been pressed for 25 ms, the state machine sets the appropriate key number in the key event status register with the key-pressed bits set (the MSB in the key event register) in the order detected. The state machine then sets the KE_INT bit in Register 0x02. If the KE_IEN field in Register 0x01 is set, an interrupt is sent to the host processor. Rev. 0 | Page 7 of 24 ADP5587 To prevent glitches or narrow press times registering as valid key presses, the key scanner requires the key to be pressed for two scan cycles. The key scanner has a sampling period of 25 ms; therefore, the key must be pressed and held for at least 25 ms to register as pressed. If the key is continuously pressed, the key scanner continues to sample every 25 ms. If a pressed key is released for 25 ms or greater, the state machine sets the appropriate key number in the key event status register with the key-pressed bits cleared in the order detected. Because the release of a key is not necessarily in sync with the key scan sampling period, it may take between 25 ms and 50 ms for a key to register as released. After the key is registered as released, the key scanner returns to idle mode. Figure 5 shows the row and column pins connected to a typical 10 × 8, 80-switch keypad matrix. D0_PULL KEYPAD SCAN AND DECODE D1_PULL D2_PULL D4_PULL D3_PULL D5_PULL D6_PULL D7_PULL VCC R7 R6 R5 R4 R3 R2 R1 R0 C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0 G7 G6 G5 G4 G3 G2 G1 G0 H7 H6 H5 H4 H3 H2 H1 H0 I6 I5 I4 I3 I2 I1 I0 J6 J5 J4 J3 J2 J1 J0 Table 10 and Table 11 show the event sequences as they are logged in and read from the FIFO. The 10 FIFO registers are labeled A through J, and the keys are labeled A0 through J7. Table 10. Example of Event Sequence Key Pressed/Released A0 B1 A0 C2 B1 D3 C2 E4 E4 D3 Status Pressed Pressed Released Pressed Released Pressed Released Pressed Released Released Key Event Counter 1 2 3 4 5 6 7 8 9 10 Table 11. Interpretation of FIFO Event Reading B7 B6 B5 B4 B3 B2 B1 B0 I7 The first read of any of the FIFO registers displays the first event that happened and its status. Subsequent reads of the same register replace the register data with the next event that happens. If tracking of all the events is important, it is best to use a single register per event. After all the events in the FIFO are read, reading of any of the event registers yields a zero value. C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 A7 A6 A5 A4 A3 A2 A1 A0 J7 bits display the binary representation of the keys that are pressed or released. 08612-010 10 × 8 KEYPAD MATRIX NOTES: 1. Dx_PULL STANDS FOR GPIO PULL-UP. Figure 5. Keypad Decode Configuration Key Event Counter 10 9 8 7 6 5 4 3 2 1 0 1 Key Event Tracking The 10 key event registers are set to act as a FIFO, meaning that reading any of the 10 key event registers yields the key events in the order the keys were pressed and released. Tracking of key events is done with the help of the key event counter (the KEC field in Register 0x03) and the FIFO/key event registers (Register 0x04 through Register 0x0D). The KEC count increases as keys are pressed and released; up to 10 events can be logged in the counter. The FIFO/key event registers, on the other hand, display the key events and their status (pressed or released) as they are read out of the FIFO. The FIFO registers contain eight bits, with the MSB dedicated as the status bit (1 indicates a press and 0 indicates a release); the remaining seven Key Event Register Read N/A D E C F G A B H J I Key Event Register Content (Binary)1 N/A 1 0000000 1 0001100 0 0000000 1 0010111 0 0001100 1 0100010 0 0010111 1 0101101 0 0101101 0 0100010 Key Event Register Interpretation N/A Key A0 pressed Key B1 pressed Key A0 released Key C2 pressed Key B1 released Key D3 pressed Key C2 released Key E4 pressed Key E4 released Key D3 released The MSB indicates a key press or key release in the key event register: 1 = key press; 0 = key release. Key Event Overflow The ADP5587 is equipped with an overflow feature to handle key events beyond the FIFO capacity. When all events are filled, any additional events set the OVR_FLOW_INT bit in Register 0x02; if the OVR_FLOW_IEN bit in Register 0x01 is set, the host processor is also interrupted when overflow occurs. When the FIFO is not full, new events are added as the last events. The OVR_FLOW_M bit in Register 0x01 sets the mode of operation during overflows. Clearing the OVR_FLOW_M bit causes new incoming events to be discarded, and setting this bit rolls over and overwrites old data with new data starting at the first event. Rev. 0 | Page 8 of 24 ADP5587 The ADP5587 features automatic increment during I C read access, which allows the user to increment the address pointer without the need to send a read command for subsequent addresses. This minimizes processor intervention and, therefore, saves processor bandwidth and current drain. Bit 7 of Register 0x01 must be set to initiate auto-increment (see Figure 12 for the full write and read sequence). 2 Key Event Interrupt On a key event (KE) interrupt, the processor reads the interrupt status register to determine the cause of the interrupt. If the KE_INT bit in Register 0x02 is set, the processor reads the key event count from the KEC [3:0] field in Register 0x03 to determine the number of events. After reading all the events from the FIFO, it then reads the KEC field again (in Register 0x03) to make sure that no new events have come in. After all the events are read, the KEC field is decremented to zero (KEC = 0), and the KE_INT bit can be cleared by writing a 1 to it. Both key presses and key releases are capable of generating key event interrupts. The KE_INT bit cannot be cleared, and the INT pin cannot be deasserted, until the FIFO is cleared of all events. REG. 0x1D THROUGH REG. 0x1F KEYPAD MODE REG. 0x02 WRITE 1 TO CLEAR KE_INT REG. 0x01 KE_IEN KEC Figure 6. Key Event Interrupt Generation START NO KEY PRESS DETECTED YES YES KEY PRESS DETECTED GENERATE KE INTERRUPT START MASK TIMER NO YES FIRST UNLOCK KEY DETECTED NO YES YES MASK TIMER EXPIRES START UNLOCK1 TO UNLOCK2 NO NO FIRST UNLOCK KEY DETECTED UNLOCK1 TO UNLOCK2 TIMER EXPIRES YES NO YES START UNLOCK1 TO UNLOCK2 SECOND UNLOCK KEY DETECTED UNLOCK1 TO UNLOCK2 TIMER EXPIRES YES YES GENERATE KEYLOCK INTERRUPT NO YES NO MASK TIMER EXPIRES NO NO SECOND UNLOCK KEY DETECTED YES GENERATE KEYLOCK INTERRUPT Figure 7. Keypad Lock Interrupt Mask Timer Flowchart Rev. 0 | Page 9 of 24 08612-015 NO MASK TIMER = 0 AND REG. 0x03 READ KE(s) TO CLEAR INT DRIVE 08612-011 Auto-Increment ADP5587 Keypad Lock/Unlock Feature The ADP5587 has a locking feature that allows the user to lock the keypad or GPIs (configured to be part of the event table). When enabled, the keypad lock can prevent generation of key event interrupts and prevent key events from being recorded in the key event table. This feature comprises the Unlock Key 1 and Unlock Key 2 registers (Register 0x0F and Register 0x10, respectively), the keypad lock interrupt mask and keypad unlock timers (Register 0x0E), and the LCK1, LCK2, and keylock enable (K_LCK_EN) bits (Register 0x03). The unlock keys can be programmed with any value of the keys in the keypad matrix or any GPI event values that are part of the key event table. When the keypad lock interrupt mask timer is enabled, the user must press two specific keys before a keylock interrupt is generated or keypad events are recorded. After the keypad is locked (set Bit 6, Register 0x03 to enable the lock), the first time that the user presses any key, a key event interrupt is generated. No additional interrupt is generated unless both unlock key sequences are correct. If the correct unlock keys are not pressed before the mask timer expires, the state machine starts over. The first key event interrupt is generated to allow the software to see that the user has pressed a key so that the host can turn on the LCD and display the unlock message. The host then reads the lock status register to see if the keypad is unlocked. After the first key event interrupt, the state machine does not interrupt the processor again unless the correct sequence is keyed. The state machine is reset if the correct sequences are not keyed before the keypad lock interrupt mask timer expires. The state of the keypad lock interrupt mask bit (Register 0x01, Bit 2) in the configuration register determines whether the interrupt pin is asserted when the keylock interrupt status bit (Register 0x02, Bit 2) is set. Setting the keylock interrupt mask bit causes the INT pin to be asserted when the keylock interrupt status bit is set in Register 0x02; clearing that bit masks the interrupt, causing the interrupt pin not to respond to the keylock interrupt status bit. The mask interrupt timer should be set for the time that it takes for the LCD to dim or turn off so that, if a key is pressed, the backlight is set to bright mode again or reset to turn on the LCD. When the unlock mask interrupt timer equals 0, only the correct unlock sequence can generate an interrupt. Disabling the unlock mask interrupt timer allows the processor to remain undisturbed for situations in which the user, for example, has the phone in a pocket or purse and the keys are constantly pressed. The flowchart in Figure 6 shows the interaction of interrupt enable, key event counter, key event interrupt status, and interrupt generation. VCC KEY EVENT INTERRUPT GPIO INTERRUPT KEYLOCK INTERRUPT OR INT LOGIC INT OVERFLOW INTERRUPT GPIEM_ OVR_FLOW_ K_LCK_IM GPI_IEN KE_IEN K_LCK_EN CFG IEN 08612-014 KEYPAD LOCK INTERRUPT MASK TIMER INTERRUPT CONFIGURATION Figure 8. INT Pin Drive Rev. 0 | Page 10 of 24 ADP5587 GENERAL-PURPOSE INPUTS AND OUTPUTS The ADP5587 supports up to 18 programmable GPIOs that can be configured to address a variety of uses. Figure 9 shows the makeup of a typical GPIO block where GPIOx represents any of the 18 I/O lines. INTERRUPT REG. 0x26 CONDITION THROUGH 0x28 DECODE Dx_ILVL AND REG. 0x11 THROUGH 0x13 REG. 0x02 READ TWICE WRITE 1 TO CLEAR TO CLEAR Dx_IN_ISTAT GPI_INT INT DRIVE REG. 0x01 Dx_IN_IEN VCC Dx_PULL 08612-013 NOTES: 1. Dx_IN STANDS FOR ANY OF THE 18 GPIOs CONFIGURED AS GPIs. 2. Dx_ILVL STANDS FOR GPIO INTERRUPT LEVEL. 3. Dx_IN_IEN STANDS FOR GPI INTERRUPT ENABLE. 4. Dx_IN_STAT STANDS FOR GPI INTERRUPT STATUS. 5. GPI_INT STANDS FOR GPI INTERRUPT. Dx_IN_DBNC Dx_IN REG. 0x23 THROUGH 0x25 Dx_IN Figure 10. GPIO Interrupt Generation DEBOUNCE GPI Events VCC GPIOx Dx_OUT NOTES: 1. Dx_IN STANDS FOR ANY OF THE 18 GPIOs CONFIGURED AS GPIs. 2. Dx_OUT STANDS FOR ANY OF THE 18 GPIOs CONFIGURED AS GPOs. 3. Dx_IN_DBNC STANDS FOR GPI DEBOUNCE. 4. Dx_DIR STANDS FOR GPIO DIRECTION. 5. Dx_PULL STANDS FOR GPIO PULL-UP. 08612-012 Dx_DIR Figure 9. Typical GPIO Block General-Purpose Inputs (GPI) The ADP5587 allows the user to configure all or some of its GPIOs as GPIs (general-purpose inputs). After the GPIOs are configured as GPIs, the user can choose to also turn on pull-up resistors and interrupt generation capability, thus reducing the amount of software monitoring and processor interaction and saving power. The programmed level of the GPI interrupt determines the active level of the GPI pin. For example, if a GPI interrupt level is programmed as high, a high on that pin is considered active and meets the interrupt requirement. If the interrupt is programmed as low, a low on that pin is considered active and meets the interrupt requirement. GPI data status and interrupt status are reflected in the GPIO interrupt status and data status registers (Register 0x11 through Register 0x16). Caution is necessary during software implementation because an interrupt may be set immediately after the registers are set. To prevent this, the correct logic levels must be present at the GPIs, and the GPIO interrupt level must be set before GPIO interrupt enable or GPI event FIFO enable registers are set. Figure 10 shows the interrupt generation scheme, where Dx represents any one of the 18 GPIOs. A column or row configured as a GPI can be programmed to be part of the key event table and is, therefore, also capable of generating a key event interrupt. A key event interrupt caused by a GPI follows the same process flow as a key event interrupt caused by a key press or key release. GPIs configured as part of the key event table allow single key switches and other GPI interrupts to be monitored. As part of the event table, GPIs are represented by a decimal value of 97 (0x61 hexadecimal or 1100001 binary) through a decimal value of 114 (0x72 hexadecimal or 1110010 binary). See Table 12 and Table 13 for GPI event number assignments for rows and columns, respectively. Table 12. GPI Event Number Assignments for Rows R0 97 R1 98 R2 99 R3 100 R4 101 R5 102 R6 103 R7 104 Table 13. GPI Event Number Assignments for Columns C0 105 C1 106 C2 107 C3 108 C4 109 C5 110 C6 111 C7 112 C8 113 C9 114 For a GPI that is set as active high and is enabled in the key event table, the state machine adds an event to the event count and event tables whenever that GPI goes high. If the GPI is set to active low, a transition from high to low is considered a press and is also added to the event count and event table. After the interrupt state is met, the state machine internally sets an interrupt for the opposite state programmed in the register to prevent polling for the released state, thereby saving current. After the released state is achieved, it is added to the event table. The press and release are still indicated by Bit 7 in the event register (Register 0x04 through Register 0x0D). The GPI events can also be used as unlocked sequences. When the GPI_EM_REGx bit in Register 0x20 through Register 0x22 is set, GPI events are not tracked when the keypad is locked. The GPIEM_CFG bit (Register 0x01, Bit 6) must be cleared for the GPI events to be tracked in the event counter and event table when the keypad is locked. Rev. 0 | Page 11 of 24 ADP5587 275 Microsecond Interrupt Configuration General-Purpose Outputs (GPOs) The ADP5587 gives the user the flexibility of deasserting the interrupt for 275 μs while there is a pending event. When the INT_CFG bit in Register 0x01 is set, any attempt to clear the interrupt bit while the interrupt pin is already asserted results in a 275 μs deassertion. When the INT_CFG bit is cleared, the processor interrupt remains asserted if the host tries to clear the interrupt. This feature is particularly useful for software development and edge triggering applications. The ADP5587 allows the user to configure all or some of its GPIOs as GPOs. These GPOs can be used as extra enables for the host processor or simply as trigger outputs. When configured as an output (GPO), a digital buffer drives the pin to 0 V for a 0 and to VCC for a 1. To set any GPIO as a GPO, make sure that the corresponding bits in Register 0x1D through Register 0x1F are set for GPIO mode; then use Register 0x23 through Register 0x25 to set the corresponding bits for GPO mode. Debouncing Power-On Reset The ADP5587 has a 275 μs debounce time for GPIOs configured as GPIs and rows in keypad scanning mode. The reset line always has a 275 μs debounce time. For built-in power-up initialization for applications lacking a power-on reset signal, a reset pin, RST, allows the user to reset the registers to default values in the event of a brownout or other reset condition. Table 14. Device Configuration Matrix 10 × 8 8×8 8×7 8×6 8×5 7×7 7×6 7×5 6×6 6×5 6×4 … 0×0 Keypad Active Pins C0 to C9, R0 to R7 C0 to C7, R0 to R7 C0 to C7, R0 to R6 C0 to C7, R0 to R5 C0 to C7, R0 to R4 C0 to C6, R0 to R6 C0 to C6, R0 to R5 C0 to C6, R0 to R4 C0 to C5, R0 to R5 C0 to C5, R0 to R4 C0 to C5, R0 to R3 … None GPIO Number of Keys 80 64 56 48 40 49 42 35 36 30 24 … 0 Available GPIO 0 C8, C9 R7, C8, C9 R6, R7, C8, C9 R5 to R7, C8, C9 R7, C7 to C9 R6, R7, C7 to C9 R5 to R7, C7 to C9 R6, R7, C6 to C9 R5 to R7, C6 to C9 R4 to R7, C6 to C9 … R0 to R7, C0 to C9 Rev. 0 | Page 12 of 24 Number of GPIOs 0 2 3 4 5 4 5 6 6 7 8 … 18 ADP5587 I2C PROGRAMMING AND DIGITAL CONTROL Figure 12 shows a typical read sequence for reading back an internal register. The cycle begins with a start condition followed by the chip write address (0x68). The ADP5587 acknowledges the chip write address byte by pulling the data line low. The address of the register from which data is to be read is sent next. The ADP5587 acknowledges the register address byte by pulling the data line low. The cycle continues with a repeat start followed by the chip read address (0x69). The ADP5587 acknowledges the chip read address byte by pulling the data line low. The ADP5587 places the contents of the previously addressed register on the bus for readback. There is no acknowledge following the readback data byte, and the cycle is completed with a stop condition. The ADP5587 provides full software programmability to facilitate its adoption in various product architectures. All register programming is done via the I2C bus at Address 0x69 (01101001) for a read and Address 0x68 (01101000) for a write. All communication to the ADP5587 is performed via its I2Ccompatible serial interface. Figure 11 shows a typical write sequence for programming an internal register. The cycle begins with a start condition followed by the chip write address (0x68). The ADP5587 acknowledges the chip write address byte by pulling the data line low. The address of the register to which data is to be written is sent next. The ADP5587 acknowledges the register address byte by pulling the data line low. The data byte to be written is sent next. The ADP5587 acknowledges the data byte by pulling the data line low. A stop condition completes the sequence. 0 = WRITE 1 0 0 0 0 0 CHIP ADDRESS SUBADDRESS 0 SP ADP5587 RECEIVES DATA 08612-019 0 ADP5587 ACK 1 ADP5587 ACK 1 ADP5587 ACK ST 0 Figure 11. I2C Write Sequence 1 = READ 0 0 0 0 0 0 CHIP ADDRESS 0 0 0 0 1 1 0 ST 0 1 SUBADDRESS 1 0 1 0 0 CHIP ADDRESS 1 0 1 SP ADP5587 SENDS DATA 08612-020 1 ADP5587 NO ACK 0 ADP5587 ACK 1 ADP5587 ACK 1 ADP5587 ACK 0 = WRITE ST 0 Figure 12. I2C Read and Write Sequences 0 = WRITE 0 0 0 0 0 0 0 0 1 READ START ADDR 1 0 ST 0 1 1 0 1 0 CHIP ADDRESS 0 1 0 ... 0 ADP5587 SENDS DATA 1 Figure 13. I2C Read Auto-Increment Rev. 0 | Page 13 of 24 1 ST ADP5587 SENDS DATA N 08612-021 CHIP ADDRESS 0 STOP 0 ADP5587 NO ACK 1 ADP5587 ACK 0 ADP5587 ACK 1 ADP5587 ACK 1 ADP5587 ACK START ST 0 1 = READ ADP5587 REGISTERS The general behavior of registers is as follows: • • • • All registers are 0 on reset. All registers are read/write unless otherwise specified. Unused bits are read as 0. Interrupt bits are cleared by writing 1 to the flag; writing 0 or reading the flag has no effect, with the exception of the key press, key release, and GPIO interrupt status registers, which are cleared on a read. Table 15. Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 Register Name DEV_ID CFG INT_STAT KEY_LCK_EC_STAT KEY_EVENTA KEY_EVENTB KEY_EVENTC KEY_EVENTD KEY_EVENTE KEY_EVENTF KEY_EVENTG KEY_EVENTH KEY_EVENTI KEY_EVENTJ KP_LCK_TMR UNLOCK1 UNLOCK2 GPIO_INT_STAT1 GPIO_INT_STAT2 GPIO_INT_STAT3 GPIO_DAT_STAT1 GPIO_DAT_STAT2 GPIO_DAT_STAT3 GPIO_DAT_OUT1 GPIO_DAT_OUT2 GPIO_DAT_OUT3 GPIO_INT_EN1 GPIO_INT_EN2 GPIO_INT_EN3 KP_GPIO1 KP_GPIO2 KP_GPIO3 GPI_EM_REG1 GPI_EM_REG2 GPI_EM_REG3 GPIO_DIR1 GPIO_DIR2 GPIO_DIR3 GPIO_INT_LVL1 GPIO_INT_LVL2 GPIO_INT_LVL3 DEBOUNCE_DIS1 Description Device ID Configuration Register 1 Interrupt status register Keylock and event counter register Key Event Register A Key Event Register B Key Event Register C Key Event Register D Key Event Register E Key Event Register F Key Event Register G Key Event Register H Key Event Register I Key Event Register J Keypad Unlock 1 timer to Keypad Unlock 2 timer Unlock Key 1 Unlock Key 2 GPIO interrupt status GPIO interrupt status GPIO interrupt status GPIO data status, read twice to clear GPIO data status, read twice to clear GPIO data status, read twice to clear GPIO data out GPIO data out GPIO data out GPIO interrupt enable GPIO interrupt enable GPIO interrupt enable Keypad or GPIO selection Keypad or GPIO selection Keypad or GPIO selection GPI Event Mode 1 GPI Event Mode 2 GPI Event Mode 3 GPIO data direction GPIO data direction GPIO data direction GPIO level detect GPIO level detect GPIO level detect Debounce disable Rev. 0 | Page 14 of 24 ADP5587 Address 0x2A 0x2B 0x2C 0x2D 0x2E Register Name DEBOUNCE_DIS2 DEBOUNCE_DIS3 GPIO_PULL1 GPIO_PULL2 GPIO_PULL3 Description Debounce disable Debounce disable GPIO pull disable GPIO pull disable GPIO pull disable REGISTER DESCRIPTIONS Table 16. DEV_ID—Register 0x00 (Device ID) Register Name DEV_ID Register Description Device ID[3:0], MFG ID[7:4] Bit 7 MFID3 Bit 6 MFID2 Bit 5 MFID1 Bit 4 MFID0 Bit 3 DID3 Bit 2 DID2 Bit 1 DID1 Bit 0 DID0 Table 17. CFG—Register 0x01 (Configuration Register 1) Field AUTO_INC Bits 7 GPIEM_CFG 6 OVR_FLOW_M 5 INT_CFG 4 OVR_FLOW_IEN 3 K_LCK_IM 2 GPI_IEN 1 KE_IEN 0 Description I2C auto-increment. Burst read is supported; burst write is not supported. 1: I2C auto-increment is on. 0: I2C auto-increment is off. GPI event mode configuration. 1: GPI events are not tracked when the keypad is locked. 0: GPI events are tracked when the keypad is locked. Overflow mode. 1: overflow mode is on; register overflow data shifts in, starting at the last event and losing first event data. 0: overflow mode is off; register overflow data is lost. Interrupt configuration. 1: processor interrupt is deasserted for 275 μs and is reasserted with pending key events. 0: processor interrupt remains asserted when host tries to clear interrupt while there is a pending key event. Overflow interrupt enable. 1: overflow interrupt is enabled. 0: overflow interrupt is disabled. Keypad lock interrupt mask. 1: keypad lock interrupt is enabled. 0: keypad lock interrupt is disabled. GPI interrupt enable. 1: GPI interrupt is enabled. 0: GPI interrupt is disabled. Key events interrupt enable. 1: key events interrupt is enabled. 0: key events interrupt is disabled. Rev. 0 | Page 15 of 24 ADP5587 Table 18. INT_STAT—Register 0x02 (Interrupt Status Register) Field Not Used OVR_FLOW_INT1 Bits [7:4] 3 K_LCK_INT2 2 GPI_INT1, 3 1 KE_INT1, 3 0 1 2 3 Description N/A Overflow interrupt status. When set, write 1 to clear. 1: overflow interrupt is detected. 0: overflow interrupt is not detected. Keylock interrupt status. When set, write 1 to clear. 1: keylock interrupt is detected. 0: keylock interrupt is not detected. GPI interrupt status. When set, write 1 to clear. 1: GPI interrupt is detected. 0: GPI interrupt is not detected. Key events interrupt status. When set, write 1 to clear. 1: key events interrupt is detected. 0: key events interrupt is not detected. The KE_INT, GPI_INT, and OVR_FLOW_INT bits reflect the status of the interrupts when the interrupt types are enabled even if the processor interrupt is masked. The K_LCK_INT bit is the interrupt to the processor when the keypad lock sequence is triggered. If there is a pending key event or GPI interrupt in their respective registers, KE_INT is not cleared until the FIFO is empty, and GPI_INT is not cleared until the cause of the interrupt is resolved. The host must write a 1 to the KE_INT and GPI_INT bits to clear them. Table 19. KEY_LCK_EC_STAT—Register 0x03 (Keylock and Event Counter Register) Field K_LCK_EN Bits [6] LCK2, LCK1 KEC1 [5:4] [3:0] 1 Description 0: lock feature is disabled. 1: lock feature is enabled. Keypad lock status[1:0] (00 = unlocked; 11 = locked; read-only bits). Key event count of key event register. The KEC field indicates the key event count of key event registers that have values in the bit (KEC(0000) = 0 events, KEC(0001) = 1 event, KEC(1010) = 10 events). As the key events are read and cleared, the state machine automatically reduces the event count in KEC. Table 20. KEY_EVENTx—Register 0x04 to Register 0x0D (Key Event Register A to Key Event Register J)1 Register Name Register Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 KEY_EVENTA (Register 0x04) Key Event Register A status (KE[6:0] = key number), KP[7] = 0: released, 1: pressed (cleared on read) Key Event Register B status (KE[6:0] = key number), KP[7 ] = 0: released, 1: pressed (cleared on read) Key Event Register C status (KE[6:0] = key number), KP[7] = 0: released, 1: pressed (cleared on read) Key Event Register D status (KE[6:0] = key number), KP[7] = 0: released, 1: pressed (cleared on read) Key Event Register E status (KE[6:0] = key number), KP[7] = 0: released, 1: pressed (cleared on read) Key Event Register F status (KE[6:0] = key number), KP[7] = 0: released, 1: pressed (cleared on read) Key Event Register G status (KE[6:0] = key number), KP[7] = 0: released, 1: pressed (cleared on read) Key Event Register H status (KE[6:0] = key number), KP[7] = 0: released, 1: pressed (cleared on read) Key Event Register I status (KE[6:0] = key number), KP[7] = 0: released, 1: pressed (cleared on read) Key Event Register J status (KE[6:0] = key number), KP[7] = 0: released, 1: pressed (cleared on read) KA7 KA6 KA5 KA4 KA3 KA2 KA1 KA0 KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0 KC7 KC6 KC5 KC4 KC3 KC2 KC1 KC0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KE7 KE6 KE5 KE4 KE3 KE2 KE1 KE0 KF7 KF6 KF5 KF4 KF3 KF2 KF1 KF0 KG7 KG6 KG5 KG4 KG3 KG2 KG1 KG0 KH7 KH6 KH5 KH4 KH3 KH2 KH1 KH0 KI7 KI6 KI5 KI4 KI3 KI2 KI1 KI0 KJ7 KJ6 KJ5 KJ4 KJ3 KJ2 KJ1 KJ0 KEY_EVENTB (Register 0x05) KEY_EVENTC (Register 0x06) KEY_EVENTD (Register 0x07) KEY_EVENTE2 (Register 0x08) KEY_EVENTF (Register 0x09) KEY_EVENTG (Register 0x0A) KEY_EVENTH (Register 0x0B) KEY_EVENTI (Register 0x0C) KEY_EVENTJ (Register 0x0D) Data in key event registers is provided as a FIFO, where data is sequentially provided on each read, regardless of an event register read. The user can read the KEY_EVENTA register only for an event count or can read registers sequentially. 2 KE[6:0] reflects the value 1 to 80 for key press events and the value 97 to 114 for GPI events. For KE[7:0], 0 = key released event, 1 = key pressed event. For GPIEM_CFG, 0 reflects a change in the GPI from GPI_INT_LVL = true to GPI_INT_LVL = false; 1 reflects a change in the GPI in which the GPI_INT_LVL condition becomes true. 1 Rev. 0 | Page 16 of 24 ADP5587 Table 21. KP_LCK_TMR—Register 0x0E (Keypad Unlock 1 Timer to Keypad Unlock 2 Timer) Register Name Register Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 KP_LCK_TMR Keypad Unlock 1 timer to Keypad Unlock 2 timer[2:0] (0: disabled, 1 sec to 7 sec) Keypad Lock Interrupt Mask Timer[7:3] (0: disabled, 0 sec to 31 sec)1, 2 KIMT7 KIMT6 KIMT5 KIMT4 KIMT3 KLLT2 KLLT1 KLLT0 When the keypad lock interrupt mask timer is enabled, the user must press two specific keys before a keylock interrupt is generated or keypad events are recorded. After the keypad is locked, the first time that the user presses any key, a key event interrupt is generated. No additional interrupt is generated unless both unlock key sequences are correct; then a keylock interrupt is generated. When the interrupt mask timer is disabled (0), an interrupt is generated only when the correct full unlock sequence is completed. 2 The Unlock 1 timer and Unlock 2 timer keys can be either a key sequence or GPIEM_CFG sequence. The unlock timer keys can be programmed with any value of the keys in the keypad matrix or any GPI values that are part of the key event table. The keylock enable bit (Bit 6, Register 0x03) must be set to lock the keypad. 1 Table 22. UNLOCK1—Register 0x0F (Unlock Key 1) Register Name UNLOCK1 Register Description Unlock Key 1[6:0] (contains key number for Unlock Key 1; 0: disabled) Bit 7 N/A Bit 6 ULK6 Bit 5 ULK5 Bit 4 ULK4 Bit 3 ULK3 Bit 2 ULK2 Bit 1 ULK1 Bit 0 ULK0 Bit 7 N/A Bit 6 ULK6 Bit 5 ULK5 Bit 4 ULK4 Bit 3 ULK3 Bit 2 ULK2 Bit 1 ULK1 Bit 0 ULK0 Table 23. UNLOCK2—Register 0x10 (Unlock Key 2) Register Name UNLOCK2 Register Description Unlock Key 2[6:0] (contains key number for Unlock Key 2; 0: disabled) Table 24. GPIO_INT_STATx—Register 0x11 to Register 0x13 (GPIO Interrupt Status) Register Name GPIO_INT_STAT1 (Register 0x11) GPIO_INT_STAT2 (Register 0x12) GPIO_INT_STAT3 (Register 0x13) Register Description GPIO interrupt status (used to check GPIO interrupt status, cleared on read) GPIO interrupt status (used to check GPIO interrupt status, cleared on read) GPIO interrupt status (used to check GPIO interrupt status, cleared on read) Bit 7 R7IS Bit 6 R6IS Bit 5 R5IS Bit 4 R4IS Bit 3 R3IS Bit 2 R2IS Bit 1 R1IS Bit 0 R0IS C7IS C6IS C5IS C4IS C3IS C2IS C1IS C0IS N/A N/A N/A N/A N/A N/A C9IS C8IS Table 25. GPIO_DAT_STATx—Register 0x14 to Register 0x16 (GPIO Data Status) Register Name GPIO_DAT_STAT1 (Register 0x14) GPIO_DAT_STAT2 (Register 0x15) GPIO_DAT_STAT3 (Register 0x16) Register Description GPIO data status (shows GPIO state when read for inputs and outputs) GPIO data status (shows GPIO state when read for inputs and outputs) GPIO data status (shows GPIO state when read for inputs and outputs) Bit 7 R7DS Bit 6 R6DS Bit 5 R5DS Bit 4 R4DS Bit 3 R3DS Bit 2 R2DS Bit 1 R1DS Bit 0 R0DS C7DS C6DS C5DS C4DS C3DS C2DS C1DS C0DS N/A N/A N/A N/A N/A N/A C9DS C8DS Table 26. GPIO_DAT_OUTx—Register 0x17 to Register 0x19 (GPIO Data Out) Register Name GPIO_DAT_OUT1 (Register 0x17) GPIO_DAT_OUT2 (Register 0x18) GPIO_DAT_OUT3 (Register 0x19) Register Description GPIO data out (GPIO data to be written to GPIO out driver, inputs are not affected). This is needed so that the value can be written prior to being set as an output. GPIO data out (GPIO data to be written to GPIO out driver, inputs are not affected). This is needed so that the value can be written prior to being set as an output. GPIO data out (GPIO data to be written to GPIO out driver, inputs are not affected). This is needed so that the value can be written prior to being set as an output. Bit 7 R7DO Bit 6 R6DO Bit 5 R5DO Bit 4 R4DO Bit 3 R3DO Bit 2 R2DO Bit 1 R1DO Bit 0 R0DO C7DO C6DO C5DO C4DO C3DO C2DO C1DO C0DO N/A N/A N/A N/A N/A N/A C9DO C8DO Rev. 0 | Page 17 of 24 ADP5587 Table 27. GPIO_INT_ENx—Register 0x1A to Register 0x1C (GPIO Interrupt Enable) Register Name GPIO_INT_EN1 (Register 0x1A) GPIO_INT_EN2 (Register 0x1B) GPIO_INT_EN3 (Register 0x1C) Register Description GPIO interrupt enable (enables interrupts for GP inputs only) GPIO interrupt enable (enables interrupts for GP inputs only) GPIO interrupt enable (enables interrupts for GP inputs only) Bit 7 R7IE Bit 6 R6IE Bit 5 R5IE Bit 4 R4IE Bit 3 R3IE Bit 2 R2IE Bit 1 R1IE Bit 0 R0IE C7IE C6IE C5IE C4IE C3IE C2IE C1IE C0IE N/A N/A N/A N/A N/A N/A C9IE C8IE Table 28. KP_GPIOx—Register 0x1D to Register 0x1F (Keypad or GPIO Selection) Register Name KP_GPIO1 (Register 0x1D) KP_GPIO2 (Register 0x1E) KP_GPIO3 (Register 0x1F) Register Description Keypad or GPIO selection 0: GPIO 1: KP matrix Keypad or GPIO selection 0: GPIO 1: KP matrix Keypad or GPIO selection 0: GPIO 1: KP matrix Bit 7 R7 Bit 6 R6 Bit 5 R5 Bit 4 R4 Bit 3 R3 Bit 2 R2 Bit 1 R1 Bit 0 R0 C7 C6 C5 C4 C3 C2 C1 C0 N/A N/A N/A N/A N/A N/A C9 C8 Table 29. GPI_EM_REGx—Register 0x20 to Register 0x22 (GPI Event Mode 1 to GPI Event Mode 3) Register Name GPI_EM_REG1 (Register 0x20) GPI_EM_REG2 (Register 0x21) GPI_EM_REG3 (Register 0x22) Register Description GPI Event Mode Register 1 0: GPI not part of event FIFO 1: GPI part of event FIFO (R0 to R7) GPI Event Mode Register 2 0: GPI not part of event FIFO 1: GPI part of event FIFO (C0 to C7) GPI Event Mode Register 3 0: GPI not part of event FIFO 1: GPI part of event FIFO (C8 to C9) Bit 7 R7_EM Bit 6 R6_EM Bit R5_EM Bit 4 R4_EM Bit 3 R3_EM Bit 2 R2_EM Bit 1 R1_EM Bit 0 R0_EM C7_EM C6_EM C5_EM C4_EM C3_EM C2_EM C1_EM C0_EM NA NA NA NA NA NA C9_EM C8_EM Table 30. GPIO_DIRx—Register 0x23 to Register 0x25 (GPIO Data Direction) Register Name GPIO_DIR1 (Register 0x23) GPIO_DIR2 (Register 0x24) GPIO_DIR3 (Register 0x25) Register Description GPIO data direction 0: input 1: output GPIO data direction 0: input 1: output GPIO data direction 0: input 1: output Bit 7 R7D Bit 6 R6D Bit 5 R5D Bit 4 R4D Bit 3 R3D Bit 2 R2D Bit 1 R1D Bit 0 R0D C7D C6D C5D C4D C3D C2D C1D C0D N/A N/A N/A N/A N/A N/A C9D C8D Table 31. GPIO_INT_LVLx—Register 0x26 to Register 0x28 (GPIO Level Detect) Register Name GPIO_INT_LVL1 (Register 0x26) GPIO_INT_LVL2 (Register 0x27) GPIO_INT_LVL3 (Register 0x28) Register Description GPIO INT level detect 0: low 1: high GPIO INT level detect 0: low 1: high GPIO INT level detect 0: low 1: high Bit 7 R7IL Bit 6 R6IL Bit 5 R5IL Bit 4 R4IL Bit 3 R3IL Bit 2 R2IL Bit 1 R1IL Bit 0 R0IL C7IL C6IL C5IL C4IL C3IL C2IL C1IL C0IL N/A N/A N/A N/A N/A N/A C9IL C8IL Rev. 0 | Page 18 of 24 ADP5587 Table 32. DEBOUNCE_DISx—Register 0x29 to Register 0x2B (Debounce Disable) Register Name DEBOUNCE_DIS1 (Register 0x29) DEBOUNCE_DIS2 (Register 0x2A) DEBOUNCE_DIS3 (Register 0x2B) Register Description Debounce disable (inputs) 0: enabled 1: disabled Debounce disable (inputs) 0: enabled 1: disabled Debounce disable (inputs) 0: enabled 1: disabled Bit 7 R7DD Bit 6 R6DD Bit 5 R5DD Bit 4 R4DD Bit 3 R3DD Bit 2 R2DD Bit 1 R1DD Bit 0 R0DD C7DD C6DD C5DD C4DD C3DD C2DD C1DD C0DD N/A N/A N/A N/A N/A N/A C9DD C8DD Table 33. GPIO_PULLx—Register 0x2C to Register 0x2E (GPIO Pull Disable) Register Name GPIO_PULL1 (Register 0x2C) GPIO_PULL2 (Register 0x2D) GPIO_PULL3 (Register 0x2E) Register Description GPIO pull disable (remove pull-ups from inputs) 0: pull enabled 1: pull disabled GPIO pull disable (remove pull-ups from inputs) 0: pull enabled 1: pull disabled GPIO pull disable (remove pull-ups from inputs) 0: pull enabled 1: pull disabled Bit 7 R7PD Bit 6 R6PD Bit 5 R5PD Bit 4 R4PD Bit 3 R3PD Bit 2 R2PD Bit 1 R1PD Bit 0 R0PD C7PD C6PD C5PD C4PD C3PD C2PD C1PD C0PD N/A N/A N/A N/A N/A N/A C9PD C8PD Rev. 0 | Page 19 of 24 ADP5587 APPLICATIONS INFORMATION 17 8 9 C0 10 11 12 13 14 15 16 C7 7 C6 6 C5 5 C4 4 C3 3 C2 2 C1 1 R0 24 R1 HOST PROCESSOR SCL SDA RST INT C8 20 R2 INT C9 CONTROL INTERFACE CONTROL REGISTERS 22 R3 RST 18 23 R4 SDA 21 R5 SCL R6 VCC ADP5587 19 R7 GND VCC VCC GPI1 VCC GPI2 ENABLE 2 (GPO) BACKLIGHT ENABLE (GPO) A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 BACKLIGHT DRIVER C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0 G7 G6 G5 G4 G3 G2 G1 G0 H7 H6 H5 H4 H3 H2 H1 H0 I7 I6 I5 I4 I3 I2 I1 I0 J5 J4 J3 J2 J1 J0 08612-022 J7 J6 PWM OUTPUT Figure 14. ADP5587 Detailed Application Block Diagram APPLICATIONS OVERVIEW KEYPAD CURRENT The ADP5587 is designed to complement host processors in a variety of ways. Its versatility makes it the ideal solution for mobile platforms that require extended keypads and GPIO expanders. The programmable registers give the designer the flexibility to configure any or all of its GPIOs in a variety of ways. Figure 14 shows a detailed application diagram. Keypad current drain varies based on how many keys and how many rows and columns are pressed during multiple key presses. Table 34 shows the typical current drain for a single key press and for two key presses. Table 34. Typical Current Drain Number of Key Presses 1 2 1 TA = TJ = −40°C to +85°C. Rev. 0 | Page 20 of 24 Conditions1 VCC = 1.8 V to 3.0 V VCC = 1.8 V to 3.0 V Typical 55 100 Unit μA μA ADP5587 KEYPAD MATRIX RST J0 A1 B1 C1 D1 E1 F1 G1 H1 I1 J1 A2 B2 C2 D2 E2 F2 G2 H2 I2 J2 A3 B3 C3 D3 E3 F3 G3 H3 I3 J3 A4 B4 C4 D4 E4 F4 G4 H4 I4 J4 A5 B5 C5 D5 E5 F5 G5 H5 I5 J5 A6 B6 C6 D6 E6 F6 G6 H6 I6 J6 A7 B7 C7 D7 E7 F7 G7 H7 I7 J7 ADP5587 BACKLIGHT ENABLE PWM BACKLIGHT DRIVER EXPANDED GPIOs BACKLIGHT Figure 15. Integration Block Diagram Rev. 0 | Page 21 of 24 08612-023 HOST PROCESSOR I2C INT A0 B0 C0 D0 E0 F0 G0 H0 I0 ADP5587 OUTLINE DIMENSIONS PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.30 0.25 0.20 0.50 BSC PIN 1 INDICATOR 24 19 18 1 EXPOSED PAD TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 13 12 6 7 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 SEATING PLANE 2.20 2.10 SQ 2.00 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8. 072809A 0.20 REF Figure 16. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-24-10) Dimensions shown in millimeters ORDERING GUIDE Model1 ADP5587ACPZ-R7 1 Temperature Range −40°C to +85°C Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Z = RoHS Compliant Part. Rev. 0 | Page 22 of 24 Package Option CP-24-10 ADP5587 NOTES Rev. 0 | Page 23 of 24 ADP5587 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08612-0-12/09(0) Rev. 0 | Page 24 of 24