AMD AM29BDS643GT7MVAI

Am29BDS643G
Data Sheet
RETIRED
PRODUCT
This product has been retired and is not recommended for designs. For new designs, S29NS064J
supersedes Am29BDS643G. Please refer to the S29NS-J family data sheet for specifications and
ordering information. Availability of this document is retained for reference and historical purposes
only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 25692
Revision A
Amendment 2
Issue Date May 8, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29BDS643G
64 Megabit (4 M x 16-Bit)
CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
This product has been retired and is not recommended for designs. For new designs, S29NS064J supersedes Am29BDS643G. Please refer to the S29NS-J family data sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
■ Single 1.8 volt read, program and erase (1.7 to
1.9 volt)
■ Multiplexed Data and Address for reduced I/O
count
— A0–A15 multiplexed as D0–D15
— Addresses are latched by AVD# control input
when CE# low
■ Simultaneous Read/Write operation
— Data can be continuously read from one bank
while executing erase/program functions in other
bank
— Zero latency between read and write operations
■ Read access times at 66/54/40 MHz
— Burst access times of 11/13.5/20 ns @ 30 pF
at industrial temperature range
— Asynchronous random access times
of 55/70/70 ns @ 30 pF
— Synchronous random access times
of 71/87.5/95 ns @ 30 pF
■ Burst length
— Continuous linear burst
— 8/16/32 word linear burst with wrap around
■ Power dissipation (typical values, 8 bits
switching, CL = 30 pF)
— Burst Mode Read: 25 mA
— Simultaneous Operation: 40 mA
— Program/Erase: 15 mA
— Standby mode: 0.2 µA
■ Sector Architecture
— Eight 8 Kword sectors and one hundred
twenty-six 32 Kword sectors
— Banks A and B each contain four 8 Kword
sectors and thirty-one 32 Kword sectors; Banks
C and D each contain thirty-two 32 Kword
sectors
■ Sector Protection
— Software command sector locking
— WP# protects the last two boot sectors
— All sectors locked when VPP = VIL
■ Handshaking feature
— Provides host system with minimum possible
latency by monitoring RDY
■ Supports Common Flash Memory
Interface (CFI)
■ Software command set compatible with JEDEC
42.4 standards
— Backwards compatible with Am29F and Am29LV
families
■ Manufactured on 0.17 µm process technology
■ Minimum 1 million erase cycle guarantee
per sector
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Data# Polling and toggle bits
— Provides a software method of detecting
program and erase operation completion
■ Erase Suspend/Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Hardware reset input (RESET#)
— Hardware method to reset the device for reading
array data
■ CMOS compatible inputs and outputs
■ Package
— 44-ball Very Thin FBGA
Publication# 25692 Revision: A Amendment: 2
Issue Date: May 8, 2006
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29BDS643G is a 64 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory
device, organized as 4,194,304 words of 16 bits each.
This device uses a single VCC of 1.7 to 1.9 V to read,
program, and erase the memory array. A 12.0-volt VPP
may be used for faster program performance if desired.
The device can also be programmed in standard
EPROM programmers.
The device uses Chip Enable (CE#), Write Enable
(WE#), Address Valid (AVD#) and Output Enable
(OE#) to control asynchronous read and write operations. For burst operations, the device additionally
requires Power Saving (PS), Ready (RDY), and Clock
(CLK). This implementation allows easy interface with
minimal glue logic to microprocessors/microcontrollers
for high performance read operations.
At 66 MHz, the Am29N643 provides a burst access of
11 ns at 30 pF with initial access times of 71 ns at 30
pF. At 54 MHz, the device provides a burst access of
13.5 ns at 30 pF with initial access times of 87.5 ns at
30 pF. At 40 MHz, the device provides a burst access
of 20 ns at 30 pF with initial access times of 95 ns at 30
pF. The device operates within the industrial temperature range of –40°C to +85°C. The device is offered in
the 44-ball Very Thin FBGA package.
The device offers complete compatibility with the
JEDEC 42.4 single-power-supply Flash command
set standard. Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory
space into four banks. The device allows a host system to program or erase in one bank, then
immediately and simultaneously read from another
bank, with zero latency. This releases the system from
waiting for the completion of program or erase
operations.
The device is divided as shown in the following table:
Bank A & B Sectors
Quantity
Size
4
8 Kwords
31
Quantity
Size
32
32 Kwords
32 Kwords
32 Mbits total
2
Bank C & D Sectors
32 Mbits total
The host system can detect whether a program or
erase operation is complete by using the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle
bits). After a program or erase cycle has been completed, the device automatically returns to reading
array data.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write operations during power transitions. The device also offers
three types of data protection at the sector level. The
sector lock/unlock command sequence disables or
re-enables both program and erase operations in any
sector. When at VIL, WP# locks the outermost sectors.
Finally, when VPP is at VIL, all sectors are locked.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly reduced in both modes.
Am29BDS643G
25692A2 May 8, 2006
D A T A
S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram of
Simultaneous Operation Circuit . . . . . . . . . . . . . . 5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6
Special Handling Instructions for FBGA Package .................... 6
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Device Bus Operations .......................................................9
Requirements for Asynchronous Read Operation (Non-Burst) 9
Requirements for Synchronous (Burst) Read Operation .......... 9
Continuous Burst ...................................................................... 9
8-, 16-, and 32-Word Linear Burst with Wrap Around ............ 10
Table 2. Burst Address Groups .......................................................10
Programmable Wait State ...................................................... 10
Handshaking Feature ............................................................. 10
Power Saving Function ........................................................... 11
Simultaneous Read/Write Operations with Zero Latency ....... 11
Writing Commands/Command Sequences ............................ 11
Accelerated Program Operation ............................................. 11
Autoselect Functions .............................................................. 11
Automatic Sleep Mode ........................................................... 12
RESET#: Hardware Reset Input ............................................. 12
Output Disable Mode .............................................................. 12
Hardware Data Protection ...................................................... 12
Low VCC Write Inhibit ............................................................ 12
Write Pulse “Glitch” Protection ............................................... 12
Logical Inhibit .......................................................................... 12
Common Flash Memory Interface (CFI) . . . . . . . 13
Table 3. CFI Query Identification String ..........................................13
Table 4. System Interface String .....................................................14
Table 5. Device Geometry Definition ..............................................14
Table 6. Primary Vendor-Specific Extended Query ........................15
Table 7. Sector Address Table ........................................................16
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 20
Reading Array Data ................................................................ 20
Set Configuration Register Command Sequence ................... 20
Table 8. Burst Modes ......................................................................20
Handshaking Feature ............................................................. 20
Table 9. Wait States for Handshaking .............................................21
Enable PS (Power Saving) Mode Command Sequence ........ 21
Sector Lock/Unlock Command Sequence .............................. 21
Reset Command ..................................................................... 21
Autoselect Command Sequence ............................................ 21
Program Command Sequence ............................................... 22
Unlock Bypass Command Sequence ..................................... 22
Figure 1. Program Operation .......................................................... 23
Chip Erase Command Sequence ........................................... 23
Sector Erase Command Sequence ........................................ 23
Erase Suspend/Erase Resume Commands ........................... 24
May 8, 2006 25692A2
Figure 2. Erase Operation.............................................................. 24
Table 10. Command Definitions .................................................... 25
Write Operation Status . . . . . . . . . . . . . . . . . . . . 26
DQ7: Data# Polling ................................................................. 26
Figure 3. Data# Polling Algorithm .................................................. 26
DQ6: Toggle Bit I .................................................................... 27
Figure 4. Toggle Bit Algorithm........................................................ 27
DQ2: Toggle Bit II ................................................................... 28
Table 11. DQ6 and DQ2 Indications .............................................. 28
Reading Toggle Bits DQ6/DQ2 ............................................... 28
DQ5: Exceeded Timing Limits ................................................ 28
DQ3: Sector Erase Timer ....................................................... 29
Table 12. Write Operation Status ................................................... 29
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 30
Figure 5. Maximum Negative Overshoot Waveform ...................... 30
Figure 6. Maximum Positive Overshoot Waveform........................ 30
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 7. Test Setup....................................................................... 32
Table 13. Test Specifications ......................................................... 32
Key to Switching Waveforms. . . . . . . . . . . . . . . . 32
Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . 32
Figure 8. Input Waveforms and
Measurement Levels...................................................................... 32
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33
Synchronous/Burst Read ........................................................ 33
Figure 9. Burst Mode Read (66 and 54 MHz) ................................ 33
Figure 10. Burst Mode Read (40 MHz) .......................................... 34
Asynchronous Read ............................................................... 35
Figure 11. Asynchronous Mode Read............................................ 35
Figure 12. Reset Timings ............................................................... 36
Erase/Program Operations ..................................................... 37
Figure 13. Program Operation Timings.......................................... 38
Figure 14. Chip/Sector Erase Operations ...................................... 39
Figure 15. Accelerated Unlock Bypass Programming Timing........ 40
Figure 16. Data# Polling Timings (During Embedded Algorithm) .. 41
Figure 17. Toggle Bit Timings (During Embedded Algorithm)........ 41
Figure 18. 8-, 16-, and 32-Word Linear Burst
Address Wrap Around.................................................................... 42
Figure 19. Latency with Boundary Crossing (54 MHz and 66 MHz) 42
Figure 20. Initial Access with Power Saving (PS)
Function and Address Boundary Latency ...................................... 43
Figure 21. Example of Extended Valid Address Reducing Wait State
Usage............................................................................................. 43
Figure 22. Back-to-Back Read/Write Cycle Timings ...................... 44
Erase and Programming Performance . . . . . . . 45
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 46
VDA044—44-Ball Very Thin Fine-Pitch Ball Grid Array
(FBGA) 9.2 x 8.0 mm Package ............................................... 46
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 47
Am29BDS643G
3
D A T A
S H E E T
PRODUCT SELECTOR GUIDE
Am29BDS643G
Part
Number
Synchronous/Burst
7G
(40 MHz)
7M
(54 MHz)
5K
(66 MHz)
Max Initial Access Time, ns
(tIACC)
95
87.5
71
Max Burst Access Time, ns
(tBACC)
20
13.5
Max OE# Access, ns (tOE)
20
13.5
Speed Option
VCC =
1.7 – 1.9 V
Asynchronous
Speed Option
7G/7M
5K
Max Access Time, ns (tACC)
70
55
11
Max CE# Access, ns (tCE)
70
55
11
Max OE# Access, ns (tOE)
20
11
BLOCK DIAGRAM
VCC
VSS
PS
A/DQ0–A/DQ15
RDY
Buffer
PS Buffer
RDY
Erase Voltage
Generator
WE#
RESET#
VPP
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
VCC
Detector
CLK
Burst
State
Control
Address Latch
CE#
OE#
AVD#
Input/Output
Buffers
Timer
Burst
Address
Counter
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0–A21
A/DQ0–A/DQ15
A16–A21
4
Am29BDS643G
25692A2 May 8, 2006
D A T A
S H E E T
Bank A Address
Y-Decoder
VCC
VSS
Bank A
Latches and
Control Logic
BLOCK DIAGRAM OF
SIMULTANEOUS OPERATION CIRCUIT
DQ0–DQ15
A0–A21
X-Decoder
OE#
AVD#
DQ0–DQ15
DQ0–
DQ15
PS
RDY
Status
Control
A0–A21
Bank C Address
A0–A21
Y-Decoder
X-Decoder
Bank C
A0–A21
Bank D Address
Y-Decoder
X-Decoder
Bank D
OE#
Latches and
Control Logic
CE#
OE#
STATE
CONTROL
&
COMMAND
REGISTER
DQ0–DQ15
OE#
Latches and
Control Logic
WE#
DQ0–DQ15
X-Decoder
A0–A21
RESET#
Bank B
Latches and
Control Logic
Y-Decoder
Bank B Address
DQ0–DQ15
Note: A0–A15 are multiplexed with DQ0–DQ15.
May 8, 2006 25692A2
Am29BDS643G
5
D A T A
S H E E T
CONNECTION DIAGRAM
44-Ball Very Thin FBGA
Top View, Balls Facing Down
NC
NC
A1
A2
A3
A4
A5
A6
A7
A8
A9
RDY
A21
GND
CLK
VCC
WE#
VPP
A19
A17
NC
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
VCC
A16
A20
AVD#
PS RESET# WP#
A18
CE#
GND
C1
C2
C3
C4
C5
C8
C9
C10
C6
C7
A10
GND A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE#
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
A/DQ15 A/DQ14 GND A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCC A/DQ1 A/DQ0
NC
NC
Special Handling Instructions for FBGA
Package
Special handling is required for Flash Memory products
in FBGA packages.
6
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
T h e p a c k a g e a n d / o r d a t a i n t e g r i t y m ay b e
compromised if the package body is exposed to
temperatures above 150°C for prolonged periods of
time.
Am29BDS643G
25692A2 May 8, 2006
D A T A
S H E E T
INPUT/OUTPUT DESCRIPTIONS
A16–A21
=
Address Inputs
A/DQ0–
A/DQ15
=
Multiplexed Address/Data input/output
CE#
=
Chip Enable Input. Asynchronous
relative to CLK for the Burst mode.
OE#
=
Output Enable Input. Asynchronous
relative to CLK for the Burst mode.
WE#
=
Write Enable Input.
VCC
=
Device Power Supply (1.7 V–1.9 V).
VSS
=
Ground
NC
=
No Connect; not connected internally
RDY
=
Ready output; indicates the status of
the Burst read. Low = data not valid at
expected time. High = data valid.
CLK
=
The first rising edge of CLK in
conjunction with AVD# low latches
address input and activates burst
mode operation. After the initial word
is output, subsequent rising edges of
CLK increment the internal address
counter. CLK should remain low
during asynchronous access.
AVD#
=
are inverted. Low = data not inverted;
High = data inverted
During write or command operations,
if the PS input is taken high the input
data will be inverted internally; if the
PS input is low the input data will not
be inverted internally
RESET#
=
Hardware reset input. Low = device
resets and returns to reading array
data
WP#
=
Hardware write protect input. Low =
disables writes to SA132 and SA133
VPP
=
At 12 V, accelerates programming;
automatically places device in unlock
bypass mode. At VIL, disables
program and erase functions. Should
be at VIH for all other conditions.
LOGIC SYMBOL
6
Address Valid input. Indicates to
device that the valid address is
present on the address inputs
(address bits A0–A15 are multiplexed,
address bits A16–A21 are address
only).
Low = for asynchronous mode,
indicates valid address; for burst
mode, causes starting address to be
latched on rising edge of CLK.
High = device ignores address inputs
PS
=
A16–A21
16
A/DQ0–
A/DQ15
CLK
CE#
OE#
WE#
PS
RESET#
AVD#
RDY
WP#
VPP
Power Saving input/output
During a read operation, PS indicates
whether or not the data on the outputs
May 8, 2006 25692A2
Am29BDS643G
7
D A T A
S H E E T
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Am29BDS643G
T
5
K
VA
I
TEMPERATURE RANGE
I
= Industrial (–40°C to +85°C)
PACKAGE TYPE
VA
= 44-Ball Very Thin Fine-Pitch Grid Array (FBGA)
0.5 mm pitch, 9.2 x 8.0 mm package (VDA044)
CLOCK RATE AND HANDSHAKING
G
= 40 MHz with handshaking
M
= 54 MHz with handshaking
K
= 66 MHz with handshaking
ASYNCHRONOUS SPEED OPTIONS
7
= 70 ns asynchronous read access
5
= 55 ns asynchronous read access
BOOT CODE SECTOR ARCHITECTURE
T
=
Top sector
DEVICE NUMBER/DESCRIPTION
Am29BDS643G
64 Megabit (4 M x 16-Bit) CMOS Flash Memory, Simultaneous Read/Write, Burst Mode Flash Memory
1.8 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations
Valid Combination configuration planned to be supported for this
device.
8
Order Number
Package Marking
Am29BDS643GT7GVAI
N643GT7GI
Am29BDS643GT7MVAI
N643GT7MI
Am29BDS643GT5KVAI
N643GT5KI
Am29BDS643G
25692A2 May 8, 2006
D A T A
S H E E T
DEVICE BUS OPERATIONS
the register serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the
commands, along with the address and data information needed to execute the command. The contents of
Table 1.
Operation
Device Bus Operations
CE#
OE#
WE#
A16–21 A/DQ0–15 RESET#
CLK
Asynchronous Read
L
L
Write
L
Standby (CE#)
Hardware Reset
AVD#
H
Addr In
I/O
H
H/L
H
L
Addr In
I/O
H
H/L
H
X
X
X
HIGH Z
H
H/L
X
X
X
X
X
HIGH Z
L
X
X
Load Starting Burst Address
L
H
H
Addr In
Addr In
H
Advance Burst to next address with appropriate
Data presented on the Data Bus
L
L
H
X
Burst
Data Out
H
H
Terminate current Burst read cycle
H
X
H
X
HIGH Z
H
X
Terminate current Burst read cycle via RESET#
X
X
H
X
HIGH Z
L
Terminate current Burst read cycle and start
new Burst read cycle
L
H
H
X
I/O
H
Burst Read Operations
X
X
Legend: L = Logic 0, H = Logic 1, X = Don’t Care.
Requirements for Asynchronous
Read Operation (Non-Burst)
ensures that no spurious alteration of the memory
content occurs during the power transition.
To read data from the memory array, the system must
asser t a valid address on A/DQ0–A/DQ15 and
A16–A21, while AVD# and CE# are at V IL . WE#
should remain at V IH . Note that CLK must not be
switching during asynchronous read operations. The
rising edge of AVD# latches the address, after which
the system can drive OE# to VIL. The data will appear
on A/DQ0–A/DQ15. (See Figure 11.) Since the memory array is divided into four banks, each bank remains
enabled for read access until the command register
contents are altered.
Requirements for Synchronous (Burst)
Read Operation
Address access time (tACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (t C E ) is the delay from the stable
addresses and stable CE# to valid data at the outputs.
The output enable access time (tOE) is the delay from
the falling edge of OE# to valid data at the output.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
May 8, 2006 25692A2
The device is capable of four different burst read modes
(see Table 8): continuous burst read; and 8-, 16-, and
32-word linear burst reads with wrap around capability.
Continuous Burst
When the device first powers up, it is enabled for asynchronous read operation. The device will automatically
be enabled for burst mode on the first rising edge on
the CLK input, while AVD# is held low for one clock
cycle. Prior to activating the clock signal, the system
should determine how many wait states are desired for
the initial word (t IACC ) of each burst session. The
system would then write the Set Configuration Register
command sequence. The system may optionally activate the PS mode (see “Power Saving Function”) by
writing the Enable PS Mode command sequence at
this time, but note that the PS mode can only be disabled by a hardware reset. (See “Command Defini-
Am29BDS643G
9
D A T A
tions” and “Programmable Wait State” for further
details).
The initial word is output tIACC after the rising edge of
the first CLK cycle. Subsequent words are output tBACC
after the rising edge of each successive clock cycle,
which automatically increments the internal address
counter. Note that the device has a fixed internal
address boundary that occurs every 64 words,
starting at address 00003Eh. The transition from
the highest address 3FFFFFh to 000000h is also a
boundary crossing. During the time the device is outputting the 64th word (address 00003Eh, 00007Eh,
0000BEh, etc.), a two cycle latency occurs before data
appears for the next address (address 00003Fh,
00007Fh, 0000BFh, etc.). The RDY output indicates
this condition to the system by pulsing low. See Figure
19.
The device will continue to output continuous, sequential burst data, wrapping around to address 000000h
after it reaches the highest addressable memory location, until the system asserts CE# high, RESET# low,
or AVD# low in conjunction with a new address. See
Table 1. The reset command does not terminate the
burst read operation.
If the host system crosses the bank boundary while
reading in burst mode, and the device is not programming or erasing, a two-cycle latency will occur as
described above. If the host system crosses the bank
boundary while the device is programming or erasing,
the device will provide asynchronous read status information. The clock will be ignored. After the host has
completed status reads, or the device has completed
the program or erase operation, the host can restart a
burst operation using a new address and AVD# pulse.
If the clock frequency is less than 6 MHz during a burst
mode operation, additional latencies will occur. RDY
indicates the length of the latency by pulsing low.
8-, 16-, and 32-Word Linear Burst with Wrap Around
The remaining three modes are of the linear wrap
around design, in which a fixed number of words are
read from consecutive addresses. In each of these
modes, the burst addresses read are determined by
the group within which the starting address falls. The
groups are sized according to the number of words
read in a single burst sequence for a given mode (see
Table 2.)
Table 2.
Mode
Burst Address Groups
Group Size Group Address Ranges
8-word
8 words
0-7h, 8-Fh, 10-17h, 18-1Fh...
16-word
16 words
0-Fh, 10-1Fh, 20-2Fh, 30-3Fh...
32-word
32 words
00-1Fh, 20-3Fh, 40-5Fh, 60-7Fh...
As an example: if the starting address in the 8-word
mode is 39h, the address range to be read would be
10
S H E E T
38-3Fh, and the burst sequence would be
39-3A-3B-3C-3D-3E-3F-38h. The burst sequence
begins with the starting address written to the device,
but wraps back to the first address in the selected
group. In a similar fashion, the 16-word and 32-word
Linear Wrap modes begin their burst sequence on the
starting address written to the device, and then wrap
back to the first address in the selected address group.
Note that in these three burst read modes the
address pointer does not cross the boundary that
occurs every 64 words; thus, no wait states are
inserted (except during the initial access).
If the clock frequency is less than 6 MHz during a burst
mode operation, additional latencies will occur. RDY
indicates the length of the latency by pulsing low.
Programmable Wait State
The programmable wait state feature indicates to the
device the number of additional clock cycles that must
elapse after AVD# is driven active before data will be
available. Upon power up, the device defaults to the
maximum of seven total cycles. The total number of
wait states is programmable from two to seven cycles.
The wait state command sequence requires three
cycles; after the two unlock cycles, the third cycle
address should be written according to the desired wait
state as shown in Table 8. Address bits A11-A0 should
be set to 555h, while addresses bits A16-A12 set the
wait state. For further details, see “Set Configuration
Register Command Sequence”.
Handshaking Feature
The handshaking feature allows the host system to
simply monitor the RDY signal from the device to determine when the initial word of burst data is ready to be
read. The host system should use the wait state
command sequence to set the number of wait states
for optimal burst mode operation (02h for 40 MHz
clock, 03h for 54 and 66 MHz clock). The initial word of
burst data is indicated by the rising edge of RDY after
OE# goes low.
The handshaking feature may be verified by writing the
autoselect command sequence to the device. See
“Autoselect Command Sequence” for details.
For optimal burst mode performance on devices
without the handshaking option, the host system must
set the appropriate number of wait states in the flash
device depending on such factors as clock frequency,
presence of a boundary crossing, or an odd or even
starting address. See “Set Configuration Register
Command Sequence” section for more information.
The autoselect function allows the host system to distinguish flash devices that have handshaking from
those that do not. See the “Autoselect Command
Sequence” section for more information.
Am29BDS643G
25692A2 May 8, 2006
D A T A
Power Saving Function
The Power Save function reduces the amount of
switching on the data output bus by changing the
minimum number of bits possible, thereby reducing
power consumption. This function is active only during
burst mode operations.
The device compares the word previously output to the
system with the new word to be output. If the number of
bits to be switched is 0–8 (less than half the bus width),
the device simply outputs the new word on the data
bus. If, however, the number of bits that must be
switched is 9 or higher, the data is inverted before being
output on the data bus. This effectively limits the
maximum number of bits that are switched for any
given read cycle to eight. The device indicates to the
system whether or not the data is inverted via the PS
(power saving) output. If the word on the data bus is not
inverted, PS = V IL ; if the word on the data bus is
inverted, PS = VIH.
During initial power up the PS function is disabled. To
enable the PS function, the system must write the
Enable PS command sequence to the flash device (see
the Command Definitions table).
When the PS function is enabled, one additional clock
cycle is inserted during the initial and second access of
a burst sequence. See Figure 20. The RDY output indicates this condition to the system.
The device is also capable of receiving inverted data
during command and write operations. The host
system must indicate to the device via the PS input
whether or not the input data is inverted. PS must be
driven to VIH for inverted data, or to VIL for non-inverted
data.
To disable the PS function, the system must hardware
reset the device (drive the RESET# input low).
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in one of the
other three banks of memory. An erase operation may
also be suspended to read from or program to another
location within the same bank (except the sector being
erased). Figure 22 shows how read and write cycles
may be initiated for simultaneous operation with zero
latency. Refer to the DC Characteristics table for
read-while-program and read-while-erase current
specifications.
Writing Commands/Command Sequences
The device has inputs/outputs that accept both address and data information. To write a command or
command sequence (which includes programming
data to the device and erasing sectors of memory), the
May 8, 2006 25692A2
S H E E T
system must drive AVD# and CE# to VIL, and OE# to
V IH when providing an address to the device, and
drive WE# and CE# to VIL, and OE# to VIH. when writing commands or data.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a word, instead of four.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 7 indicates the address
space that each sector occupies. The device address
space is divided into four banks: Banks A and B contain both 8 Kword boot sectors in addition to 32 Kword
sectors, while Banks C and D contain only 32 Kword
sectors. A “bank address” is the address bits required
to uniquely select a bank. Similarly, a “sector address”
is the address bits required to uniquely select a sector.
Refer to the DC Characteristics table for write mode
current specifications. The AC Characteristics section
contains timing specification tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the V PP input. This function is primarily intended to allow faster manufacturing throughput at the
factory. If the system asserts VID on this input, the device automatically enters the aforementioned Unlock
Bypass mode and uses the higher voltage on the input
to reduce the time required for program operations.
The system would use a two-cycle program command
sequence as required by the Unlock Bypass mode.
Removing VID from the VPP input returns the device to
normal operation.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Functions and Autoselect Command Sequence sections for more
information.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# inputs are both held at VCC ± 0.2 V.
The device requires standard access time (tCE ) for
Am29BDS643G
11
D A T A
S H E E T
read access when the device is in either of these
standby modes, before it is ready to read data.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 12 for the timing diagram.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
Output Disable Mode
ICC3 in the DC Characteristics table represents the
standby current specification.
Hardware Data Protection
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enters
this mode when addresses remain stable for tACC +
60 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard add r es s a c c e s s tim in g s pr ovi d e n ew d a t a w h e n
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
ICC4 in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Input
The RESET# input provides a hardware method of resetting the device to reading array data. When
RESET# is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tr istates all outputs, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.2 V, the device
draws CMOS standby current (I CC4 ). If RESET# is
held at VIL but not within VSS±0.2 V, the standby current will be greater.
RESET# may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from
the Flash memory.
If RESET# is asserted during a program or erase operation, the device requires a time of tREADY (during
Embedded Algorithms) before the device is ready to
read data again. If RESET# is asserted when a program or erase operation is not executing, the reset
operation is completed within a time of tREADY (not
during Embedded Algorithms). The system can read
data tRH after RESET# returns to VIH.
12
When the OE# input is at VIH, output from the device is
d i s a bl e d . T h e o u t p u t s a r e p l a c e d i n t h e h i g h
impedance state.
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 10 for command definitions).
The device offers three types of data protection at the
sector level:
■ The sector lock/unlock command sequence disables or re-enables both program and erase operations in any sector.
■ When WP# is at VIL, the two outermost sectors are
locked.
■ When VPP is at VIL, all sectors are locked.
The following hardware data protection measures prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals
during VCC power-up and power-down transitions, or
from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to reading array data. Subsequent writes are ignored until V CC is greater than
VLKO. The system must provide the proper signals to
the control inputs to prevent unintentional writes when
VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Am29BDS643G
25692A2 May 8, 2006
D A T A
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address
55h any time the device is ready to read array data.
Table 3.
S H E E T
The system can read CFI information at the addresses
given in Tables 3–6. To terminate reading CFI data,
the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 3–6. The
system must write the reset command to return the
device to the autoselect mode.
For further information, please refer to the CFI Specification and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/products/nvd/overv i ew / c f i . h t m l . A l t e r n a t i ve l y, c o n t a c t a n A M D
representative for copies of these documents.
CFI Query Identification String
Addresses
Data
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
May 8, 2006 25692A2
Description
Am29BDS643G
13
D A T A
Table 4.
System Interface String
Addresses
Data
Description
1Bh
0017h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
0019h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
0000h
VPP Min. voltage (00h = no VPP pin present) Refer to 4Dh.
1Eh
0000h
VPP Max. voltage (00h = no VPP pin present) Refer to 4Eh.
1Fh
0003h
Typical timeout per single byte/word write 2N µs
20h
0000h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
0008h
Typical timeout per individual block erase 2N ms
22h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
0005h
Max. timeout for byte/word write 2N times typical
24h
0000h
Max. timeout for buffer write 2N times typical
25h
0004h
Max. timeout per individual block erase 2N times typical
26h
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 5.
14
S H E E T
Device Geometry Definition
Addresses
Data
Description
27h
0017h
Device Size = 2N byte
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0000h
0000h
Max. number of bytes in multi-byte write = 2N
(00h = not supported)
2Ch
0004h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
005Eh
0000h
0000h
0001h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
0003h
0000h
0040h
0000h
Erase Block Region 2 Information
35h
36h
37h
38h
001Eh
0000h
0000h
0001h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
0003h
0000h
0040h
0000h
Erase Block Region 4 Information
Am29BDS643G
25692A2 May 8, 2006
D A T A
Table 6.
S H E E T
Primary Vendor-Specific Extended Query
Addresses
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
0031h
Major version number, ASCII
44h
0033h
Minor version number, ASCII
45h
0000h
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Silicon Revision Number (Bits 7-2)
46h
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h
0000h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
0005h
Sector Protect/Unprotect scheme
05 = 29BDS/N643 mode
4Ah
0066h
Simultaneous Operation
Number of Sectors in Bank 2 (Uniform Bank)
4Bh
0001h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh
00B5h
4Eh
00C5h
4Fh
0001h
0001h = Top/Middle Boot Device,
0002h = Bottom Boot Device, 03h = Top Boot Device
50h
0000h
Program Suspend. 00h = not supported
57h
0004h
Bank Organization: X = Number of banks
58h
0020h
Bank D Region Information. X = Number of sectors in bank
59h
0020h
Bank C Region Information. X = Number of sectors in bank
5Ah
0023h
Bank B Region Information. X = Number of sectors in bank
5Bh
0023h
Bank A Region Information. X = Number of sectors in bank
5Ch
0001h
Process Technology. 00h = 0.23 µm, 01h = 0.17 µm
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
May 8, 2006 25692A2
Am29BDS643G
15
D A T A
Bank D
Table 7.
16
S H E E T
Sector Address Table
Sector
Sector Size
(x16) Address Range
SA0
32 Kwords
000000h—007FFFh
SA1
32 Kwords
008000h—00FFFFh
SA2
32 Kwords
010000h—017FFFh
SA3
32 Kwords
018000h—01FFFFh
SA4
32 Kwords
020000h—027FFFh
SA5
32 Kwords
028000h—02FFFFh
SA6
32 Kwords
030000h—037FFFh
SA7
32 Kwords
038000h—03FFFFh
SA8
32 Kwords
040000h—047FFFh
SA9
32 Kwords
048000h—04FFFFh
SA10
32 Kwords
050000h—057FFFh
SA11
32 Kwords
058000h—05FFFFh
SA12
32 Kwords
060000h—067FFFh
SA13
32 Kwords
068000h—06FFFFh
SA14
32 Kwords
070000h—077FFFh
SA15
32 Kwords
078000h—07FFFFh
SA16
32 Kwords
080000h—087FFFh
SA17
32 Kwords
088000h—08FFFFh
SA18
32 Kwords
090000h—097FFFh
SA19
32 Kwords
098000h—09FFFFh
SA20
32 Kwords
0A0000h—0A7FFFh
SA21
32 Kwords
0A8000h—0AFFFFh
SA22
32 Kwords
0B0000h—0B7FFFh
SA23
32 Kwords
0B8000h—0BFFFFh
SA24
32 Kwords
0C0000h—0C7FFFh
SA25
32 Kwords
0C8000h—0CFFFFh
SA26
32 Kwords
0D0000h—0D7FFFh
SA27
32 Kwords
0D8000h—0DFFFFh
SA28
32 Kwords
0E0000h—0E7FFFh
SA29
32 Kwords
0E8000h—0EFFFFh
SA30
32 Kwords
0F0000h—0F7FFFh
SA31
32 Kwords
0F8000h—0FFFFFh
Am29BDS643G
25692A2 May 8, 2006
D A T A
Bank B
Bank C
Table 7.
May 8, 2006 25692A2
S H E E T
Sector Address Table (Continued)
Sector
Sector Size
(x16) Address Range
SA32
32 Kwords
100000h—107FFFh
SA33
32 Kwords
108000h—10FFFFh
SA34
32 Kwords
110000h—117FFFh
SA35
32 Kwords
118000h—11FFFFh
SA36
32 Kwords
120000h—127FFFh
SA37
32 Kwords
128000h—12FFFFh
SA38
32 Kwords
130000h—137FFFh
SA39
32 Kwords
138000h—13FFFFh
SA40
32 Kwords
140000h—147FFFh
SA41
32 Kwords
148000h—14FFFFh
SA42
32 Kwords
150000h—157FFFh
SA43
32 Kwords
158000h—15FFFFh
SA44
32 Kwords
160000h—167FFFh
SA45
32 Kwords
168000h—16FFFFh
SA46
32 Kwords
170000h—177FFFh
SA47
32 Kwords
178000h—17FFFFh
SA48
32 Kwords
180000h–187FFFh
SA49
32 Kwords
188000h–18FFFFh
SA50
32 Kwords
190000h–197FFFh
SA51
32 Kwords
198000h–19FFFFh
SA52
32 Kwords
1A0000h–1A7FFFh
SA53
32 Kwords
1A8000h–1AFFFFh
SA54
32 Kwords
1B0000h–1B7FFFh
SA55
32 Kwords
1B8000h–1BFFFFh
SA56
32 Kwords
1C0000h–1C7FFFh
SA57
32 Kwords
1C8000h–1CFFFFh
SA58
32 Kwords
1D0000h–1D7FFFh
SA59
32 Kwords
1D8000h–1DFFFFh
SA60
32 Kwords
1E0000h–1E7FFFh
SA61
32 Kwords
1E8000h–1EFFFFh
SA62
32 Kwords
1F0000h–1F7FFFh
SA63
32 Kwords
1F8000h–1FFFFFh
SA64
32 Kwords
200000h–207FFFh
SA65
32 Kwords
208000h–20FFFFh
SA66
32 Kwords
210000h–217FFFh
SA67
32 Kwords
218000h–21FFFFh
SA68
32 Kwords
220000h–227FFFh
SA69
32 Kwords
228000h–22FFFFh
SA70
32 Kwords
230000h–237FFFh
SA71
32 Kwords
238000h–23FFFFh
SA72
32 Kwords
240000h–247FFFh
SA73
32 Kwords
248000h–24FFFFh
SA74
32 Kwords
250000h–257FFFh
SA75
32 Kwords
258000h–25FFFFh
Am29BDS643G
17
D A T A
Bank A
Bank B (continued)
Table 7.
18
S H E E T
Sector Address Table (Continued)
Sector
Sector Size
(x16) Address Range
SA76
32 Kwords
260000h–267FFFh
SA77
32 Kwords
268000h–26FFFFh
SA78
32 Kwords
270000h–277FFFh
SA79
32 Kwords
278000h–27FFFFh
SA80
32 Kwords
280000h–287FFFh
SA81
32 Kwords
288000h–28FFFFh
SA82
32 Kwords
290000h–297FFFh
SA83
32 Kwords
298000h–29FFFFh
SA84
32 Kwords
2A0000h–2A7FFFh
SA85
32 Kwords
2A8000h–2AFFFFh
SA86
32 Kwords
2B0000h–2B7FFFh
SA87
32 Kwords
2B8000h–2BFFFFh
SA88
32 Kwords
2C0000h–2C7FFFh
SA89
32 Kwords
2C8000h–2CFFFFh
SA90
32 Kwords
2D0000h–2D7FFFh
SA91
32 Kwords
2D8000h–2DFFFFh
SA92
32 Kwords
2E0000h–2E7FFFh
SA93
32 Kwords
2E8000h–2EFFFFh
SA94
32 Kwords
2F0000h–2F7FFFh
SA95
8 Kwords
2F8000h–2F9FFFh
SA96
8 Kwords
2FA000h–2FBFFFh
SA97
8 Kwords
2FC000h–2FDFFFh
SA98
8 Kwords
2FE000h–2FFFFFh
SA99
32K words
300000h–307FFFh
SA100
32K words
308000h–30FFFFh
SA101
32K words
310000h–317FFFh
SA102
32K words
318000h–31FFFFh
SA103
32K words
320000h–327FFFh
SA104
32K words
328000h–32FFFFh
SA105
32K words
330000h–337FFFh
SA106
32K words
338000h–33FFFFh
SA107
32K words
340000h–347FFFh
SA108
32K words
348000h–34FFFFh
SA109
32K words
350000h–357FFFh
SA110
32K words
358000h–35FFFFh
SA111
32K words
360000h–367FFFh
SA112
32K words
368000h–36FFFFh
SA113
32K words
370000h–377FFFh
SA114
32K words
378000h–37FFFFh
SA115
32K words
380000h–387FFFh
SA116
32K words
388000h–38FFFFh
Am29BDS643G
25692A2 May 8, 2006
D A T A
Bank A (continued)
Table 7.
May 8, 2006 25692A2
S H E E T
Sector Address Table (Continued)
Sector
Sector Size
(x16) Address Range
SA117
32K words
390000h–397FFFh
SA118
32K words
398000h–39FFFFh
SA119
32K words
3A0000h–3A7FFFh
SA120
32K words
3A8000h–3AFFFFh
SA121
32K words
3B0000h–3B7FFFh
SA122
32K words
3B8000h–3BFFFFh
SA123
32K words
3C0000h–3C7FFFh
SA124
32K words
3C8000h–3CFFFFh
SA125
32K words
3D0000h–3D7FFFh
SA126
32K words
3D8000h–3DFFFFh
SA127
32K words
3E0000h–3E7FFFh
SA128
32K words
3E8000h–3EFFFFh
SA129
32K words
3F0000h–3F7FFFh
SA130
8K words
3F8000h–3F9FFFh
SA131
8K words
3FA000h–3FBFFFh
SA132
8K words
3FC000h–3FDFFFh
SA133
8K words
3FE000h–3FFFFFh
Am29BDS643G
19
D A T A
S H E E T
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 10 defines the valid register
command sequences. Writing incorrect address and
data values or writing them in the improper sequence
resets the device to reading array data.
All addresses are latched on the rising edge of AVD#.
All data is latched on the rising edge of WE#. Refer to
the AC Characteristics section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data in asynchronous mode. Each bank is
ready to read array data after completing an Embedded
Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-suspend-read mode, after which the system can read data
from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend
mode, the system may once again read array data with
the same exception. See the Erase Suspend/Erase
Resume Commands section for more information.
Table 8.
The system must issue the reset command to return a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase operation,
or if the bank is in the autoselect mode. See the next
section, Reset Command, for more information.
S e e a l s o R e q u i r e m e n t s fo r A s y n c h r o n o u s
Read Operation (Non-Burst) and Requirements for
Synchronous (Burst) Read Operation in the Device
Bus Operations section for more information. The
Asynchronous Read and Synchronous/Burst Read
tables provide the read parameters, and Figures 9 and
11 show the timings.
Set Configuration Register Command Sequence
The configuration register command sequence
instructs the device to set a particular number of clock
cycles for the initial access in burst mode. The number
of wait states that should be programmed into the
device is directly related to the clock frequency. The
first two cycles of the command sequence are for
unlock purposes. On the third cycle, the system should
write C0h to the address associated with the intended
wait state setting (see Table 8). Address bits A16–A12
determine the setting. Note that addresses A19–A17
are shown as “0” but are actually don’t care.
Burst Modes
Third Cycle Addresses for Wait States
Wait States
0
1
2
3
4
5
Clock Cycles
2
3
4
5
6
7
Continuous
00555h
01555h
02555h
03555h
04555h
05555h
8-word Linear
08555h
09555h
0A555h
0B555h
0C555h
0D555h
16-word Linear
10555h
11555h
12555h
13555h
14555h
15555h
32-word Linear
18555h
19555h
1A555h
1B555h
1C555h
1D555h
Burst
Mode
Note: The burst mode is set in the third cycle of the Set Wait State command sequence.
Upon power up, the device defaults to the maximum
seven cycle wait state setting. It is recommended that
the wait state command sequence be written, even if
the default wait state value is desired, to ensure the
device is set as expected. A hardware reset will set the
wait state to the default setting.
Handshaking Feature
The host system should set address bits A16–A12 to
“00010” for a clock frequency of 40 MHz or to “00011”
for a clock frequency of 54 or 66 MHz, assuming continuous burst is desired in both cases.
Table 9 describes the typical number of clock cycles
(wait states) for various conditions.
20
Am29BDS643G
25692A2 May 8, 2006
D A T A
Table 9.
Reset Command
Wait States for Handshaking
Typical No. of Clock
Cycles after AVD# Low
Conditions at Address
S H E E T
40 MHz
54/66 MHz
Initial address is even
4
5
Initial address is odd
5
6
Initial address is even,
and is at boundary crossing*
6
7
Initial address is odd,
and is at boundary crossing*
7
8
* In the 8-, 16- and 32-word burst read modes, the address
pointer does not cross 64-word boundaries (addresses
which are multiples of 3Eh).
The autoselect function allows the host system to
determine whether the flash device is enabled for
h an d s h ak i n g . S e e th e “ Au t os e l e c t C om m a n d
Sequence” section for more information.
Enable PS (Power Saving) Mode
Command Sequence
The Enable PS (Power Saving) Mode command
sequence is required to set the device to the PS mode.
On power up, the Power Saving mode is disabled. The
command sequence consists of two unlock cycles followed by a command cycle in which the address and
data should 555h/70h, respectively. The PS mode
remains enabled until the device is hardware reset
(either device is powered down or RESET# is asserted
low).
Writing the reset command resets the banks to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the bank to which
the system was writing to the read mode. Once erasure
begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the bank to
which the system was writing to the read mode. If the
program command sequence is written to a bank that
is in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read
mode. Once programming begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to the read mode. If a bank entered
the autoselect mode while in the Erase Suspend mode,
writing the reset command returns that bank to the
erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to the
read mode (or erase-suspend-read mode if that bank
was in Erase Suspend).
Sector Lock/Unlock Command Sequence
Autoselect Command Sequence
The sector lock/unlock command sequence allows the
system to determine which sectors are protected from
accidental writes. When the device is first powered up,
all sectors are locked. To unlock a sector, the system
must write the sector lock/unlock command sequence.
Two cycles are first written: addresses are don’t care
and data is 60h. During the third cycle, the sector
address (SLA) and unlock command (60h) is written,
while specifying with address A6 whether that sector
should be locked (A6 = VIL) or unlocked (A6 = VIH).
After the third cycle, the system can continue to lock or
unlock additional cycles, or exit the sequence by writing
F0h (reset command).
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
Table 10 shows the address and data requirements.
The autoselect command sequence may be written to
an address within a bank that is either in the read or
erase-suspend-read mode. The autoselect command
may not be written while the device is actively programming or erasing in the other bank.
Note that the last two outermost boot sectors can be
locked by taking the WP# signal to VIL. Also, if VPP is at
VIL all sectors are locked; if the VPP input is at VPP, all
sectors are unlocked.
May 8, 2006 25692A2
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the bank address and the
autoselect command. The bank then enters the
autoselect mode. The system may read at any address
within the same bank any number of times without initiating another autoselect command sequence. The following table describes the address requirements for
the various autoselect functions, and the resulting data.
BA represents the bank address, and SA represents
Am29BDS643G
21
D A T A
the sector address. The device ID is read in three
cycles.
Description
Address
Read Data
Manufacturer ID
(BA) + 00h
0001h
Device ID, Word 1
(BA) + 01h
227Eh
Device ID, Word 2
(BA) + 0Eh
2202h
Device ID, Word 3
(BA) + 0Fh
2200h
Sector Block
Lock/Unlock
(SA) + 02h
0001 (locked),
0000 (unlocked)
Handshaking
(BA) + 03h
43h
from “0” back to a “1.” Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and
DQ6 status bit to indicate the operation was successful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a “0”
to a “1.”
Unlock Bypass Command Sequence
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the
bank was previously in Erase Suspend).
Program Command Sequence
Programming is a four-bus-cycle operation. The
program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 10 shows the address
and data requirements for the program command
sequence.
When the Embedded Program algorithm is complete,
that bank then returns to the read mode and addresses
are no longer latched. The system can determine the
status of the program operation by monitoring DQ7 or
DQ6/DQ2. Refer to the Write Operation Status section
for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should be
reinitiated once that bank has returned to the read
mode, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
22
S H E E T
The unlock bypass feature allows the system to primarily program to a bank faster than using the standard
program command sequence. The unlock bypass
command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. That
bank then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total programming time. Table 10 shows the requirements for the
unlock bypass command sequences.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
bank address and the data 90h. The second cycle
need only contain the data 00h. The bank then returns
to the read mode.
The device offers accelerated program operations
through the VPP input. When the system asserts VPP
on this input, the device automatically enters the
Unlock Bypass mode. The system may then write the
t wo - c y c l e U n l o ck B y p a s s p r o g ra m c o m m a n d
sequence. The device uses the higher voltage on the
VPP input to accelerate the operation.
Figure 1 illustrates the algorithm for the program operation. Refer to the Erase/Program Operations table in
the AC Characteristics section for parameters, and
Figure 13 for timing diagrams.
Am29BDS643G
25692A2 May 8, 2006
D A T A
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset
immediately terminates the erase operation. If that
occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading array
data, to ensure data integrity.
START
The host system may also initiate the chip erase
command sequence while the device is in the unlock
bypass mode. The command sequence is two cycles
cycles in length instead of six cycles. See Table 10 for
details on the unlock bypass command sequences.
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
Figure 2 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations table in
the AC Characteristics section for parameters, and
Figure 14 section for timing diagrams.
No
No
Last Address?
Yes
Programming
Completed
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
Note: See Table 10 for program command sequence.
Figure 1.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations. Table 10
shows the address and data requirements for the chip
erase command sequence.
When the Embedded Erase algorithm is complete,
that bank returns to the read mode and addresses are
no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2.
Refer to the Write Operation Status section for information on these status bits.
May 8, 2006 25692A2
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock cycles are written, and are then followed by the address of the sector to be erased, and
the sector erase command. Table 10 shows the
address and data requirements for the sector erase
command sequence.
Yes
Increment Address
S H E E T
After the command sequence is written, a sector erase
time-out of no less than 50 µs occurs. During the
time-out period, additional sector addresses and sector
erase commands may be written. Loading the sector
erase buffer may be done in any sequence, and the
number of sectors may be from one sector to all sectors. The time between these additional cycles must be
less than 50 µs, otherwise erasure may begin. Any
sector erase address and command following the
exceeded time-out may or may not be accepted. It is
recommended that processor interrupts be disabled
during this time to ensure all commands are accepted.
The interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
Sector Erase or Erase Suspend during the time-out
period resets that bank to the read mode. The
system must rewrite the command sequence and any
additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command
sequence.
Am29BDS643G
23
D A T A
When the Embedded Erase algorithm is complete, the
bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded Erase
operation is in progress, the system can read data from
the non-erasing bank. The system can determine the
status of the erase operation by reading DQ7 or DQ6/
DQ2 in the erasing bank. Refer to the Write Operation
Status section for information on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. However, note that a hardware reset
immediately terminates the erase operation. If that
occurs, the sector erase command sequence should
be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
The host system may also initiate the sector erase
command sequence while the device is in the unlock
bypass mode. The command sequence is four cycles
cycles in length instead of six cycles.
Figure 2 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations table in
the AC Characteristics section for parameters, and
Figure 14 section for timing diagrams.
S H E E T
within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or
DQ6 and DQ2 together, to determine if a sector is
actively erasing or is erase-suspended. Refer to the
Write Operation Status section for information on these
status bits.
After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard program operation. Refer to the
Write Operation Status section for more information.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Functions and Autoselect Command
Sequence sections for details.
To resume the sector erase operation, the system must
write the Erase Resume command. The bank address
of the erase-suspended bank is required when writing
this command. Further writes of the Resume command
are ignored. Another Erase Suspend command can be
written after the chip has resumed erasing.
Erase Suspend/Erase Resume
Commands
START
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read
data from, program data to, any sector not selected for
erasure. The system may also lock or unlock any sector while the erase operation is suspended. The syst e m mu s t n o t w r i t e t h e s e c t o r l o ck / u n l o ck
command to sectors selected for erasure. The
bank address is required when writing this command.
This command is valid only during the sector erase operation, including the minimum 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program
algorithm.
When the Erase Suspend command is written during
the sector erase operation, the device requires a
maximum of 20 µs to suspend the erase operation.
However, when the Erase Suspend command is written
during the sector erase time-out, the device immediately terminates the time-out period and suspends the
erase operation.
After the erase operation has been suspended, the
bank enters the erase-suspend-read mode. The
system can read data from or program data to any
sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) The system
may also lock or unlock any sector while in the
erase-suspend-read mode. Reading at any address
24
Write Erase
Command Sequence
Data Poll
from System
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 10 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Am29BDS643G
Figure 2.
Erase Operation
25692A2 May 8, 2006
D A T A
Command Sequence
(Note 1)
Cycles
Table 10.
S H E E T
Command Definitions
Bus Cycles (Notes 2–5)
First
Second
Addr Data Addr Data
Third
Fourth
Fifth
Addr
Data
Addr
Data
1
RA
RD
Reset (Note 7)
1
XXX
F0
Manufacturer ID
4
555
AA
2AA
55
(BA)555
90
(BA)X00
0001
Device ID
6
555
AA
2AA
55
(BA)555
90
(BA)X01
227E
Sector Lock Verify (Note 9)
4
555
AA
2AA
55
(SA)555
90
(SA)X02 0000 0001
Handshaking Option (Note 10)
4
555
AA
2AA
55
(BA)555
90
(BA)X03 0042 0043
Autoselect (Note 8)
Asynchronous Read (Note 6)
Program
4
555
AA
2AA
55
555
A0
Unlock Bypass
3
555
AA
2AA
55
555
20
Unlock Bypass Program (Note 11)
2
XXX
A0
PA
PD
Unlock Bypass Reset (Note 12)
2
BA
90
XXX
00
Chip Erase
6
555
AA
2AA
55
555
Sector Erase
6
555
AA
2AA
55
555
Erase Suspend (Note 13)
1
BA
B0
Erase Resume (Note 14)
1
BA
30
Sector Lock/Unlock
3
XXX
60
XXX
60
SLA
60
Set Configuration Register (Note 15)
3
555
AA
2AA
55
(CR)555
C0
Enable PS Mode
3
555
AA
2AA
55
555
70
CFI Query (Note 16)
1
55
98
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
Notes:
1. See Table 1 for description of bus operations.
All values are in hexadecimal.
3.
Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4.
Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
5.
Unless otherwise noted, address bits A21–A12 are don’t cares.
6.
No unlock or command cycles required when bank is reading
array data.
7.
The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information).
9.
(BA)
X0E
2202
(BA)
X0F
2200
PA
Data
80
555
AA
2AA
55
555
10
80
555
AA
2AA
55
SA
30
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A21–A12 uniquely select any sector.
BA = Address of the bank (A21, A20) that is being switched to
autoselect mode, is in bypass mode, or is being erased.
SLA = Address of the sector to be locked. Set sector address (SA) and
either A6 = 1 for unlocked or A6 = 0 for locked.
CR = Configuration Register set by address bits A16–A12.
10. The data is 0043h for handshaking enabled.
2.
8.
Sixth
Addr Data Addr Data
The fourth cycle of the autoselect command sequence is a read
cycle. The system must read device IDs across the 4th, 5th, and
6th cycles, The system must provide the bank address. See the
Autoselect Command Sequence section for more information.
11. The Unlock Bypass command sequence is required prior to this
command sequence.
12. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass mode.
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
14. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
15. The addresses in the third cycle must contain, on A12–A16, the
additional wait counts to be set. See “Set Configuration Register
Command Sequence”.
16. Command is valid when device is ready to read array data or
when device is in autoselect moe.
The data is 0000h for an unlocked sector and 0001h for a locked
sector
May 8, 2006 25692A2
Am29BDS643G
25
D A T A
S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the status of a
program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 12 and the following subsections describe the
function of these bits. DQ7 and DQ6 each offers a method
for determining whether a program or erase operation is
complete or in progress.
invalid. Valid data on DQ0–DQ7 will appear on successive read cycles.
Table 12 shows the outputs for Data# Polling on DQ7.
Figure 3 shows the Data# Polling algorithm. Figure 16
in the AC Characteristics section shows the Data#
Polling timing diagram.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is
in Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then that bank returns to the read
mode.
START
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
No
No
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status information on DQ7.
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data#
Polling on DQ7 is active for approximately 100 µs, then
the bank returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the
selected sectors that are protected. However, if the
system reads DQ7 at an address within a protected
sector, the status may not be valid.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has completed the program or erase operation and DQ7 has
valid data, the data outputs on DQ0–DQ6 may be still
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 3.
26
Yes
Am29BDS643G
Data# Polling Algorithm
25692A2 May 8, 2006
D A T A
RDY: Ready
The RDY is a dedicated output that indicates (when at
logic low) the system should wait until RDY returns high
before expecting the next word of data.
S H E E T
See the following for additional information: Figure 4
(toggle bit flowchart), DQ6: Toggle Bit I (description),
Figure 17 (toggle bit timing diagram), and Table 11
(compares DQ2 and DQ6).
RDY functions only while reading data in burst mode.
The following conditions cause the RDY output to be
low: during the initial access (in burst mode); after the
boundary that occurs every 64 words beginning with
the 63rd address, 3Eh; and when the clock frequency
is less than 6 MHz (in which case RDY is low every third
clock). The RDY pin will also switch during status reads
if there is a clock signal at the CLK input. If RDY goes
low, it indicates that the status data is not yet valid and
that the system should wait until RDY returns high.
START
Read Byte
(DQ0-DQ7)
Address = VA
Read Byte
(DQ0-DQ7)
Address = VA
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address in the
same bank, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
DQ6 = Toggle?
Yes
No
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle. Note that OE# must be low during
toggle bit status reads. When the operation is complete, DQ6 stops toggling.
DQ5 = 1?
Yes
Read Byte Twice
(DQ 0-DQ7)
Adrdess = VA
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles
for approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase
Suspend mode, DQ6 stops toggling. However, the
system must also use DQ2 to determine which sectors
are erasing or erase-suspended. Alternatively, the
system can use DQ7 (see the subsection on DQ7:
Data# Polling).
No
DQ6 = Toggle?
No
Yes
FAIL
PASS
Note: The system should recheck the toggle bit even if DQ5
= “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 μs after the program
command sequence is written, then returns to reading
array data.
Figure 4.
Toggle Bit Algorithm
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
May 8, 2006 25692A2
Am29BDS643G
27
D A T A
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for erasure. Note that OE# must be low during toggle bit
status reads. But DQ2 cannot distinguish whether the
S H E E T
sector is actively erasing or is erase-suspended. DQ6,
by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information. Refer to Table 12 to compare outputs for DQ2 and
DQ6.
See the following for additional information: Figure 4
(toggle bit flowchart), DQ6: Toggle Bit I (description),
Figure 17 (toggle bit timing diagram), and Table 11
(compares DQ2 and DQ6).
Table 11. DQ6 and DQ2 Indications
If device is
and the system reads
then DQ6
and DQ2
programming,
at any address,
toggles,
does not toggle.
at an address within a sector
selected for erasure,
toggles,
also toggles.
at an address within sectors not
selected for erasure,
toggles,
does not toggle.
at an address within a sector
selected for erasure,
does not toggle,
toggles.
at an address within sectors not
selected for erasure,
returns array data,
returns array data. The system can read
from any sector not selected for erasure.
at any address,
toggles,
is not applicable.
actively erasing,
erase suspended,
programming in
erase suspend
Reading Toggle Bits DQ6/DQ2
Refer to Figure 4 for the following discussion. Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not completed the operation successfully,
28
and the system must write the reset command to return
to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 4).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1,” indicating that
the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
Am29BDS643G
25692A2 May 8, 2006
D A T A
S H E E T
halts the operation, and when the timing limit has been
exceeded, DQ5 produces a “1.”
See also the Sector Erase Command Sequence section.
Under both these conditions, the system must write
the reset command to return to the read mode (or to
the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all
further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the
system software should check the status of DQ3 prior
to and following each subsequent sector erase command. If DQ3 is high on the second status check, the
last command might not have been accepted.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sectors
are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out period is complete, DQ3 switches
from a “0” to a “1.” If the time between additional sector
erase commands from the system can be assumed to
be less than 50 µs, the system need not monitor DQ3.
Table 12.
Standard
Mode
Erase
Suspend
Mode
Table 12 shows the status of DQ3 relative to the other
status bits.
Write Operation Status
Status
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Erase-Suspend- Suspended Sector
Read (Note 4)
Non-Erase Suspended
Sector
Erase-Suspend-Program
DQ7
(Note 2)
DQ7#
0
DQ6
Toggle
Toggle
DQ5
(Note 1)
0
0
DQ3
N/A
1
DQ2
(Note 2)
No toggle
Toggle
1
No toggle
0
N/A
Toggle
Data
Data
Data
Data
Data
DQ7#
Toggle
0
N/A
N/A
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
4. The system may read either asynchronously or synchronously (burst) while in erase suspend. RDY will function exactly as in
non-erase-suspended mode.
May 8, 2006 25692A2
Am29BDS643G
29
D A T A
S H E E T
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground,
All Inputs and I/Os
except VPP (Note 1) . . . . . . . . . –0.5 V to VCC + 0.5 V
20 ns
20 ns
+0.9 V
–2.0 V
VCC (Note 1) . . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V
20 ns
VPP (Note 2) . . . . . . . . . . . . . . . . . –0.5 V to +12.5 V
Output Short Circuit Current (Note 3) . . . . . . 100 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During
voltage transitions, input at I/Os may undershoot VSS to
–2.0 V for periods of up to 20 ns during voltage transitions
inputs might overshooot to VCC +0.5 V for periods up to
20 ns. See Figure 5. Maximum DC voltage on output and
I/Os is VCC + 0.5 V. During voltage transitions outputs
may overshoot to VCC + 2.0 V for periods up to 20 ns. See
Figure 6.
2. Minimum DC input voltage on VPP is –0.5 V. During
voltage transitions, VPP may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 5. Maximum DC input
voltage on VPP is +12.5 V which may overshoot to +13.5
V for periods up to 20 ns.
Figure 5. Maximum Negative
Overshoot Waveform
20 ns
VCC
+2.0 V
2.0 V
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
4. Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not
implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
20 ns
20 ns
Figure 6. Maximum Positive
Overshoot Waveform
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
VCC Supply Voltages
VCC min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.7 V
VCC max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.9 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
30
Am29BDS643G
25692A2 May 8, 2006
D A T A
S H E E T
DC CHARACTERISTICS
CMOS Compatible
Parameter Description
Test Conditions (Note 1)
Min
Typ
Max
Unit
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCCmax
±1
µA
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCCmax
±1
µA
ICCB
VCC Active Burst Read Current
(Note 6)
CE# = VIL, OE# = VIL
25
30
mA
VCC Active Asynchronous Read
Current
5 MHz
12
16
mA
ICC1
CE# = VIL, OE# = VIH
1 MHz
3.5
5
mA
ICC2
VCC Active Write Current (Note 3)
CE# = VIL, OE# = VIH, VPP = VIH
15
40
mA
ICC3
VCC Standby Current (Note 4)
CE# = VIH, RESET# = VIH
0.2
10
µA
ICC4
VCC Reset Current
RESET# = VIL, CLK = VIL
0.2
10
µA
ICC5
VCC Active Current
(Read While Write)
CE# = VIL, OE# = VIL
40
60
mA
Accelerated Program Current
(Note 5)
CE# = VIL, OE# = VIH,
VPP = 12.0 ± 0.5 V
VPP
7
15
mA
IPP
VCC
5
10
mA
VIL
Input Low Voltage
–0.5
0.4
V
VIH
Input High Voltage
VCC – 0.4
VCC + 0.2
V
VOL
Output Low Voltage
IOL = 100 µA, VCC = VCC min
0.1
V
VOH
Output High Voltage
IOH = –100 µA, VCC = VCC min
VID
Voltage for Accelerated Program
11.5
12.5
V
Low VCC Lock-out Voltage
1.0
1.4
V
VLKO
VCC – 0.1
V
Note:
1. Maximum ICC specifications are tested with VCC = VCCmax.
2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Device enters automatic sleep mode when addresses are stable for tACC + 60 ns. Typical sleep mode current is equal to ICC3.
5. Total current during accelerated programming is the sum of VPP and VCC currents.
6. Specifications assume 8 I/Os switching.
May 8, 2006 25692A2
Am29BDS643G
31
D A T A
S H E E T
TEST CONDITIONS
Table 13.
Device
Under
Test
Test Condition
All Speeds
Unit
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
5
ns
0.0–VCC
V
Input timing measurement
reference levels
VCC/2
V
Output timing measurement
reference levels
VCC/2
V
Input Pulse Levels
CL
Figure 7.
Test Specifications
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
SWITCHING WAVEFORMS
VCC
Input
VCC/2
Measurement Level
VCC/2
Output
0.0 V
Figure 8. Input Waveforms and
Measurement Levels
32
Am29BDS643G
25692A2 May 8, 2006
D A T A
S H E E T
AC CHARACTERISTICS
Synchronous/Burst Read
Parameter
JEDEC
Standard
7G
7M
5K
(40 MHz) (54 MHz) (66 MHz)
Description
Unit
tIACC
Initial Access Time
Max
95
87.5
71
ns
tBACC
Burst Access Time Valid Clock to Output Delay
Max
20
13.5
11
ns
tAVDS
AVD# Setup Time to CLK
Min
5
4
ns
tAVDH
AVD# Hold Time from CLK
Min
7
6
ns
tAVDO
AVD# High to OE# Low
Min
0
0
ns
tACS
Address Setup Time to CLK
Min
5
4
ns
tACH
Address Hold Time from CLK
Min
7
6
ns
tBDH
Data Hold Time from Next Clock Cycle
Max
4
4
ns
tOE
Output Enable to Data, PS, or RDY Valid
Max
11
ns
tCEZ
Chip Enable to High Z
Max
10
10
ns
tOEZ
Output Enable to High Z
Max
10
10
ns
tCES
CE# Setup Time to CLK
Min
5
4
ns
tRDYS
RDY Setup Time to CLK
Min
5
4
ns
tRACC
Ready access time from CLK
Max
11
ns
5 cycles for initial access shown.
Programmable wait state function is set to 03h.
tCES
18.5 ns typ. (54 MHz)
20
13.5
20
1 cycle
wait state
when PS
enabled
13.5
tCEZ
CE#
CLK
tAVDS
AVD#
tAVDH
tAVDO
tACS
A16:
A21
tBDH
Aa
tBACC
tACH
A/DQ0:
A/DQ15
Hi-Z
Aa
tIACC
Da
Da + 1
Da + 2
Da + n
tOEZ
OE#
tRACC
tOE
RDY
Hi-Z
Hi-Z
tRYDS
Notes:
1. Figure shows total number of clock set to five.
2. Figure shows that PS (power saving mode) has been enabled; one additional wait state occurs during initial data Da. Latency
is not present if PS is not enabled.
3. If any burst address occurs at a 64-word boundary, two additional clock cycles are inserted, and is indicated by RDY.
Figure 9.
May 8, 2006 25692A2
Burst Mode Read (66 and 54 MHz)
Am29BDS643G
33
D A T A
S H E E T
AC CHARACTERISTICS
4 cycles for initial access shown.
Programmable wait state function is set to 02h.
tCES
25 ns typ.
1 cycle
wait state
when PS
enabled
tCEZ
CE#
CLK
tAVDS
AVD#
tAVDH
tAVDO
tACS
A16:
A21
tBDH
Aa
tBACC
tACH
A/DQ0:
A/DQ15
Hi-Z
Aa
tIACC
Da
Da + 1
Da + 2
Da + n
tOEZ
OE#
tRACC
tOE
RDY
Hi-Z
Hi-Z
tRYDS
Notes:
1. Figure shows total number of clock cycles set to four.
2. Figure shows that PS (power saving mode) has been enabled; one additional wait state occurs during initial data Da. Latency
is not present if PS is not enabled.
3. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and are indicated by RDY.
Figure 10. Burst Mode Read (40 MHz)
34
Am29BDS643G
25692A2 May 8, 2006
D A T A
S H E E T
AC CHARACTERISTICS
Asynchronous Read
Parameter
JEDEC
Standard
Description
7G/7M
5K
Unit
tCE
Access Time from CE# Low
Max
70
55
ns
tACC
Asynchronous Access Time
Max
70
55
ns
tAVDP
AVD# Low Time
Min
12
11
ns
tAAVDS
Address Setup Time to Rising Edge of AVD
Min
5
4
ns
tAAVDH
Address Hold Time from Rising Edge of AVD
Min
7
6
ns
tOE
Output Enable to Output Valid
Max
20
11
ns
tOEH
Output Enable Hold Time
tOEZ
Output Enable to High Z (See Note)
Read
Min
0
ns
Toggle and Data# Polling
Min
10
ns
Max
10
ns
Note: Not 100% tested.
CE#
tOE
OE#
tOEH
WE#
tCE
A/DQ0:
A/DQ15
tOEZ
RA
Valid RD
tACC
RA
A16-A21
tAAVDH
AVD#
tAVDP
tAAVDS
Note: RA = Read Address, RD = Read Data.
Figure 11.
May 8, 2006 25692A2
Asynchronous Mode Read
Am29BDS643G
35
D A T A
S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tReadyw
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
Max
20
μs
tReady
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
Reset High Time Before Read (See Note)
Min
200
ns
tRPD
RESET# Low to Standby Mode
Min
20
μs
Note: Not 100% tested.
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
CE#, OE#
tReadyw
RESET#
tRP
Figure 12.
36
Reset Timings
Am29BDS643G
25692A2 May 8, 2006
D A T A
S H E E T
AC CHARACTERISTICS
Erase/Program Operations
Parameter
JEDEC
Standard
Description
7G/7M
5K
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
80
45
ns
tAVWL
tAS
Address Setup Time
Min
5
4
ns
tWLAX
tAH
Address Hold Time
Min
7
6
ns
tAVDP
AVD# Low Time
Min
12
11
ns
tDVWH
tDS
Data Setup Time
Min
45
25
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tGHWL
tGHWL
Read Recovery Time Before Write
Typ
0
ns
tELWL
tCS
CE# Setup Time
Typ
0
ns
tWHEH
tCH
CE# Hold Time
Typ
0
ns
tWLWH
tWP/tWRL
Write Pulse Width
Typ
50
25
ns
tWHWL
tWPH
Write Pulse Width High
Typ
30
20
ns
tSR/W
Latency Between Read and Write Operations
Min
0
ns
tWHWH1
tWHWH1
Programming Operation (Note 2)
Typ
11.5
µs
tWHWH1
tWHWH1
Accelerated Programming Operation (Note 2)
Typ
4
µs
tWHWH2
tWHWH2
Sector Erase Operation (Notes 2, 3)
Typ
0.4
sec
tVPP
VPP Rise and Fall Time
Min
500
ns
tVPS
VPP Setup Time (During Accelerated Programming)
Min
1
µs
tVCS
VCC Setup Time
Min
50
µs
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
3. Does not include the preprogramming time.
May 8, 2006 25692A2
Am29BDS643G
37
D A T A
S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data
tAS
AVD
tAH
tAVDP
VA
PA
A16:A21
A/DQ0:
A/DQ15
555h
PA
A0h
VA
PD
VA
In
Progress
VA
Complete
tDS
tDH
CE#
tCH
OE#
tWP
WE#
tCS
tWHWH1
tWPH
tWC
VIH
CLK
VIL
tVCS
VCC
PS
PS in
valid only when PS mode is enabled
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A16–A21 are don’t care during command sequence unlock cycles.
Figure 13.
38
Program Operation Timings
Am29BDS643G
25692A2 May 8, 2006
D A T A
S H E E T
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
tAS
AVD
tAH
tAVDP
VA
SA
A16:A21
555h for
chip erase
A/DQ0:
A/DQ15
2AAh
SA
55h
VA
10h for
chip erase
VA
30h
In
Progress
VA
Complete
tDS
tDH
CE#
tCH
OE#
tWP
WE#
tCS
tWHWH2
tWPH
tWC
VIH
CLK
VIL
tVCS
VCC
Notes:
1. SA is the sector address for Sector Erase.
2. Address bits A16–A21 are don’t cares during unlock cycles in the command sequence.
Figure 14. Chip/Sector Erase Operations
May 8, 2006 25692A2
Am29BDS643G
39
D A T A
S H E E T
AC CHARACTERISTICS
CE#
AVD#
WE#
A16:A21
PA
A/DQ0:
A/DQ15
Don't Care
CE#
VPP
A0h
PA
PD
Don't Care
tVPS
1 μs
VID
tVPP
VIL or VIH
Notes:
1. VPP can be left high for subsequent programming pulses.
2. Use setup and hold times from conventional program operation.
Figure 15.
40
Accelerated Unlock Bypass Programming Timing
Am29BDS643G
25692A2 May 8, 2006
D A T A
S H E E T
AC CHARACTERISTICS
AVD
tCEZ
tCE
CE#
tCH
tOEZ
tOE
OE#
tOEH
WE#
tACC
A16:A21
VA
A/DQ0:
A/DQ15
VA
VA
Status Data
VA
Status Data
Notes:
1. All status reads are asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete,
and Data# Polling will output true data.
Figure 16.
Data# Polling Timings (During Embedded Algorithm)
AVD
tCEZ
tCE
CE#
tCH
tOEZ
tOE
OE#
tOEH
WE#
tACC
A16:A21
VA
A/DQ0:
A/DQ15
VA
VA
Status Data
VA
Status Data
Notes:
1. All status reads are asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete,
the toggle bits will stop toggling.
Figure 17.
May 8, 2006 25692A2
Toggle Bit Timings (During Embedded Algorithm)
Am29BDS643G
41
D A T A
S H E E T
AC CHARACTERISTICS
Address wraps back to beginning of address group.
Initial Access
CLK
39
Address (hex)
39
A/DQ0:
A/DQ15
3A
D0
D1
3B
3C
D2
D3
3D
3E
D4
3F
D5
38
D6
D7
VIH
AVD#
OE#,
CE#
VIL
VIH
VIL
Note: 8-word linear burst mode shown. 16- and 32-word linear burst read modes behave similarly.
Figure 18. 8-, 16-, and 32-Word Linear Burst
Address Wrap Around
Address boundary occurs every 64 words, beginning at address
00003Eh: 00007Eh, 0000BEh, etc. Address 000000h is also a boundary crossing.
C59
C60
C61
C62
C62
C62
C63
C64
C65
C66
3B
3C
3D
3E
3E
3E
3F
40
41
42
CLK
Address (hex)
AVD#
(stays high)
tRACC
RDY
A/DQ0:
A/DQ15
OE#,
CE#
latency
D59
D60
D61
D62
D63
D64
D65
D66
(stays low)
Note: Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
Figure 19.
42
Latency with Boundary Crossing (54 MHz and 66 MHz)
Am29BDS643G
25692A2 May 8, 2006
D A T A
S H E E T
AC CHARACTERISTICS
AVD# low with clock
present enables
burst read mode
device is programmable from 2 to 7 total cycles
during initial access (here, programmable wait state
function is set to 04h; 6 cycles total)
1 additional
wait state to
indicate PS
is enabled
2 additional
wait states if
address is
at boundary
PS high if data is inverted,
low if data is not inverted
CLK
AVD#
RDY
PS
A/DQ0:
A/DQ15
Address
A16:A21
Address
PS
High-Z
boundary
latency
D0
High-Z
D1
D2
PS1
PS2
tOE
OE#
Note: Devices should be programmed with wait states as discussed in the “Programmable Wait State” section on page 10.
Figure 20.
Initial Access with Power Saving (PS) Function and Address Boundary Latency
CE#
A/DQ
Addresses
D0
D1
D2
tIACC2
AVD#
tAVDSM
CLK
OE#
RDY
High-Z
Note: If tAVDSM > 1 CLK cycle, wait state usage is reduced. Figure shows 40 MHz clock, handshaking enabled. Wait state usage
is 4 clock cycles instead of 5. Note that tAVDSM must be less than 76 µs for burst operation to begin.
Figure 21.
May 8, 2006 25692A2
Example of Extended Valid Address Reducing Wait State Usage
Am29BDS643G
43
D A T A
S H E E T
AC CHARACTERISTICS
Last Cycle in
Program or
Sector Erase
Command Sequence
Read status (at least two cycles) in same bank
and/or array data from other bank
tWC
tRC
Begin another
write or program
command sequence
tRC
tWC
CE#
OE#
tOE
tOEH
tGHWL
WE#
tWPH
tWP
tDS
tOEZ
tACC
tOEH
tDH
A/DQ0:
A/DQ15
PA/SA
PD/30h
RA
RD
RA
RD
555h
AAh
tSR/W
A16:
A21
PA/SA
RA
RA
tAS
AVD#
tAH
Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while checking
the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure valid information.
Figure 22. Back-to-Back Read/Write Cycle Timings
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D A T A
S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
32 Kword
0.4
5
8 Kword
0.4
5
Unit
Sector Erase Time
s
Chip Erase Time
Word Programming Time
54
Comments
Excludes 00h programming
prior to erasure (Note 4)
s
11.5
210
µs
Accelerated Word Programming Time
4
120
µs
Chip Programming Time (Note 3)
48
144
s
Accelerated Chip Programming Time
16
48
s
Excludes system level
overhead (Note 5)
Excludes system level
overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 1.8 V VCC, 1 million cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 1.8 V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 10 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1 million cycles.
DATA RETENTION
Parameter
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Minimum Pattern Data Retention Time
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45
D A T A
S H E E T
PHYSICAL DIMENSIONS*
VDA044—44-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 9.2 x 8.0 mm Package
A
D
+0.20
1.00 -0.50
D1
A1 CORNER
A1 ID
+0.20
1.00 -0.50
0.50 REF
0.50 REF
10 9 8 7 6 5 4 3 2 1
NF1
NF2
e
A
B
C
D
E
SE
1.00
7
NF3
NF4
1.00
B
TOP VIEW
A2
A
E1
φb
0.10 C
SD 7
6
φ0.05 M C
φ0.15 M C A B
BOTTOM VIEW
A1
SIDE VIEW
SEATING PLANE C
0.08 C
NOTES UNLESS OTHERWISE SPECIFIED:
PACKAGE
JEDEC
SYMBOL
A
A1
A2
VDA 044
N/A
9.20 mm x 8.00 mm
PACKAGE
MIN. NOM. MAX.
NOTE
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JESD 95-1, SPP-010
(EXCEPT AS NOTED).
-
1.00
0.20
-
-
OVERALL THICKNESS
BALL HEIGHT
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
0.78
BODY THICKNESS
5.
SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D"
DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE
IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER
BALLS.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM Z .
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER
OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D
OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000.
0.64
-
BODY SIZE
E
8.00 BSC.
9.20 BSC.
D1
4.50 BSC.
E1
1.50 BSC.
10
ROW MATRIX SIZE D DIRECTION
4
ROW MATRIX SIZE E DIRECTION
MD
ME
N
e
SD/SE
DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2.
-
D
φb
1.
BODY SIZE
BALL FOOTPRINT
BALL FOOTPRINT
TOTAL BALL COUNT
44
0.25
0.30
0.35
BALL DIAMETER
0.50 BSC.
BALL PITCH
0.25 BSC.
SOLDER BALL PLACEMENT
NF1-4
A
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
DEPOPULATED SOLDER BALLS
8.
PACKAGE OUTLINE TYPE
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
* For reference only. BSC is an ANSI standard for Basic Space Centering.
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Am29BDS643G
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D A T A
S H E E T
REVISION SUMMARY
AC Characteristics, Erase and Program Operations
Revision A (November 1, 2001)
Corrected tWHWH1 and tWHWH2 to match same specifications elsewhere in document.
Initial release.
Physical Dimensions
Revision A+1 (November 9, 2001)
Replaced drawing with updated version.
Program Command Sequence;
Table 10, Command Definitions
Revision A2 (May 8, 2006)
Deleted references to unlock bypass chip and sector
erase commands.
Added migration/obsolescence information.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
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conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
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