ANACHIP AM93LC86

AM93LC86
16384-bits Serial Electrically Erasable PROM
General Description
Features
• State-of-the-art architecture
- Non-volatile data storage
- Standard voltage and low voltage operation
Vcc: 2.7V ~ 5.5V
- Full TTL compatible inputs and outputs
- Auto increment read for efficient data dump
• Hardware and software write protection
- Software instructions for write-enable/disable
- VCC level verification before self-timed
programming cycle
• Versatile, easy-to-use interface
- Self-timed programming cycle
- Automatic erase-before-write
- Programming status indicator
- Word and chip erasable
- Stop SK anytime for power savings
• Durability and reliability
- 40 years data retention
- Minimum of 1M write cycles per word
- Unlimited read cycles
- ESD protection
The AM93LC86 is the 16384-bit non-volatile serial
EEPROM. The AM93LC86 provides efficient
non-volatile read/write memory arranged as 1024
words of 16 bits each when the ORG Pin is
connected to VCC and 2048 words of 8 bits each
when it is tied to ground. The instruction set
includes read, write, and write enable/disable
functions. The data out pin (DO) indicates the
status of the device during the self-timed
non-volatile programming cycle.
The self-timed write cycle includes an automatic
erase-before-write capability. Only when the chip is
in the write enable state and proper Vcc operation
range is the write instruction accepted and thus to
protect against inadvertent writes. Data is written in
16 bits per write instruction into the selected
register. If chip select (CS) is brought high after
initiation of the write cycle, the data output (DO) pin
will indicate the read/busy status of the chip.
The AM93LC86 is available in space-saving 8-lead
PDIP, SOP and TSSOP packages.
Pin Descriptions (note)
Pin Assignments
CS
1
8
SK
2
DI
3
DO
4
(Preliminary)
VCC
CS
1
8
VCC
7
WP
SK
2
7
WP
6
ORG
DI
3
6
ORG
5
GND
DO
4
5
GND
PDIP Package
Name
CS
SK
DI
DO
GND
VCC
SOP Package
CS
1
8
VCC
SK
2
7
WP
DI
3
6
ORG
DO
4
5
GND
WP
ORG
Description
Chip select
Serial clock
Data input
Data output
Ground
Power supply
Write protection (active low)
Organization
Note: See pin descriptions (continued) for more details
TSSOP Package
Ordering Information
AM93 LC 86 X X X
Operating Voltage
Type
LC : 2.7V~5.5V,CMOS
86: 16K
Temp. grade
o
o
Blank : 0 Co~ +70 Co
I : − 40 C ~ +85 C
Package
S : SOP-8L
N : PDIP-8L
TS: TSSOP-8L
Packing
Blank : Tube
A : Taping
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev 0.1 Oct 20, 2003
1/12
AM93LC86
16384-bits Serial Electrically Erasable PROM
(Preliminary)
Block Diagram
Data register
Instruction
register
(13/14 bits)
DI
R/W AMPS
CS
Address register
Decoder
Instruction
decode control
and
clock generation
SK
DO
Dummy bit
EEPROM
array
(1024 X 16)
or
(2048 X 8)
VCC range
detector
VCC
GND
WP
Write enable
High voltage
generator
ORG
Absolute Maximum Ratings
Symbol
TSTG
VCC
TOP
Parameter
Storage temperature
Voltage with respect to ground
Temperature under bias
Rating
-65 to +125
-0.3 to + 6.5
0 to + 70
Unit
°C
V
°C
Note: These are stress rating only. Appropriate conditions for operating these devices given elsewhere may permanently damage the
part. Prolonged exposure to maximum ratings may affect device reliability.
Anachip Corp.
www.anachip.com.tw
Rev 0.1 Oct 20, 2003
2/12
AM93LC86
16384-bits Serial Electrically Erasable PROM
(Preliminary)
DC Electrical Characteristics (Vcc =2.7~5.5V, TA = 25oC, unless otherwise noted)
Symbol
ICC
ISB
IIL
IOL
Parameter
Operating current**
Standby current
Input leakage
Output leakage
VIL
Input low voltage**
VIH
Input high voltage**
VOL1
VOH1
VOL2
VOL2
Output low voltage
Output high voltage
Output low voltage
Output high voltage
Conditions
CS=VIH, SK=1MHz CMOS input levels
CS=DI=SK=0V
VIN = 0V to VCC(CS,SK,DI)
VOUT = 0V to VCC, CS=0V
VCC = 3V + 10%
VCC = 5V + 10%
VCC = 3V + 10%
VCC = 5V + 10%
IOL = 2.1mA TTL, VCC=5V + 10%
IOH = -400uA TTL, VCC=5V + 10%
IOL = 10uA CMOS
IOH = -10uA CMOS
Min
-1
-1
-0.1
-0.1
0.8 VCC
2
Max
3
10
1
1
0.15 VCC
0.8
VCC +0.2
VCC+0.2
0.4
2.4
0.2
VCC -0.2
Unit
mA
µA
µA
µA
V
V
V
V
V
V
Note ** : ICC, VIL min and VIH max are for reference only and are not tested.
AC Electrical Characteristics (Vcc = 2.7V ~ 5.5V, TA = 25oC, unless otherwise noted)
Symbol
FSK
TSKH
TSKL
TCS
TCSS
TDIS
TCSH
TDIH
TPD1
TPD0
TSV
TDF
TWP
Endurance(note)
Parameter
SK Clock Frequency
SK High Time
SK Low Time
Minimum CS Low Time
CS Setup Time
DI Setup Time
CS Hold Time
DI Hold Time
Output Delay to "1"
Output Delay to "0"
CS to Status Valid
CS to DO in 3-state
Write Cycle Time
5V, 25ºC
Conditions
Relative to SK
Relative to SK
Relative to SK
Relative to SK
AC test (Fig. 1)
AC test (Fig. 1)
AC test CL = 100pF
CS = VIL
Min
0
250
250
250
50
100
0
100
Max
1
500
500
500
100
10
1M
Unit
Mhz
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
mS
write cycles
Note: The parameter is characterized and isn’t 100% tested.
1.247V
(1 TTL Gate Load)
632 ohm
DO
100PF
Figure 1. AC test circuit
Anachip Corp.
www.anachip.com.tw
Rev 0.1 Oct 20, 2003
3/12
AM93LC86
16384-bits Serial Electrically Erasable PROM
(Preliminary)
Pin Capacitance (note) (TA=25°C, F=1Mhz )
Symbol
COUT
CIN
Parameter
Output capacitance
Input capacitance
Max
5
5
Unit
pF
pF
Note: The parameter is characterized and isn’t 100% tested.
Instruction Set
Instruction
(note)
Start bit
Op code
1
1
1
1
1
1
1
10
00
01
00
00
11
00
READ
EWEN
WRITE
WRAL
EWDS
ERASE
ERAL
Note:
READ: Read
EWEN: Erase/write enable
WRITE: Write
WRAL: Write all
Address
X8
X16
A10 ~ A0
A9 ~ A0
11XXXXXXXXX
11XXXXXXXX
A10 ~ A0
A9 ~ A0
01XXXXXXXXX
01XXXXXXXX
00XXXXXXXXX
00XXXXXXXX
A10 ~ A0
A9 ~ A0
10XXXXXXXXX
10XXXXXXXX
Input data
× 8
× 16
D7 – D0
D15 - D0
D7 – D0
D15 - D0
-
EWDS: Erase/write disable
ERASE: Erase
ERAL: Erase all
Functional Description
Endurance and data retention
The AM93LC86 is designed for applications
requiring up to 1M programming cycles (WRITE,
WRAL, EARSE and ERAL). It provides 40 years of
secure data retention.
operation instruction. To utilize this function, the
system asserts a read instruction specifying a start
location address. Once the 8-bit or 16-bit of the
addressed word have been clocked out, the data in
consecutively higher address locations is output.
The address will wrap around continuously with CS
high until the chip select (CS) control pin is brought
low. This allows for single instruction data dumps to
be executed with a minimum of firmware overhead.
Device operation
The AM93LC86 is controlled by seven 13-bit
instructions. Instructions are clocked in (serially) on
the DI pin. Each instruction begins with a logical "1"
(the start bit). This is followed by the opcode (2 bits),
the address field (10/11 bits), and data, if
appropriated,. The clock signal (SK) may be halted
at any time and the AM93LC86 will remain in its last
state. This allows full static flexibility and maximum
power conservation.
Read (READ)
The READ instruction is the only instruction that
outputs serial data on the DO pin. After the read
instruction and address have been decoded, data is
transferred from the selected memory register into
a 8-bit or 16-bit serial shift register. (Please note
that one logical "0" bit precedes the actual 8-bit or
16-bit output data string.) The output on DO
changes during the rising edge transitions of SK.
(shown in figure 3)
Auto increment read operations
Sequential read is possible, since the AM93LC86
has been designed to output a continuous stream
of memory content in response to a single
read
Anachip Corp.
www.anachip.com.tw
Rev 0.1 Oct 20, 2003
4/12
AM93LC86
16384-bits Serial Electrically Erasable PROM
(Preliminary)
Functional Description
Erase/write enable (EWEN)
Before any device programming (WRITE, WRAL,
ERASE, and ERAL) can be done, the EWEN
instruction must be executed first. When Vcc is
applied, this device powers up in the EWDS state.
The device then remains in a erase/write disable
(EWDS) state until a EWEN instruction is executed.
Thereafter the device remains enabled until a
EWDS instruction is executed or until Vcc is
removed. (shown in Figure 4)
Note: Neither the EWEN nor the EWDS instruction
has any effect on the READ instruction.
Before a WRITE instruction can be executed, the
device must be in the Write enable (WEN) state.
Write all (WRAL)
The Write All (WRAL) instruction programs all
registers with the data pattern specified in the
instruction. While the WRAL instruction is being
loaded, the address field becomes a sequence of
DON'T-CARE bits. (Shown in Figure 7)
As with the WRITE instruction, if CS is brought
HIGH after a minimum wait of 250ns (tcs), the DO
pin indicates the READY/BUSY status of the chip.
(shown in figure 7)
Erase/write disable (EWDS)
The erase/write disable (EWDS) instruction
disables all programming capabilities. This protects
the entire part against accidental modification of
data until a EWEN instruction is executed. (When
Vcc is applied, this part powers up in the EWDS
state.) To protect data, a EWDS instruction should
be executed upon completion of each programming
operation.
Erase (ERASE)
After the erase instruction is entered, CS must be
brought LOW. The falling edge of CS initiates the
self-timed internal programming cycle. Bringing CS
HIGH after minimum of tcs, will cause DO to
indicate the READ/BUSY status of the chip. To
explain this, a logical "0" indicates the programming
is still in progress while a logical "1" indicates the
erase cycle is complete and the part is ready for
another instruction. (shown in figure 8)
Note:
Neither the EWEN nor the EWDS instruction has any effect on
the READ instruction. (shown in figure 5)
Erase all (ERAL)
Full chip erase is provided for ease of programming.
Erasing the entire chip involves setting all bits in the
entire memory array to a logical "1". (shown in
figure 9)
Write (WRITE)
The WRITE instruction includes 8-bit or 16-bit of
data to be written into the specified register. After
the last data bit has been applied to DI, and before
the next rising edge of SK, CS must be brought low.
The falling edge of CS initiates the self-timed
programming cycle. After a minimum wait of 250ns
(5V operation) from the falling edge of CS (tcs), DO
will indicate the READY/BUSY status of the chip if
CS is brought HIGH. This means that logical "0"
implies the programming is still in progress while
logical "1" indicates the selected register has been
written, and the part is ready for another instruction.
(shown in figure 6)
Note:
The combination of CS HIGH, DI HIGH and the rising edge of
the SK clock, resets the READY/BUSY flag. Therefore, it is
important if you want to access the READY/BUSY flag, not to
reset it through this combination of control signals.
Anachip Corp.
www.anachip.com.tw
Rev 0.1 Oct 20, 2003
5/12
AM93LC86
16384-bits Serial Electrically Erasable PROM
(Preliminary)
Timing Diagrams
Organization Key
AM93LC86 (16K)
I/O
X8
A10
D7
AN
DN
X16
A9
D15
T
CS
tSKH
tCSS
tSKL
tCSH
SK
tDIS
tDIH
DI
tPD1
tPDO
tDF
DO(READ)
tSV
tDF
STATUS VALID
DO(WRITE)
(WRALL)
(ERASE)
(ERALL)
Figure 2. Synchronous data timing
tCS
CS
+
SK
1
DI
DO
1
0
AN
AO
*
TRI-STATE
O
DN
DO
+For all instructions, SK cycles before start bit don't care.
*Address Pointer Cycle to the Next Register.
Figure 3. Data read cycle timing
Anachip Corp.
www.anachip.com.tw
Rev 0.1 Oct 20, 2003
6/12
AM93LC86
16384-bits Serial Electrically Erasable PROM
(Preliminary)
tCS
CS
SK
**
1
DI
0
0
1
X- - - - - - - - - - - X
1
DO = TRI-STATE
**AN-2~A0 don't care.
FIigure 4. Erase/write enable(WEN) cycle timing
tCS
CS
SK
**
1
DI
0
0
0
X- - - - -- - - - X
0
DO = TRI-STATE
**AN-2~A0 don't care.
Figure 5. Erase/write disable(EWDS) cycle timing
tCS
CS
SK
1
DI
0
1
AN
AO
DN
DO
tSV
DO
TRI-STATE
tDF
BUSY
READY
tWP
Figure 6. Write(WRITE) cycle timing
Anachip Corp.
www.anachip.com.tw
Rev 0.1 Oct 20, 2003
7/12
AM93LC86
16384-bits Serial Electrically Erasable PROM
(Preliminary)
tCS
CS
SK
**
1
0
DI
0
X- - - - - - - - - - - -X
1
0
DN
DO
tSV
TRI-STATE
DO
BUSY
**AN-2~A0 don't care.
READY
tWP
Figure 7. Write all(WRAL) cycle timing
tCS
CS
SK
1
DI
1
AN
1
AO
tSV
tDF
TRI-STATE
DO
BUSY
READY
tWP
Figure 8. Erase(ERASE) cycle timing
tCS
CS
SK
**
1
0
DI
0
1
0
X- - - - - - - - - X
tSV
DO
TRI-STATE
BUSY
tDF
READY
tWP
**AN-2~A0 don't care.
Figure 9. Erase all(ERAL) cycle timing
Anachip Corp.
www.anachip.com.tw
Rev 0.1 Oct 20, 2003
8/12
AM93LC86
16384-bits Serial Electrically Erasable PROM
(Preliminary)
Pin Description (Continued)
the table of instruction set). SK and DI then become
don’t care inputs waiting for a new start condition to
be detected.
Note:
CS must go low between consecutive instructions,
except when performing a sequential read.
Chip select (CS)
A high level selects the device. A low level
deselects the device an forces it into standby mode.
However, a programming cycle which is already
initiated will be completed, regardless of the CS
input signal. If CS is brought low during a program
cycle, the device will go into standby mode as soon
as the programming cycle is completed.
Data input (DI)
Data input is used to clock in a start bit, opcode,
address, and data synchronously with the CLK
input.
Serial clock (SK)
The serial clock is used to synchronize the
communication between a master device and the
AM93LC86. Opcode, address, and data bits are
clocked in on the positive edge of SK. Data bits are
also clocked out on the positive edge of SK.
SK can be stopped anywhere in the transmission
sequence (at high or low level) and can be
continued anytime with respect to clock high time
(TCKH) and clock low time (TCKL). This gives the
controlling master freedom in preparing opcode,
address, and data.
SK is a “don’t care” if CS is low (device deselected).
If CS is high, but START condition has not been
detected, any number of clock cycles can be
recevived by the device without changing its status
(i.e., waiting for START condition).
SK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycles.
After detection of a start condition the specified
number of clock cycles (respectively low to high
transitions of SK) must be provided. These clock
cycles are required to clock in all opcode, address,
and data bits before an instruction is executed (see
Data output (DO)
Data output is used in the READ mode to output
data synchronously with the CLK input( TPD after
the positive edge of CLK)
Write protection ( WP )
This pin allows the user to enable or disable the
ability to write data to the memory array. If the WP
pin is floated or tied to VCC, the device can be
programmed. If the WP pin is tied to GND,
programming will be inhibited. There is an internal
pull-up on this device that enables programming if
this pin is left floating.
Organization (ORG)
When ORG is connected to VCC, the X16 memory
organization is selected. When ORG is tied to GND,
the X8 memory organization is selected. There is
an internal pull-up resistor on the ORG pin that will
select X16 organization when left unconnected.
Anachip Corp.
www.anachip.com.tw
Rev 0.1 Oct 20, 2003
9/12
AM93LC86
16384-bits Serial Electrically Erasable PROM
(Preliminary)
Package Information
(1) Package Type: PDIP-8L
D
E1
E-PIN O0.118 inch
E
15 (4X)
PIN #1 INDENT O0.025 DEEP 0.006-0.008 inch
C
7 (4X)
A1
L
A
A2
eB
B
S
Symbol
A
A1
A2
B
B1
B2
C
D
E
E1
e
L
eB
S
e
B1
B2
Dimensions in millimeters
Min.
Nom.
Max.
5.33
0.38
3.1
3.30
3.5
0.36
0.46
0.56
1.4
1.52
1.65
0.81
0.99
1.14
0.20
0.25
0.36
9.02
9.27
9.53
7.62
7.94
8.26
6.15
6.35
6.55
2.54
2.92
3.3
3.81
8.38
8.89
9.40
0.71
0.84
0.97
Anachip Corp.
www.anachip.com.tw
Dimensions in inches
Min.
Nom.
Max.
0.210
0.015
0.122
0.130
0.138
0.014
0.018
0.022
0.055
0.060
0.065
0.032
0.039
0.045
0.008
0.010
0.014
0.355
0.365
0.375
0.300
0.313
0.325
0.242
0.250
0.258
0.100
0.115
0.130
0.150
0.330
0.350
0.370
0.028
0.033
0.038
Rev 0.1 Oct 20, 2003
10/12
AM93LC86
16384-bits Serial Electrically Erasable PROM
(Preliminary)
H
E
(2) Package Type: SOP-8L
L
VIEW "A"
D
0.015x45
C
B
A1
e
7 (4X)
A
A2
7 (4X)
VIEW "A"
y
Symbol
A
A1
A2
B
C
D
E
e
H
L
y
θ
Dimensions In Millimeters
Min.
Nom.
Max.
1.40
1.60
1.75
0.10
0.25
1.30
1.45
1.50
0.33
0.41
0.51
0.19
0.20
0.25
4.80
5.05
5.30
3.70
3.90
4.10
1.27
5.79
5.99
6.20
0.38
0.71
1.27
0.10
8O
0O
Anachip Corp.
www.anachip.com.tw
Dimensions In Inches
Min.
Nom.
Max.
0.055
0.063
0.069
0.040
0.100
0.051
0.057
0.059
0.013
0.016
0.020
0.0075
0.008
0.010
0.189
0.199
0.209
0.146
0.154
0.161
0.050
0.228
0.236
0.244
0.015
0.028
0.050
0.004
0O
8O
Rev 0.1 Oct 20, 2003
11/12
AM93LC86
16384-bits Serial Electrically Erasable PROM
(Preliminary)
E
E1
(3) Package Type: TSSOP-8L
PIN 1 INDICATOR ψ0.70 mm
SURFACE POLISHED
L
L1
DETAIL A
D
e
A
A1
A2
b
C
D
E
E1
e
L
L1
y
θ
Dimensions In Millimeters
Min.
Nom.
Max.
1.05
1.10
1.20
0.05
0.10
0.15
1.00
1.05
0.20
0.25
0.28
0.13
2.90
3.05
3.10
6.20
6.40
6.60
4.30
4.40
4.50
0.65
0.50
0.60
0.70
0.90
1.00
1.10
0.10
4O
8O
0O
DETAIL A
C
A1
b
y
Symbol
L1
A
A2
E1
Dimensions In Inches
Min.
Nom.
Max.
0.041
0.043
0.047
0.002
0.004
0.006
0.039
0.041
0.008
0.01
0.011
0.005
0.114
0.12
0.122
0.244
0.252
0.26
0.169
0.173
0.177
0.026
0.02
0.024
0.028
0.035
0.039
0.043
0.004
0O
4O
8O
Marking Information
8
Logo
Part Number & grade
o
o
X=Blank( 0 C to + 70 C)
o
( - 40 C to + 85o C)
X=I
7
6
5
AC
93LC86X
YYWWX
1 2 3 4
PDIP/SOP/TSSOP Package
Anachip Corp.
www.anachip.com.tw
Date Code
YY: Year
WW: Nth week
X: Internal code
Rev 0.1 Oct 20, 2003
12/12