APL5930 3A, Ultra Low Dropout (0.23V Typical) Linear Regulator Features General Description • • The APL5930 is a 3A ultra low dropout linear regulator. The IC needs two supply voltages, one is a control voltage Compatible with APL5913 Ultra Low Dropout (VCNTL) for the control circuitry, the other is a main supply voltage (VIN) for power conversion, to reduce power dissi- - 0.23V(typical) at 3A Output Current • Low ESR Output Capacitor (Multi-layer pation and provide extremely low dropout voltage. The APL5930 integrates many functions. A Power-On- Chip Capacitors (MLCC)) Applicable • • 0.8V Reference Voltage Reset (POR) circuit monitors both supply voltages on VCNTL and VIN pins to prevent erroneous operations. High Output Accuracy - ±1.5% over Line, Load, and Temperature Range • • • The functions of thermal shutdown and current-limit protect the device against thermal and current over-loads. A Fast Transient Response POK indicates the output voltage status with a delay time set internally. It can control other converter for power Adjustable Output Voltage Power-On-Reset Monitoring on Both VCNTL and sequence. The APL5930 can be enabled by other power systems. Pulling and holding the EN voltage below 0.4V VIN Pins • • • • • • • • Internal Soft-Start shuts off the output. The APL5930 is available in a SOP-8P package which Current-Limit and Short Current-Limit Protections Thermal Shutdown with Hysteresis Open-Drain VOUT Voltage Indicator (POK) features small size as SOP-8 and an Exposed Pad to reduce the junction-to-case resistance to extend power Low Shutdown Quiescent Current (<30 µA) range of applications. Shutdown/Enable Control Function Applications Simple SOP-8P Package with Exposed Pad • • • Lead Free and Green Devices Available (RoHS Compliant) Pin Configuration Front Side Bus VTT (1.2V/3A) Note Book PC Applications Motherboard Applications Simplified Application Circuit VCNTL GND FB VOUT VOUT 8 7 6 5 1 2 3 4 EN POK VCNTL VIN VIN VCNTL VIN POK POK SOP-8P (Top View) VOUT VOUT APL5930 = Exposed Pad (connected to VIN plane for better heat dissipation) EN Enable EN GND FB Optional ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2009 1 www.anpec.com.tw APL5930 Ordering and Marking Information Package Code KA : SOP-8P Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APL5930 Assembly Material Handling Code Temperature Range Package Code APL5930 XXXXX APL5930 KA : XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VIN (Note 1) Parameter VIN Supply Voltage (VIN to GND) VCNTL VCNTL Supply Voltage (VCNTL to GND) VOUT VOUT to GND Voltage POK to GND Voltage EN, FB to GND Voltage PD Power Dissipation TJ Maximum Junction Temperature TSTG TSDR Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds Rating Unit -0.3 ~ 4.0 V -0.3 ~ 7 V -0.3 ~ VIN +0.3 V -0.3 ~ 7 V -0.3 ~ VCNTL +0.3 V 3 W 150 o -65 ~ 150 o 260 o C C C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA θJC Parameter Typical Value Junction-to-Ambient Resistance in Free Air (Note 2) SOP-8P Junction-to-Case Resistance in Free Air (Note 3) SOP-8P Unit 42 o 18 o C/W C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8P is soldered directly on the PCB. Note 3: The “Thermal Pad Temperature” is measured on the PCB copper area connected to the thermal pad of package. 1 2 3 4 8 VIN 7 6 5 Measured Point PCB Copper Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2009 2 www.anpec.com.tw APL5930 Recommended Operating Conditions Symbol VCNTL VIN VOUT Range Unit VCNTL Supply Voltage Parameter 3.0 ~ 5.5 V VIN Supply Voltage 1.2 ~ 3.65 V 0.8 ~ VIN – VDROP V VOUT Output Voltage (when VCNTL-VOUT>1.9V) IOUT VOUT Output Current COUT VOUT Output Capacitance ESRCOUT TA TJ Continuous Current 0~3 Peak Current 0~4 IOUT = 3A at 25% nominal VOUT 8 ~ 1100 IOUT = 2A at 25% nominal VOUT 8 ~ 1700 IOUT = 1A at 25% nominal VOUT 8 ~ 2400 A µF ESR of VOUT Output Capacitor 0 ~ 200 Ambient Temperature -40 ~ 85 o -40 ~ 125 o Junction Temperature mΩ C C Electrical Characteristics Unless otherwise specified, these specifications apply over VCNTL=5V, VIN=1.8V, VOUT= 1.2V and TA= -40 ~ 85 oC. Typical values are at T A=25oC. Symbol Parameter Test Conditions APL5930 Min. Typ. Max. Unit SUPPLY CURRENT IVCNTL ISD VCNTL Supply Current EN = VCNTL, IOUT=0A - 1.0 1.5 mA VCNTL Supply Current at Shutdown EN = GND - 15 30 µA VIN Supply Current at Shutdown EN = GND, VIN=3.65V - - 1 µA 2.5 2.7 2.9 V POWER-ON-RESET (POR) Rising VCNTL POR Threshold VCNTL POR Hysteresis Rising VIN POR Threshold VIN POR Hysteresis - 0.4 - V 0.8 0.9 1.0 V - 0.5 - V - 0.8 - V -1.5 - +1.5 % - 0.06 0.25 % - 0.15 - + 0.15 %/V OUTPUT VOLTAGE VREF Reference Voltage FB=VOUT Output Voltage Accuracy VCNTL=3.0 ~ 5.5V, IOUT= 0~3A, TJ= -40~125oC Load Regulation IOUT=0A ~3A Line Regulation IOUT=10mA, VCNTL= 3.0 ~ 5.5V VOUT Pull-low Resistance VCNTL=3.3V, VEN=0V, VOUT<0.8V FB Input Current VFB=0.8V - 85 - Ω -100 - 100 nA TJ=25oC - 0.26 0.31 TJ=-40~125oC - - 0.42 TJ=25oC - 0.24 0.29 TJ=-40~125oC - - 0.40 TJ=25oC - 0.23 0.28 TJ=-40~125oC - - 0.38 DROPOUT VOLTAGE VOUT=2.5V VDROP VIN-to-VOUT Dropout Voltage VCNTL=5.0V VOUT=1.8V , IOUT=3A VOUT=1.2V Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2009 3 V www.anpec.com.tw APL5930 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCNTL=5V, VIN=1.8V, VOUT= 1.2V and TA= -40 ~ 85 oC. Typical values are at T A=25oC. Symbol Parameter APL5930 Test Conditions Unit Min. Typ. Max. 4.7 5.7 6.7 4.2 - - - 1.1 - A 0.6 1.5 - ms - 170 - o - 50 - o 0.5 0.8 1.1 - 0.1 - V - 5 - µA 0.3 0.6 1.2 ms From being enabled to VOUT rising 10% 60 120 180 µs VFB rising 90 92 94 % DROPOUT VOLTAGE (CONT.) ILIM Current-Limit Level TJ=25oC o TJ= -40 ~ 125 C A PROTECTIONS ISHORT TSD Short Current-Limit Level VFB<0.2V Short Current-Limit Blanking Time From beginning of soft-start Thermal Shutdown Temperature TJ rising Thermal Shutdown Hysteresis C C ENABLE AND SOFT-START EN Logic High Threshold Voltage VEN rising EN Hysteresis EN Pull-High Current TSS EN=GND Soft-Start Interval Turn On Delay V POWER-OK AND DELAY VTHPOK Rising POK Threshold Voltage POK Threshold Hysteresis - 8 - % POK Pull-low Voltage POK sinks 5mA - 0.25 0.4 V POK Debounce Interval VFB<falling POK voltage threshold - 10 - µs POK Delay Time From VFB =VTHPOK to rising edge of the VPOK 1 2 4 ms Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2009 4 www.anpec.com.tw APL5930 Typical Operating Characteristics Current-Limit vs. Junction Temperature Short Current-Limit vs. Junction Temperature 6.5 1.20 Current-Limit, ILIM (A) 6.0 Short Current-Limit, ISHORT (mA) VOUT = 1.2V VCNTL = 5V 5.5 5.0 VCNTL = 3.3V 4.5 4.0 3.5 1.18 1.16 1.14 1.10 1.08 -25 0 25 50 75 100 VCNTL = 3.3V 1.06 1.04 1.02 1.00 -50 VCNTL = 5V 1.12 125 -50 -25 Junction Temperature (oC) 50 75 100 125 Droput Voltage vs. Output Current 450 450 VCNTL = 5V VOUT = 1.2V 400 350 Dropout Voltage, VDROP (mV) Dropout Voltage, VDROP (mV) 25 Junction Temperature (oC) Dropout Voltage vs. Output Current TJ = 125° C 300 TJ = 75° C TJ = 25° C 250 200 150 100 TJ = 0° C 50 TJ = - 40° C VCNTL = 3.3V VOUT = 1.2V 400 350 TJ = 125° C 300 TJ = 75° C TJ = 25° C 250 200 150 100 TJ = 0° C 50 TJ = - 40° C 0 0 0 0.5 1 1.5 2 2.5 0 3 0.5 Output Current, IOUT (A) 1 1.5 2 2.5 3 Output Current, IOUT (A) Dropout Voltage vs. Output Current Dropout Voltage vs. Output Current 400 400 VCNTL = 5V VOUT = 1.5V 350 Dropout Voltage, VDROP (mV) Dropout Voltage, VDROP (mV) 0 TJ = 125° C 300 TJ = 75° C 250 TJ = 25° C 200 150 100 TJ = 0° C 50 TJ = - 40° C 0 VCNTL = 5V 350 VOUT = 1.8V TJ = 125° C 300 TJ = 75° C 250 TJ = 25° C 200 150 100 TJ = 0° C TJ = - 40° C 50 0 0 0.5 1 1.5 2 2.5 3 0 Output Current, IOUT (A) Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2009 0.5 1 1.5 2 2.5 3 Output Current, IOUT (A) 5 www.anpec.com.tw APL5930 Typical Operating Characteristics (Cont.) Reference Voltage vs. Junction Temperature Dropout Voltage vs. Output Current 0.808 VCNTL = 5V 400 VOUT = 2.5V Reference Voltage, VREF (V) Dropout Voltage, VDROP (mV) 450 TJ = 125° C 350 300 TJ = 75° C TJ = 25° C 250 200 150 100 TJ = 0° C 50 0.806 0.804 0.802 0.800 0.798 0.796 0.794 TJ = - 40° C 0 0.792 0 0.5 1 1.5 2 2.5 -50 3 -25 Output Current, IOUT (A) Power Supply Rejection Ratio (dB) Power Supply Rejection Ratio (dB) 100 125 0 -30 -40 -50 10000 75 VCNTL Power Supply Rejection Ratio (PSRR) VCNTL=5V VIN=1.8V VINPK-PK=100mV VOUT=1.2V IOUT=3A CIN=10µF COUT=10µF -60 1000 50 Junction Temperature ( C) 0 -20 25 o VIN Power Supply Rejection Ratio (PSRR) -10 0 100000 -20 VCNTL=4.6~5.4V VIN=1.8V VOUT=1.2V IOUT=3A CIN=COUT=10µF -30 -40 -50 -60 -70 1000 1000000 Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2009 -10 10000 100000 1000000 Frequency (Hz) 6 www.anpec.com.tw APL5930 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=1.8V, VCNTL=5V, VOUT=1.2V, TA= 25oC unless otherwise specified. Power On Power Off VCNTL VCNTL 1 1 VIN VIN 2 2 VOUT VOUT 3 3 VPOK VPOK 4 4 COUT=10µF, CIN=10µF, RL=0.4Ω CH1: VCNTL, 5V/Div, DC CH2: VIN, 1V/Div, DC CH3: VOUT, 1V/Div, DC CH4: VPOK, 5V/Div, DC TIME: 2ms/Div COUT=10µF, CIN=10µF, RL=0.4Ω CH1: VCNTL, 5V/Div, DC CH2: VIN, 1V/Div, DC CH3: VOUT, 1V/Div, DC CH4: VPOK, 5V/Div, DC TIME: 2ms/Div Load Transient Response Over Current Protection VOUT VOUT 1 1 IOUT IOUT 2 4 IOUT=10mA to 3A to 10mA (rise / fall time = 1µs) COUT=10µF, CIN=10µF CH1: VOUT, 50mV/Div, AC CH2: IOUT, 1A/Div, DC TIME: 50µs/Div Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2009 COUT=10µF, CIN=10µF, IOUT= 2A to 5.6A CH1: VOUT, 0.5V/Div, DC CH4: IOUT, 2A/Div, DC TIME: 0.2ms/Div 7 www.anpec.com.tw APL5930 Operating Waveforms (Cont.) Refer to the typical application circuit. The test condition is VIN=1.8V, VCNTL=5V, VOUT=1.2V, TA= 25oC unless otherwise specified. Enable Shutdown VEN VEN 1 1 VOUT VOUT 2 2 VPOK VPOK 3 3 IOUT IOUT 4 4 COUT=10µF, CIN=10µF, RL=0.4Ω CH1: VEN, 5V/Div, DC CH2: VOUT, 0.5V/Div, DC CH3: VPOK, 5V/Div, DC CH4: IOUT, 2A/Div, DC TIME: 0.5ms/Div COUT=10µF, CIN=10µF, RL=0.4Ω CH1: VEN, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPOK, 5V/Div, DC CH4: IOUT, 2A/Div, DC TIME: 2µs/Div Pin Description PIN FUNCTION NO. NAME 1 GND 2 FB Voltage Feedback Pin. Connecting this pin to an external resistor divider receives the feedback voltage of the regulator. 3，4 VOUT Output pin of the regulator. Connecting this pin to load and output capacitors (10µF at least) is required for stability and improving transient response. The output voltage is programmed by the resistor-divider connected to FB pin. The VOUT can provide 3A (max.) load current to loads. During shutdown, the output voltage is quickly discharged by an internal pull-low MOSFET. 5 VIN Main supply input pin for voltage conversions. A decoupling capacitor (≥10µF recommended) is usually connected near this pin to filter the voltage noise and improve transient response. The voltage on this pin is monitored for Power-On-Reset purpose. 6 VCNTL Bias voltage input pin for internal control circuitry. Connect this pin to a voltage source (+5V recommended). A decoupling capacitor (1µF typical) is usually connected near this pin to filter the voltage noise. The voltage at this pin is monitored for Power-On-Reset purpose. 7 POK Power-OK signal output pin. This pin is an open-drain output used to indicate the status of output voltage by sensing FB voltage. This pin is pulled low when output voltage is not within the Power-OK voltage window. 8 EN Active-high enable control pin. Applying and holding the voltage on this pin below the enable voltage threshold shuts down the output. When re-enabled, the IC undergoes a new soft-start process. When leave this pin open, an internal pull-up current (5µA typical) pulls the EN voltage and enables the regulator. Exposed Pad - Ground pin of the circuitry. All voltage levels are measured with respect to this pin. Connect this pad to system VIN plane for good thermal conductivity. Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2009 8 www.anpec.com.tw APL5930 Block Diagram VCNTL Thermal Shutdown VCNTL PowerOn-Reset (POR) POR 5µA EN Enable 0.8V Control Logic and Soft-Start POR Enable Soft-Start POK VIN PWOK VREF 0.8V VOUT Error Amplifier ISEN Delay Current-Limit and Short CurrentLimit 90% VREF GND FB Typical Application Circuit VCNTL (+5V is preferred) CCNTL 1µF VIN +1.8V 6 R3 5.1kΩ VCNTL 7 POK CIN 10µF VIN POK VOUT 5 3,4 VOUT +1.2V / 3A COUT 10µF APL5930 EN 8 EN FB 2 (X5R/X7R Recommended) GND Enable 1 R2 24kΩ R1 12kΩ C1 Optional (X5R/X7R Recommended) 10µF: GRM31MR60J106KE19 Murata Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2009 9 www.anpec.com.tw APL5930 Function Description Power-On-Reset Thermal Shutdown A Power-On-Reset (POR) circuit monitors both of supply voltages on VCNTL and VIN pins to prevent wrong logic A thermal shutdown circuit limits the junction temperature of APL5930. When the junction temperature exceeds +170oC, a thermal sensor turns off the output NMOS, al- controls. The POR function initiates a soft-start process after both of the supply voltages exceed their rising POR lowing the device to cool down. The regulator regulates the output again through initiation of a new soft-start pro- voltage thresholds during powering on. The POR function also pulls low the POK voltage regardless the output cess after the junction temperature cools by 50oC, resulting in a pulsed output during continuous thermal over- status when one of the supply voltages falls below its load conditions. The thermal shutdown is designed with a 50oC hysteresis to lower the average junction tempera- falling POR voltage threshold. Internal Soft-Start ture during continuous thermal overload conditions, extending lifetime of the device. An internal soft-start function controls rise rate of the output voltage to limit the current surge during start-up. The For normal operation, the device power dissipation should be externally limited so that junction temperatures will typical soft-start interval is about 0.6 ms. not exceed +125oC. Output Voltage Regulation Enable Control An error amplifier works with a temperature-compensated 0.8V reference and an output NMOS regulates The APL5930 has a dedicated enable pin (EN). A logic output to the preset voltage. The error amplifier is designed with high bandwidth and DC gain provides very low signal applied to this pin shuts down the output. Following a shutdown, a logic high signal re-enables the fast transient response and less load regulation. It compares the reference with the feedback voltage and ampli- output through initiation of a new soft-start cycle. When left open, this pin is pulled up by an internal current source (5µA typical) to enable normal operation. It’s not neces- fies the difference to drive the output NMOS which provides load current from VIN to VOUT. sary to use an external transistor to save cost. Current-Limit Protection Power-OK and Delay The APL5930 monitors the current flowing through the output NMOS and limits the maximum current to prevent The APL5930 indicates the status of the output voltage by monitoring the feedback voltage (VFB) on FB pin. As the load and APL5930 from damages during current over- VFB rises and reaches the rising Power-OK voltage threshold (VTHPOK), an internal delay function starts to work. At load conditions. the end of the delay time, the IC turns off the internal NMOS of the POK to indicate that the output is ok. As the Short Current-Limit Protection V FB falls and reaches the falling Power-OK voltage threshold, the IC turns on the NMOS of the POK (after a The short current-limit function reduces the current-limit level down to 1.1A (typical) when the voltage on FB pin debounce time of 10µs typical). falls below 0.2V (typical) during current overload or shortcircuit conditions. The short current-limit function is disabled for successful start-up during soft-start interval. Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2009 10 www.anpec.com.tw APL5930 Application Information Power Sequencing Ultra-low-ESR capacitors (such as ceramic chip capacitors) and low-ESR bulk capacitors (such as solid The power sequencing of VIN and VCNTL is not necessary to be concerned. However, do not apply a voltage to tantalum, POSCap, and Aluminum electrolytic capacitors) can all be used as an input capacitor of VIN. For most VOUT for a long time when the main voltage applied at VIN is not present. The reason is the internal parasitic applications, the recommended input capacitance of VIN is 10µF at least. However, if the drop of the input voltage diode from VOUT to VIN conducts and dissipates power without protections due to the forward-voltage. is not cared, the input capacitance can be less than 10µF. More capacitance reduces the variations of the supply Output Capacitor voltage on VIN pin. The APL5930 requires a proper output capacitor to maintain stability and improve transient response. The output Setting Output Voltage The output voltage is programmed by the resistor divider capacitor selection is dependent upon ESR (equivalent series resistance) and capacitance of the output capaci- connected to FB pin. The preset output voltage is calculated by the following equation : tor over the operating temperature. Ultra-low-ESR capacitors (such as ceramic chip R1 VOUT = 0.8 ⋅ 1 + R2 capacitors) and low-ESR bulk capacitors (such as solid tantalum, POSCap, and Aluminum electrolytic capacitors) ........... (V) Where R1 is the resistor connected from VOUT to FB with Kelvin sensing connection and R2 is the resistor con- can all be used as output capacitors. During load transients, the output capacitors, depending nected from FB to GND. A bypass capacitor(C1) may be connected with R1 in parallel to improve load transient on the stepping amplitude and slew rate of load current, are used to reduce the slew rate of the current seen by response and stability. the APL5930 and help the device to minimize the variations of output voltage for good transient response. For the applications with large stepping load current, the lowESR bulk capacitors are normally recommended. Decoupling ceramic capacitors must be placed at the load and ground pins as close as possible and the impedance of the layout must be minimized. Input Capacitor The APL5930 requires proper input capacitors to supply current surge during stepping load transients to prevent the input voltage rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the surge currents, more parasitic inductance needs more input capacitance. Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2009 11 www.anpec.com.tw APL5930 Layout Consideration 1. Please solder the Exposed Pad on the VIN pad on the top-layer of PCBs. The VIN pad must have wide Thermal Consideration Refer to the figure 2, the SOP-8P is a cost-effective package featuring a small size like a standard SOP-8 and a size to conduct heat into the ambient air through the VIN plane and PCB as a heat sink. 2. 3. bottom exposed pad to minimize the thermal resistance of the package, being applicable to high current applica- Please place the input capacitors for VIN and VCNTL pins near the pins as close as possible for tions. The exposed pad must be soldered to the top-layer VIN plane. The copper of the VIN plane on the Top layer decoupling high-frequency ripples. Ceramic decoupling capacitors for load must be conducts heat into the PCB and ambient air. Please enlarge the area of the top-layer pad and the VIN plane to placed near the load as close as possible for decoupling high-frequency ripples. 4. 5. reduce the case-to-ambient resistance (θCA). To place APL5930 and output capacitors near the load reduces parasitic resistance and inductance 102 mil for excellent load transient response. The negative pins of the input and output capacitors 1 and the GND pin must be connected to the ground plane of the load. 6. Large current paths, shown by bold lines on the figure 1, must have wide tracks. 7. Place the R1, R2, and C1 near the APL5930 as close as possible to avoid noise coupling. 8. Connect the ground of the R2 to the GND pin by using a dedicated track. 9. Connect the one pin of the R1 to the load for Kelvin sensing. 2 118 mil 3 8 SOP-8P 7 6 5 4 Top VOUT plane Die Exposed Pad Top VIN plane Ambient Air PCB 10. Connect one pin of the C1 to the VOUT pin for reliable feedback compensation. Figure 2 Recommended Minimum Footprint 8 CIN 7 6 5 VCNTL 0.072 0.024 VCNTL CCNTL VIN VIN APL5930 VOUT 0.138 COUT C1 FB GND R1 0.118 0.212 VOUT Load R2 1 Figure 1 Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2009 2 0.050 12 3 4 Unit : Inch www.anpec.com.tw APL5930 Package Information SOP-8P D SEE VIEW A h X 45o E THERMAL PAD E1 E2 D1 c A1 0.25 A2 A b e GAUGE PLANE SEATING PLANE θ L VIEW A S Y M B O L SOP-8P MIN. MAX. MAX. 1.60 A A1 INCHES MILLIMETERS MIN. 0.063 0.000 0.15 0.00 0.006 0.049 A2 1.25 b 0.31 0.51 c 0.17 0.25 0.007 0.010 0.197 0.012 0.020 D 4.80 5.00 0.189 D1 2.50 3.50 0.098 0.138 E 5.80 6.20 0.228 0.244 0.157 0.118 E1 3.80 4.00 0.150 E2 2.00 3.00 0.079 0.020 0.050 e 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 L 0.40 1.27 0.016 0 o 0C o o 8C 0C 8oC Note : 1. Followed from JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2009 13 www.anpec.com.tw APL5930 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 OD1 B A B T SECTION A-A SECTION B-B H A d T1 Application SOP-8P A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.40±0.20 5.20±0.20 2.10±0.20 4.0±0.10 8.0±0.10 (mm) Devices Per Unit Package Type Unit Quantity SOP- 8P Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2009 14 www.anpec.com.tw APL5930 Taping Direction Information SOP-8P USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2009 15 www.anpec.com.tw APL5930 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2009 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 16 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APL5930 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Sep., 2009 17 www.anpec.com.tw