ANPEC APW1175KC-TUL

APW1175
Dual Synchronous DC/DC Controllers with Current Sharing Control
Features
General Description
•
Two Operation Modes
The APW1175 is a two-phase, synchronous, and voltage
- Independent Operation
- Two-Phase Operation with Current Sharing
mode PWM controller to provide dual channel or single
outputs in two distinct operation modes. In independent
•
mode, the two PWM converters supply two independently
regulated voltages by converting a common or two differ-
Driving N-Channel MOSFETs
• 300kHz Constant Frequency Operation
• Built-in Feedback Compensation
ent power inputs. In two-phase mode, the two PWM converters supply one regulated voltage with programmable
current sharing control by converting a common or two
different power inputs. The two-phase mode can supply
- Voltage-Mode PWM Control
- Fast Transient Response
• ±1% VREF Accuracy Over Temperature
• Adjustable Output Voltage by an External Resistor
Divider
• Phase-Shifted Switchers to Minimize Ripple
• Current Limit with 50% Fold-Back
• Soft-Start and Enable Function
• Power-ON Reset (POR) Monitor
• Power Good Monitor for Outputs
the larger power than that provided each single channel.
APW1175 features an internal 300KHz oscillator, VCC
Power-On-Reset (POR), an external adjustable soft-start
and the programmable output current limit with 50% foldback. The two PWM controllers are 180o out of phase to
minimize the input ripple (common power input) and the
output ripple (two-phase mode).
Pin Description
Applications
•
•
•
•
VR EF
1
20
GN D
+IN 2
2
19
PW R GD
-IN 2
3
18
-IN 1
Graphics Cards
VC C
C L2-
4
17
5
16
SS/EN A
C L1-
DDR Memory
C L2+
BST2
6
15
7
14
C L1+
BST1
DH2
8
13
DH1
D L2
9
12
D L1
PGN D
10
11
BSTC
SSTL-2 Termination
Power Supply Requiring Two Outputs
Ordering and Marking Information
Package Code
K : SO P-20
Tem p. R ange
C : 0 to 70°C
Handling Code
TU : Tube
TR : Tape & R eel
Lead Free Code
L : Lead Free D evice
Blank : O rginal Device
)29 %#
Lead Free Code
Handling Code
Tem p. R ange
Package Code
APW 1175 K :
APW 1175
XXXXX
XXXXX - Date Code
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.3 - July., 2003
1
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APW1175
Block Diagram
VREF
-IN1
CL1-
CL1+
BSTC
Master Error
Amplifier
R
BST1
Q
S
V CL1
PWRGD
DH1
R
Q
0.125V
S
V REF
1.25V
DL1
0.125V
OSC
POWER-ON
RESET(POR)
VCC
GND
300KHZ
0.125V
soft-start
control
BST2
4V
25uA
S
DH2
Q
R
SS/ENA
DL2
V CL2
Slave Error
Amplifier
+IN2
PGND
CL2-
-IN2
CL2+
Absolute Maximum Ratings
Operating Conditions
•
VCC to GND . . . . . . . . . . . . . -0.3V ~ 15V
•
•
•
•
•
•
PGND to GND . . . . . . . . . . . . ±1V
•
•
•
•
BST to GND . . . . . . . . . . . . . -0.3V ~ 22V
Junction Temperature . . . . . . . 150oC
VCC . . . . . . . . . . . . . . . . . . . . 4.2V ~ 15V
BST. . . . . . . . . . . . . . . . . . . . . 5V ~ 17V
Ambient Temperature Range . . . 0oC to 85oC
Junction Temperature Range. . . . 0oC to 125oC
Storage Temperature . . . . . . . -65oC ~ 150oC
Soldering Temperature . . . 300oC , 10 Seconds
Minimum ESD Rating . . . . . . . ±3kV
Thermal Characteristics
Symbol
Parameter
Rating
Unit
R JA
Thermal Resistance in Free Air
SOIC
SOIC(with 3in of Copper)
75
65
°C/W
Copyright  ANPEC Electronics Corp.
Rev. A.3 - July., 2003
2
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APW1175
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC=4.75~5.25V, GND=PGND=0V, and T)=0~85°C.
Typical values refer to T)=25°C.
S ym b o l
P aram eter
AP W 1175
Test C o n d itio n s
M in
Typ
M ax
U n it
S U P P LY C U R R E N T
IC C
V C C S upply C urrent
IBST C
B S T C S upply C urrent
I B S T 1,2
B S T 1,2 S upply C urrent
P O W E R -O N R E S E T
V C C P O R T hreshold Voltage
V C C =5~15V , F O S C =300k H z
B S T C =5V , D L1,2=O pen,
F O S C =300k H z
B S T 1,2=10V , D H 1,2=O pen,
F O S C =300k H z
V C C R ising
9
mA
2.8
mA
1.6
mA
3.6
4.2
V
270
300
330
KHz
80
90
O S C IL L AT O R
F OSC
O scillator F requency
DH1
M axim um D uty C ycle
DH2
R am p A m plitude
∆ V OSC
E R R O R AM P L IF IE R
A OL
E rror A m plifier Voltage G ain
Input B ias C urrent
Input Voltage = 1.25V
(-IN 1, +IN 2, -IN 2)
R E F E R E N C E V O LTAG E
V REF
R eference Voltage
M easure P in 1
V R E F Load R egulation
I R E F = 1m A
V R E F Line R egulation
V C C = 5~15V
1.238
F old B ack Voltage K nee
V O U T =0 V
circuit)
V
35
dB
0.5
1
µA
1.250
1.262
V
mV
0.5
C urrent Lim it Voltage
F old B ack C urrent
1.1
3.5
P W M C O N T R O L L E R S G AT E D R IV E R S
B S T H -D H =5V
D H S ource
B S T H -D H =2.5V
D H -P G N D =3.5V
D H S ink
D H -P G N D =1.75V
B S T L-D L=5V
D L S ource
B S T L-D L=2.5V
D L-P G N D =3.5V
D L S ink
D L-P G N D =1.75V
D ead Tim e
C U R R E N T L IM IT P R O T E C T IO N
V CL
%
100
(refer
to
1
0.5
1
0.5
1
0.5
1
0.5
50
200
60
70
ap plica tio n
I=I LIM (refer to application circuit)
%
A
A
A
A
nS
80
50%
1.25
mV
I LIM
V OUT
V
S O F T -S TAR T
ISS
S oft-S tart C urrent
V S S =1V
25
µA
S oft-S tart Transition
S ynchronous P W M
3.3
V
Copyright  ANPEC Electronics Corp.
Rev. A.3 - July., 2003
3
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APW1175
Electrical Characteristics Cont.
Symbol
Parameter
Test Conditions
APW1175
Min
Typ
Max
Unit
POWER GOOD
Upper -IN1 Threshold
110%
VREF
Lower –IN1 Threshold
90%
VREF
Upper –IN2 Threshold
V+IN2
+0.1VREF
V
Lower –IN2 Threshold
90%
VREF
PWRGD Voltage Low
IPWRGD=-5mA
0.8
V
Functional Pin Description
VREF (Pin 1)
Internal 1.25V reference voltage . This pin is internally
connected to the positive input of the master channel
error amplifier.
+IN2 (Pin 2)
Positive input of the slave channel error amplifier. Connect this pin to 1.25V reference (Pin 1) for the two
independent channel configuration.
-IN2, -IN1 (Pin 3, 18)
Negative inputs of the slave and master error amplifier.
VCC (Pin 4)
Connect this pin to 5V~15 V power to provides the
bias for the control circuitry. Need a 1uF multi-layer
ceramic decoupling capacitor to GND (Pin 20). The
voltage at this pin is also monitored for Power-On
Reset (POR) purpose.
CL2-, CL2+, CL1+, CL1- (Pin 5,6,15,16)
Current sense input pins. Connect the positive and
negative inputs to output current sense resistor for
each channel. A current limit comparator for each
channel to limit the output current while the difference
voltage between the positive and negaive inputs is
greater than the 75mV reference.
A RC filter is required for noise rejection.
DH2, DH1 (Pin 8,13)
High-side MOSFET drivers to provide strong drive current
to drive each high-side MOSFET. A small series resistor
to the gate of the MOSFET maybe required for each pin.
DL2, DL1 (Pin 9,12)
Low-side MOSFET drivers to provide strong drive current
to drive each low-side MOSFET. A small series resistor
to the gate of the MOSFET maybe required for each pin.
PGND (Pin 10)
Power ground connection. The pin provide the path for
return of gate drive currents.
BSTC (Pin 11)
This pin provide supply voltage to the low-side MOSFET
drivers.
SS/ENA (Pin 17)
Connect a capacitor from this pin to ground.This
capacitor, along with an internal 25uA current source,
sets the soft-start interval, preventing the outputs from
overshoot as well as limiting the input current. Pull this
pin to below 1.4V to shutdown the outputs
PWRGD (Pin 19)
Power good signal output pin. This pin is an open collector output, which is pulled low if the output voltage is outside the power good window.
GND (Pin 20)
Signal ground for the control circuitry. All voltage levels
are measured with respect to this pin.
BST2,BST1 (Pin 7,14)
Power inputs to the high-side MOSFET drivers. A bootstrap circuit may be used to pump a boot voltage .
Copyright  ANPEC Electronics Corp.
Rev. A.3 - July., 2003
4
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APW1175
Typical Application
1. Independent Operation
+12V
+5V
+5V
16V
100uF
C1
16V
100uF
C2
16V
100uF
C3
C18
6V
150uF
C19
6V
150uF
C20
PW RO K
6V
150uF
R1
2 .2
R2
D1
1N 4148
D2
2 .2
C22
R13
1N 4148
1uF
2 .2
Q1
R3
C5
1uF
R4
2 .2
AP M 4416
Q2
7 .5 u H
L1
6V
150uF
C13
6V
150uF
C14
C12
6V
150uF
6V
150uF
C17
100
R10
C16
R9
6V
150uF
220
C15
R8
6V
150uF
124
124
R7
R6
2 .2
C7
0 .2 2 u F
C10
0 .2 2 u F
R5
C9
C4
10nF
6m
C6
10nF
C11
10nF
R12
C8
100
C23
1nF
R11
L2
4 .7 u H
6m
AP M 4416
Q4
100
10nF
0 .2 2 u F
AP M 4416
Q3
AP M 4416
2 .2
R15
1uF
C21
2 .2
R14
2 .5 V / 6 A
1 .8 V / 6 A
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Copyright  ANPEC Electronics Corp.
Rev. A.3 - July., 2003
GND
PW RGD
- IN 1
S S /E N A
C L1C L1+
BST1
DH1
DL1
BSTC
VREF
+ IN 2
- IN 2
VCC
C L2C L2+
BST2
DH2
DL2
PG ND
APW1175
Typical Application
2. Two-Phase Operation with Current Sharing Control
+12V
+5V
+5V
16 V
100uF
C1
16 V
100uF
C2
16 V
100uF
C3
C 12
6V
150uF
C 13
6V
150uF
C 14
PW ROK
6V
150uF
R1
2.2
R2
2.2
D1
1N 4148
22k
R 11
D2
Q1
R3
C5
1uF
R4
APM 4416
Q2
7 .5 u H
L1
R6
2.2
R5
C8
15 0
R8
12 4
6m
R 10
4 .7 u H
L2
R9
APM 4416
Q4
10 0
10nF
R7
C4
2.2
C7
6m
C6
10nF
C 17
10nF
0 .2 2 u F
10 0
2.2
R 14
1uF
C 18
0 .2 2 u F
APM 4416
Q3
APM 4416
1nF
C 16
R 12
1N 4148
1uF
C 15
2.2
2.2
R 13
6V
150uF
C9
6V
150uF
C 10
6V
150uF
C 11
2 .7 V / 1 2 A
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Copyright  ANPEC Electronics Corp.
Rev. A.3 - July., 2003
GND
PW RGD
- IN 1
S S /E N A
C L1C L1+
B ST1
DH1
DL1
BSTC
VREF
+ IN 2
- IN 2
VCC
C L2C L2+
B ST2
DH2
DL2
PGND
APW1175
Packaging Information
SO – 300mil ( Reference JEDEC Registration MS-013)
D
N
H
GAUGE
PLANE
E
1 2 3
A
B
e
Millimeters
Dim
Min.
Max.
A
2.35
2.65
A1
0.10
0.30
B
0.33
0.51
D
See variations
E
7.40
e
7.60
1.27BSC
L
Variations- D
Inches
Variations- D
Variations
Min.
Max.
Dim
SO-16
10.10
10.50
A
0.093
0.1043
SO-16
0.398
0.413
SO-18
11.35
11.76
A1
0.004
0.0120
SO-18
0.447
0.463
SO-20
12.60
13
B
0.013
0.020
SO-20
0.496
0.512
SO-24
15.20
15.60
D
See variations
SO-24
0.599
0.614
SO-28
17.70
18.11
E
SO-28
0.697
0.713
SO-14
8.80
9.20
e
SO-14
0.347
0.362
Min.
Max.
Variations
Min.
Max.
0.2914
0.2992
0.050BSC
H
10
10.65
H
0.394
0.419
L
0.40
1.27
L
0.016
0.050
N
See variations
N
See variations
0°
φ1
φ1
1
A1
8°
Copyright  ANPEC Electronics Corp.
Rev. A.3 - July., 2003
7
0°
8°
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APW1175
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb)
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
temperature
Reference JEDEC Standard J-STD-020A APRIL 1999
Peak temperature
183°C
Pre-heat temperature
Time
Classification Reflow Profiles
Convection or IR/
Convection
Average ramp-up rate(183°C to Peak)
3°C/second max.
120 seconds max
Preheat temperature 125 ± 25°C)
60 – 150 seconds
Temperature maintained above 183°C
Time within 5°C of actual peak temperature 10 –20 seconds
Peak temperature range
220 +5/-0°C or 235 +5/-0°C
Ramp-down rate
6 °C /second max.
6 minutes max.
Time 25°C to peak temperature
VPR
10 °C /second max.
60 seconds
215-219°C or 235 +5/-0°C
10 °C /second max.
Package Reflow Conditions
pkg. thickness ≥ 2.5mm
and all bgas
Convection 220 +5/-0 °C
VPR 215-219 °C
IR/Convection 220 +5/-0 °C
pkg. thickness < 2.5mm and
pkg. volume ≥ 350 mm³
Copyright  ANPEC Electronics Corp.
Rev. A.3 - July., 2003
8
pkg. thickness < 2.5mm and pkg.
volume < 350mm³
Convection 235 +5/-0 °C
VPR 235 +5/-0 °C
IR/Convection 235 +5/-0 °C
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APW1175
Reliability test program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C , 5 SEC
1000 Hrs Bias @ 125 °C
168 Hrs, 100 % RH , 121°C
-65°C ~ 150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms , IJH > 100mA
Carrier Tape
t
D
P
Po
E
P1
Bo
F
W
Ao
Ko
D1
T2
J
C
A
B
T1
Application
SOP- 20
A
B
330±1
62 ±1.5
C
12.75 +
0.15
F
D
D1
J
T1
T2
2 + 0.6 24.4 + 0.2 2 ± 0.2
Po
P1
Ao
11.5 ± 0.1 1.5 +0.1 1.5+ 0.25 4.0 ± 0.1 2.0 ± 0.1 8.2 ± 0.1
Copyright  ANPEC Electronics Corp.
Rev. A.3 - July., 2003
9
W
24 + 0.3
-0.1
Bo
13± 0.1
P
E
12 + 0.1 1.75± 0.1
Ko
t
0.35±0.01
2.5± 0.1
3
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APW1175
Cover Tape Dimensions
Application
SOP- 20
Carrier Width
24
Cover Tape Width
21.3
Devices Per Reel
1000
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright  ANPEC Electronics Corp.
Rev. A.3 - July., 2003
10
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