APW7098 Two- Phase Buck PWM Controller with Integrated MOSFET Drivers Features • • • • • • General Description - Fast Load Transient Response Operate with 8V~13.2VCC Supply Voltage Selectable External or Internal 0.6V Reference - ±1.5% Accuracy Over Temperature Support Single- and Two-Phase Operations 5VCC and Buffered Reference Outputs 8~12V Gate Drivers with Internal Bootstrap Diode • • Lossless Inductor DCR Current Sensing Selectable Operation Frequency • - 150k/300k/400kHz per Phase Power-OK Indicator Output • • • • • • • • The APW7098, two-phase PWM control IC, provides a precision voltage regulation system for advanced graphic microprocessors in graphics card applications. The integration of power MOSFET drivers into the controller IC and reduces the number of external parts for a cost and space saving power management solution. The APW7098 uses a voltage-mode PWM architecture, operating with fixed-frequency, to provides excellent load transient response. The device uses the voltage across the DCRs of the inductors for current sensing. Load line voltage positioning (DROOP), channel-current balance, and over-current protection are accomplished through continuous inductor DCR current sensing. The MODE pin programs single- or two- phase operation. When IC operates in two-phase mode normally, it can transfer two-phase mode to single-phase mode at liberty. Nevertheless, once operates in single-phase mode, the operation mode is latched. It is required to toggle SS, REFIN/EN or 5VCC pin to reset the IC. Such feature of the MODE pin makes the APW7098 ideally suitable for dual power input applications, such as PCIE interfaced graphic cards. This control IC‘s protection features include a set of sophisticated over-temperature, over-voltage, undervoltage, and over-current protections. Over-voltage results in the converter turning the lower MOSFETs on to clamp the rising output voltage and protects the microprocessor. The over-current protection level is set through external resistors. The device also provides a power-on-reset function and a programmable soft-start to prevent wrong operation and limit the input surge current during power-on or start-up. The APW7098 is available in a QFN4x4-24A package. Voltage-Mode Operation with Current Sharing - Adjustable Feedback Compensation - Regulated 1.5V on REFOUT/POK Adjustable Over-Current Protection (OCP) Accurate Load Line (DROOP) Programming Adjustable Soft-Start Over-Voltage Protection (OVP) Under-Voltage Protection (UVP) Over-Temperature Protection (OTP) QFN4x4 24-Lead Package (QFN4x4-24A) Lead Free and Green Devices Available (RoHS Compliant) Simplified Application Circuit VIN1 VOUT REFIN/EN REFOUT/POK APW7098 Applications VIN2 COMP FB • • Graphics Card GPU Core Power Supply Motherboard Chipset or DDR SDRAM Core Power • Supply On-board High Power PWM Converter with Output Current up to 60A ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 1 www.anpec.com.tw APW7098 Ordering and Marking Information Package Code QA : QFN4x4-24A Operating Ambient Temperature Range E : -20 to 70 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7098 Assembly Material Handling Code Temperature Range Package Code APW7098 QA : XXXXX - Date Code APW7098 XXXXX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). LGATE2 PHASE2 VCCDRV VCC PHASE1 LGATE1 Pin Configuration 24 23 22 21 20 19 18 UGATE2 UGATE1 1 BOOT1 2 17 BOOT2 5VCC 3 16 REFOUT/POK 25 PGND AGND 4 15 REFIN/EN MODE 5 14 SS CSP1 6 CSP2 COMP CSN1 RT 9 10 11 12 DROOP 8 CSN2 13 FB 7 QFN4x4-24A (Top View) Absolute Maximum Ratings Symbol VCC VBOOT1/2 (Note 1) Parameter Rating Unit VCC Supply Voltage (VCC to AGND) -0.3 ~ 15 V BOOT1/2 Voltage (BOOT1/2 to PHASE1/2) -0.3 ~ 15 V <200ns pulse width >200ns pulse width -5 ~ VBOOT1/2+5 -0.3 ~ VBOOT1/2+0.3 V <200ns pulse width >200ns pulse width -5 ~ VCC+5 -0.3 ~ VCC+0.3 V <200ns pulse width >200ns pulse width -10 ~ 30 -2 ~ 15 V UGATE1/2 Voltage (UGATE1/2 to PHASE1/2) LGATE1/2 Voltage (LGATE1/2 to PGND) PHASE1/2 Voltage (PHASE1/2 to PGND) Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 2 www.anpec.com.tw APW7098 Absolute Maximum Ratings (Cont.) Symbol (Note 1) Parameter Rating Unit -0.3 ~ 42 -0.3 ~ 30 V VCCDRV to AGND Voltage -0.3 ~ 15 V 5VCC Supply Voltage (5VCC to AGND, V5VCC < VCC +0.3V) -0.3 ~ 7 V REFIN/EN, MODE to AGND Voltage -0.3 ~ 7 V -0.3 ~ V5VCC +0.3 V BOOT1/2 to AGND Voltage <200ns pulse width >200ns pulse width V5VCC Input Voltage (REFOUT/POK, SS, FB, COMP, DROOP, RT, CSP1/2, CSN1/2 to AGND) PGND to AGND Voltage PDMAX Maximum Power Dissipation Maximum Junction Temperature TSTG Storage Temperature Range TSDR Maximum Soldering Temperature, 10 Seconds -0.3 ~ +0.3 V Limited Internally W 150 o -65 ~ 150 o 260 o C C C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA θJC Parameter Junction-to-Ambient Resistance Typical Value Unit (Note 2) QFN4x4-24A Junction-to-Case Resistance (Note 3) QFN4x4-24A 45 °C/W 7 Note 2 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of QFN4x4-24A is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the QFN4x4-24A package. Recommended Operating Conditions (Note 4) Symbol VCC Parameter VCC Supply Voltage Range Unit 8 ~ 13.2 V V5VCC 5VCC Supply Voltage (V5VCC < VCC +0.3V) 5 ± 5% V VOUT Converter Output Voltage 0.6 ~ 2.5 V VIN1 PWM 1 Converter Input Voltage 3.1 ~ 13.2 V VIN2 PWM 2 Converter Input Voltage 3.1 ~ 13.2 V IOUT Converter Output Current ~ 60 A VREFIN/EN REFIN/EN Input Voltage 0~2 V TA Ambient Temperature -20 ~ 70 o TJ Junction Temperature -20 ~ 125 o CVCC Linear Regulator Output Capacitor 0.8 ~ 15 µF C5VCC 5VCC Linear Regulator Output Capacitor 0.8 ~ 15 µF C C Note 4 : Refer to the typical application circuits. Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 3 www.anpec.com.tw APW7098 Electrical Characteristics Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=1.2V and TA= -20 ~ 70°C, unless otherwise specified. Typical values are at TA=25°C. The V5VCC is supplied by the internal regulator. Symbol Parameter APW7098 Test Conditions Unit Min. Typ. Max. SUPPLY CURRENT ICC VCC Nominal Supply Current UGATEx and LGATEx Open, FB forced above regulation point - 5 10 mA ISD VCC Shutdown Supply Current SS/EN=GND - 5 - mA POWER-ON-RESET (POR) AND OPERATION PHASE SELECTION V5VCC_THR 5VCC Rising Threshold Voltage 4.2 4.5 4.8 V 5VCC POR Hysteresis 0.4 0.58 0.76 V 0.77 0.8 0.83 V -100 - +100 nA MODE Rising Threshold Voltage IMODE VMODE Rising MODE Pin Input Current VCC LINEAR CONTROLLER VRRG_VCC Regulated Voltage on VCC IO=0A, RPULL-UP=1kΩ 8 8.5 9 V Maximum VCCDRV Sink Current VCC = VREG_VCC +200mV, VVCCDRV = 8V 5 - - mA 4.75 5 5.25 V 5VCC LINEAR REGULATOR VREG_5VCC Output Voltage IO = 0A, VCC =8V Line Regulation IO = 0A, VCC = 8V ~ 13.2V -20 - 20 mV Load Regulation IO = 3mA, VCC > 8V -200 - 200 mV Current-Limit 5VCC = GND 20 30 - mA - 0.6 - V -1 - +1 -1.5 - +1.5 -100 - +100 nA -5 - 5 mV 0.37 0.4 0.43 V - 50 - mV 2.1 2.5 3.0 V - 20 - µs -100 - +100 nA - 1.5 - V IO = 0~3mA, TA=25 C -2 - +2 IO = 0~3mA, Over temperature -3 - +3 REFOUT/POK Current-Limit REFOUT/POK = GND 4 8 15 mA REFOUT/POK Pull-Low Resistance IREFOUT/POK = 5mA - 70 100 Ω REFERENCE VOLTAGE VREF Regulated Voltage on FB pin Internal reference voltage used o Accuracy TA=25 C Over temperature IFB VREFIN/EN_THR FB Pin Input Current REFIN/EN Voltage Offset VFB - VREFIN/EN, VREFIN/EN =0.6V~1.5V Device Enable Voltage Threshold On REFIN/EN pin, VREFIN/EN rising Device Enable Voltage Hysteresis IREFIN/EN VPOK Internal/External Reference Selection Voltage Threshold On REFIN/EN pin Reference Selection Debounce Time VREFIN/EN falling, Switching to external reference REFIN/EN Pin Input Current REFOUT/POK Output Voltage o REFOUT/POK Accuracy Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 4 % % www.anpec.com.tw APW7098 Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=1.2V and TA= -20 ~ 70°C, unless otherwise specified. Typical values are at TA=25°C. The V5VCC is supplied by the internal regulator. Symbol Parameter APW7098 Test Conditions Unit Min. Typ. Max. - 85 - ERROR AMPLIFIER DC Gain RL = 10kΩ to the ground dB Gain-Bandwidth Product CL = 100pF, RL = 10kΩ to the ground - 20 - MHz Slew Rate CL = 100pF, IO = ±400µA - 8 - V/µs Upper Clamp Voltage IO = 1mA 2.7 3.0 - V Lower Clamp Voltage IO = -1mA - - 0.1 V COMP Pull-Low Resistance In fault or shutdown condition - 2 - kΩ RT = GND 135 150 165 RT = Floating 270 300 330 RT = 5VCC 360 400 440 - 1.5 - V RT Input Current RT = GND/5VCC(5V) -100 - +100 µA RT 5VCC Level For FOSC =150kHz V5VCC-0.5 - - V RT Floating Voltage For FOSC =300kHz 1.2 3.6 V5VCC-1.2 V RT GND Level For FOSC =400kHz - - 0.3 V 85 88 - % OSCILLATOR FOSC ∆VOSC1/2 IRT Oscillator Frequency Oscillator Sawtooth Amplitude Maximum Duty Cycle kHz MOSFET GATE DRIVERS TD UGATE1/2 Source Current VBOOT = 12V, VUGATE-VPHASE = 2V - 2.6 - A UGATE1/2 Sink Current VBOOT = 12V, VUGATE-VPHASE = 2V - 1 - A LGATE1/2 Source Current VCC = 12V, VLGATE = 2V - 2.6 - A LGATE1/2 Sink Current VCC =12V, VLGATE = 2V - 1.4 - A UGATE1/2 Source Resistance VBOOT = 12V, 100mA Source Current - 2.5 3.75 Ω UGATE1/2 Sink Resistance VBOOT = 12V, 100mA Sink Current - 2 3 Ω LGATE1/2 Source Resistance VCC = 12V, 100mA Source Current - 2 3 Ω LGATE1/2 Sink Resistance VCC = 12V, 100mA Sink Current - 1.4 2.1 Ω - 30 - ns -100 - +100 nA Dead-Time CURRENT SENSE AND DROOP FUNCTION ICSP CSP1/2 Pin Input Current ICSN CSN1/2 Maximum Output Current R CSN1/2 = 2kΩ, Sourcing current 80 - - Sinking current 15 - - - 3 - Current Sense Amplifier Bandwidth µA MHz DROOP Output Current Accuracy RDROOP = 2kΩ, VDROOP =0.005V - 50 - µA DROOP Accuracy ∆VFB = VDROOP/20, VDROOP = 1V -5 - +5 mV -10 - +10 % Current Difference Between Channel1/2 and Average Current Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 5 www.anpec.com.tw APW7098 Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=1.2V and TA= -20 ~ 70°C, unless otherwise specified. Typical values are at TA=25°C. The V5VCC is supplied by the internal regulator. Symbol Parameter APW7098 Test Conditions Unit Min. Typ. Max. 8 10 12 Soft-Start Complete Threshold - 3.2 - V SS Pull-low Resistance - 10 18 kΩ SOFT-START AND ENABLE ISS Soft-Start Current Source Flowing out of SS pin µA POWER-OK AND PROTECTIONS VUV Over-Current Trip Level ICS1 + ICS2 110 120 140 µA FB Under-Voltage Threshold ~ 2µs noise filter, VFB falling, Percentage of VR at Error Amplifier 40 50 60 % - 87.5 - % 115 125 135 % - 60 80 mV - 150 - o - o VPOK_L POK Lower Threshold VOV, VPOK_H FB Over-Voltage Threshold and POK Upper Threshold ~ 2µs noise filter, VFB rising Percentage of VR at Error Amplifier FB Over-Voltage Hysteresis TOTR Over-Temperature Trip Level TJ rising Over-Temperature Hysteresis Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 - 6 50 C C www.anpec.com.tw APW7098 Typical Operating Characteristics 5VCC Line Regulation 5VCC Load Regulation 6 VCC=12V, VIN=12V 5VCC Voltage,V5VCC (V) 5VCC Voltage,V5VCC (V) 6 5 4 3 2 5 4 3 2 1 1 0 0 0 2 4 6 8 10 12 0 14 5 10 Output Voltage Load Regulation 25 30 35 40 0.606 VCC=12V VCC=12V, VIN=12V Feedback Voltage,VFB (V) Feedback Voltage,VFB (V) 20 Output Voltage Line Regulation 0.606 0.604 0.602 0.6 0.598 0.604 0.602 0.6 0.598 0.596 0.596 0.594 0.594 0 10 20 30 40 5 50 6 7 Reference Voltage Accuracy Over Switching Frequency, FSW (kHz) 0.607 0.605 0.603 0.601 0.599 0.597 0.595 0.593 20 40 60 80 100 120 o 12 13 310 300 290 280 -20 0 20 40 60 80 100 120 o Junction Temperature, TJ ( C) Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 11 320 270 -40 0.591 0 10 330 0.609 -20 9 Switching Frequency Over Temperature Temperature -40 8 VIN Voltage,VIN (V) Output Current,IOUT (A) Reference Voltage,VREF (V) 15 5VCC Load Current ,I5VCC (mA) VCC Voltage,VCC (V) Junction Temperature, TJ ( C) 7 www.anpec.com.tw APW7098 Operating Waveforms Power On Power Off IOUT=10A IOUT=10A V5VCC V5VCC 1 1 VCOMP VCOMP 2 2 VSS VSS 3 3 VOUT 4 VOUT 4 CH1: V5VCC (5V/div) CH2: VCOMP (1V/div) CH3: VSS (5V/div) CH4: VOUT (1V/div) Time: 5ms/div CH1: V5VCC (5V/div) CH2: VCOMP (1V/div) CH3: VSS (5V/div) CH4: VOUT (1V/div) Time: 5ms/div Shutdown by REFIN/EN Pin Enable by REFIN/EN Pin IOUT=10A IOUT=10A VREFIN/EN VREFIN/EN 1 1 VCOMP VCOMP 2 2 VSS VSS 3 3 4 VOUT VOUT 4 CH1: VREFIN/EN (5V/div) CH2: VCOMP (1V/div) CH3: VSS (2V/div) CH4: VOUT (1V/div) Time: 5ms/div Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 CH1: VREFIN/EN (5V/div) CH2: VCOMP (1V/div) CH3: VSS (2V/div) CH4: VOUT (1V/div) Time: 5ms/div 8 www.anpec.com.tw APW7098 Operating Waveforms (Cont.) External Step-Up Reference by VREFIN/EN External Step-Down Reference by VREFIN/EN VREFIN/EN VREFIN/EN 1 1 VFB VFB VSS VSS 2 2 IOUT 3 IOUT 3 4 4 CH1: VREFIN/EN (1V/div) CH2: VFB (500mV/div) CH3: VSS (1V/div) CH4: IOUT (10A/div) Time: 200µs/div CH1: VREFIN/EN (1V/div) CH2: VFB (500mV/div) CH3: VSS (1V/div) CH4: IOUT (10A/div) Time: 200µs/div Power On Without VIN2 Voltage Under-Voltage Protection (UVP) VOUT VFB 1 1 VPHASE1 VPHASE1 2 2 VPHASE2 VPHASE2 3 3 4 Vss Vss 4 CH1: VOUT (1V/div) CH2: VPHASE1 (10V/div) CH3: VPHASE2 (2V/div) CH4: VSS (2V/div) Time: 5ms/div Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 CH1: VFB (500mV/div) CH2: VPHASE1 (10V/div) CH3: VPHASE2 (10V/div) CH4: VSS (2V/div) Time: 200µs/div 9 www.anpec.com.tw APW7098 Operating Waveforms (Cont.) Load Transient , 0A==>40A 1 2 Load Transient , 40A==>0A VPHASE1 VPHASE1 1 IPHASE2 IPHASE2 2 VOUT VOUT 3 3 IOUT RSEN=3kΩ L=0.56µH DCR=4mΩ RSEN=3kΩ L=0.56µH DCR=4mΩ IOUT 4 4 CH1: VPHASE1 (20V/div) CH2: IPHASE2 (20A/div) CH3: VOUT (AC, 200mV/div) CH4: IOUT (10A/div) Time: 20µs/div CH1: VPHASE1 (20V/div) CH2: IPHASE2(20A/div) CH3: VOUT (AC, 200mV/div) CH4: IOUT (10A/div) Time: 20µs/div OCP at Slow Slew IOUT RSEN=1.5kΩ L=0.56µH DCR=4mΩ Short-Circuit Test After Power On RSEN=1.5kΩ L=0.56µH DCR=4mΩ IL1 1 IL1 1 IL2 IL2 2 2 VSS 3 VOUT 4 VOUT 4 CH1: IL1 (10A/div) CH2: IL2 (10A/div) CH3: VSS (5V/div) CH4: VOUT (1V/div) Time: 5ms/div CH1: IL1 (10A/div) CH2: IL2 (10A/div) CH3: VSS (5V/div) CH4: VOUT (1V/div) Time: 5ms/div Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 VSS 3 10 www.anpec.com.tw APW7098 Operating Waveforms (Cont.) Short-Circuit Test Before Power On OVP After Power On RSEN=1.5kΩ L=0.56µH DCR=4mΩ Pull-Up VFB > V OV VSS 1 IL1 VFB 1 VLG1 2 IL2 3 2 VLG2 VSS 3 4 VOUT 4 CH1: VFB (1V/div) CH2: VSS (2V/div) CH3: VLG1 (10V/div) CH4: VLG2 (10V/div) Time: 100µs/div CH1: IL1 (10A/div) CH2: IL2 (10A/div) CH3: VSS (5V/div) CH4: VOUT (1V/div) Time: 5ms/div Pin Description PIN FUNCTION NO. NAME 1 UGATE1 High-side Gate Driver Output for channel 1. Connect this pin to the gate of high-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. 2 BOOT1 Bootstrap Supply for the floating high-side gate driver of channel 1. Connect the Bootstrap capacitor between the BOOT1 pin and the PHASE1 pin to form a bootstrap circuit. The bootstrap capacitor provides the charge to turn on the high-side MOSFET. Typical values for CBOOT ranged from 0.1µF to 1µF. Ensure that CBOOT is placed near the IC. 3 5VCC Internal Regulator Output. This is the output pin of the linear regulator, which is converting power from VCC and provides output current up to 20mA minimums for internal bias and external usage. 4 AGND Signal Ground for the IC. All voltage levels are measured with respect to this pin. Tie this pin to the ground island/plane through the lowest impedance connection available. 5 MODE Operation Phase Selection Input. Pulling this pin lower than 0.64V sets two-phase operation with both channels enabled. Pulling this pin higher than 0.8V sets single-phase operation with the channel 2 disabled. Once operating in single-phase mode, the operation mode is latched. It is required to toggle SS, REFIN/EN, or 5VCC pin to reset the IC. 6 CSP1 Positive Input of current sensing Amplifier for channel 1. This pin combined with CSN1 senses the inductor current through an RC network. 7 CSN1 Negative Input of current sensing amplifier for channel 1. This pin combined with CSP1 senses the inductor current through an RC network. 8 CSN2 Negative Input of current sensing amplifier for channel 2. This pin combined with CSP2 senses the inductor current through an RC network. 9 CSP2 Positive Input of current sensing Amplifier for Channel 2. This pin combined with CSN2 senses the inductor current through an RC network. Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 11 www.anpec.com.tw APW7098 Pin Description (Cont.) PIN NO. 10 FUNCTION NAME DROOP Load Line (droop) Setting. Connect a resistor between this pin and AGND to set the droop. A sourcing current, proportional to output current is present on the DROOP pin. The droop scale factor is set by the resistors (connected with CSP1, CSP2, and DROOP), resistance of the output inductors, and the internal voltage divider with the ratio of 5%. Operating Frequency Setting. The three-level input pin sets the operating frequency for each channel. RT Operating Frequency (kHz) GND 150 Floating 300 5VCC 400 Error Amplifier Output. Connect the compensation network between COMP, FB, and VOUT for Type 2 or Type 3 feedback compensation. 11 RT 12 COMP 13 FB Feedback Voltage. This pin is the inverting input to the error comparator. A resistor divider from the output to the AGND is used to set the regulation voltage. 14 SS Soft-start Current Output. Connect a capacitor from this pin to the AGND to set the soft-start interval. Pulling the voltage on this pin below 0.5V causes COMP to pull low and then shuts off the output. 15 REFIN/EN External Reference and Enable Input. The IC uses the voltage (VREFIN/EN) as reference voltage of the converter with soft-start control. If this pin is driven by an external voltage ranged from 0.4V to 2V. The IC is disabled if the voltage is below 0.4V (typical). If external reference is not available, then connect this pin to 5VCC for internal 0.6V reference. 16 REFOUT/PO K Power-OK and 1.5V Reference Output. This pin is a reference output used to indicate the status of the voltages on SS pin and FB pin. REFOUT/POK provides 1.5V reference if VFB> 87.5% of reference (VR). 17 BOOT2 Bootstrap Supply for the floating high-side gate driver of channel 2. Connect the Bootstrap capacitor between the BOOT2 pin and the PHASE2 pin to form a bootstrap circuit. The bootstrap capacitor provides the charge to turn on the high-side MOSFET. Typical values for CBOOT range from 0.1µF to 1µF. Ensure that CBOOT is placed near the IC. 18 UGATE2 High-side Gate Driver Output for Channel 2. Connect this pin to the gate of high-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. 19 PHASE2 Switch Node for Channel 2. Connect this pin to the source of high-side MOSFET and the drain of the low-side MOSFET. This pin is used as sink for UGATE2 driver. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. An Schottky diode between this pin and the ground is recommended to reduce negative transient voltage that is common in a power supply system. 20 LGATE2 Low-side Gate Driver Output for Channel 2. Connect this pin to the gate of low-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the low-side MOSFET has turned off. 21 VCCDRV Drive for External Linear Regulator. This pin is the drive output for the external linear regulator. Connect this pin to base/gate of NPN/NMOS transistor as the pass element. 22 VCC Supply Voltage. This pin along with VCCDRV pin and external pass element provides 8.5V regulated bias supply, low-side gate drivers, and the bootstrap circuit for high-side drivers. This pin can receive a well-decoupled 8V~13.2V supply voltage alone if the VCCDRV is left open. Ensure that this pin is bypassed by a ceramic capacitor next to the pin. 23 LGATE1 Low-side Gate Driver Output for Channel 1. Connect this pin to the gate of low-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the low-side MOSFET has turned off. Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 12 www.anpec.com.tw APW7098 Pin Description (Cont.) PIN NO. FUNCTION NAME 24 PHASE1 Switch Node for Channel 1. Connect this pin to the source of high-side MOSFET and the drain of the low-side MOSFET. This pin is used as sink for UGATT1 driver. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. An Schottky diode between this pin and the ground is recommended to reduce negative transient voltage, which is common in a power supply system. 25 PGND Power Ground for the low-side gate drivers. Connect this pin to the source of low-side MOSFETs. This pin is used as sink for LGATE1 and LGATE2 drivers. Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 13 www.anpec.com.tw APW7098 Block Diagram REFOUT/POK VCCDRV VCC VCC Linear Controller 8.5V 1.5V Reference VCC 5VCC Linear Regulator 5VCC 87.5% 125% OV Power-onReset UV V5VCC 50% Over-Temperature Protection FB Droop Control 0.6V VREF PGND SSEND DROOP '' L'' Control Logic Operation Phase Selection + ''H'' REFIN/EN 3.6V VR ISS 10µA Error Amplifier V5VCC-1V MODE SS Soft-Start 0.4V Selectable Oscillator and Sawtooth RT VCC COMP VOSC1 AGND VOSC2 VCC 150/300/400 kHz BOOT2 BOOT1 PWM Signal Controller UGATE2 PHASE2 UGATE1 VCC VCC LGATE2 PHASE1 LGATE1 120µA OC ICS1+ICS2 CSN2 CSP2 Current Sense ICS2 Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 Current Balance ICS1 ICS1+ICS2 14 Current Sense CSN1 CSP1 www.anpec.com.tw APW7098 Typical Application Circuits 1. APW7098 PWM Converter With 8V Gate Drive 5 R10 1.2kΩ VIN +12V R12 1kΩ C16 1µF BOOT1 21 22 C13 1µF 3 C14 1µF 15 14 C15 0.1µF VCCDRV PHASE1 FOSC=300kHz 10 R11 2kΩ 16 C2 22nF LGATE1 5VCC PGND R1 1.5kΩ R3 51Ω Q2 23 SS C6 1200µFx3 25 VOUT 1.2V C7 47µFx2 IOCP=45A REFIN/EN Q1 : APM4350KPx1 Q2 : APM4354KPx2 APW7098 RT UGATE2 18 DROOP PHASE2 19 C8 10µF C9 330µFx3 Q3 L2 0.56µH C10 0.1µF DCR=4mΩ REFOUT/POK CSP1 12 L1 0.56µH DCR=4mΩ LGATE2 13 R2 1.5kΩ 24 C5 0.1µF VCC C3 2.2nF R4 2kΩ Q1 1 BOOT2 17 11 C4 10µF MODE UGATE1 Q5 2N7002 2 CSN1 COMP CSP2 FB CSN2 Q4 20 R5 1.5kΩ 6 PHASE1 7 9 PHASE2 8 AGND 4 C1 10nF Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 R8 1.5kΩ 15 C12 0.1µF (X7R) R6 1.5kΩ R7 1.5kΩ C11 0.1µF (X7R) www.anpec.com.tw APW7098 Typical Application Circuits (Cont.) 2. APW7098 PWM Converter With 12V Gate Drive VIN +12V 5 BOOT1 22 C13 1µF 3 C14 1µF 15 14 C15 0.1µF VCCDRV PHASE1 FOSC=300kHz 10 R11 2kΩ 16 C2 22nF LGATE1 5VCC PGND R2 1.5kΩ R1 1.5kΩ R3 51Ω Q2 SS C6 1200uFx3 25 VOUT 1.2V C7 47µFx2 IOCP=45A Q1 : APM4350KPx1 Q2 : APM4354KPx2 APW7098 RT 17 UGATE2 18 DROOP PHASE2 REFOUT/POK CSP1 13 L1 0.56µH 23 REFIN/EN LGATE2 12 24 C5 0.1µF DCR=4mΩ C3 2.2nF R4 2kΩ Q1 1 VCC BOOT2 11 C4 10µF MODE UGATE1 21 2 CSN1 COMP CSP2 FB CSN2 19 C8 10µF Q3 4 Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 L2 0.56µH C10 0.1µF DCR=4mΩ Q4 20 R5 1.5kΩ 6 PHASE1 7 9 PHASE2 8 AGND C1 10nF C9 330µFx3 R8 1.5kΩ 16 C12 0.1µF (X7R) R6 1.5kΩ R7 1.5kΩ C11 0.1µF (X7R) www.anpec.com.tw APW7098 Function Description Voltage(V) VCC Linear Controller VCC The VCC linear-regulator controller is an analog gain block with an open-drain n-channel output. It drives an VSS external NPN or N-channel MOSFET pass transistor with a 1kΩ (typical) pull-up resistor and senses the feedback voltage via VCC pin. The regulator uses a 1µF (minimum) ceramic output capacitor and is designed to deliver V5VCC 5VCC POR VPOK 100mA (at 8.5V) for VCC. 1.5V VFB 0.6V VSS_VT 5VCC Linear Regulator 5VCC is the output terminal of the internal 5V linear regulator which regulates a 5V voltage on 5VCC by Time Figure 1. Power Sequence controlling an internal bypass transistor between VCC and 5VCC. The linear regulator powers the internal When soft-start is initiated, the internal 10µA current source starts to charge the capacitor. When the soft-start control circuitry and is stable with a low-ESR ceramic output capacitor. Bypass 5VCC to GND with a ceramic voltage across the soft-start capacitor reaches the enabled threshold about 0.8V (VSS_VT), the internal reference capacitor of at least 1µF. Place the capacitor physically close to the IC to provide good noise decoupling. The starts to rise and follows the soft-start voltage with converter operating at 150k/300k/400kHz PWM switching linear regulator can also provide output current up to 20mA for external loads. The linear regulator with current- frequency. When output voltage rises to 87.5% of the regulation voltage, the power-ok is enabled. The soft- limit protection can protect itself during over-load or shortcircuit conditions on 5VCC pin. The 5VCC linear regulator stops regulating in Over-Tem- start time (from the moment of enabling the IC to the moment when VPOK goes high) can be expressed as the following equation: perature Protection. When the junction temperature is cooled by 50oC, the 5VCC linear regulator starts to regu- TSS = late the output voltage again. CSS × (VSS_VT + VREF × 0.875) ISS where CSS= external soft-start capacitor 5VCC Power-On-Reset (POR) and REFIN/EN (External VSS_VT= internal soft-start threshold voltage, is about 0.8V Reference and Enable Input) Figure 1 shows the power sequence. The APW7098 VREF= 0.6V or the voltage on the REFIN/EN pin keeps monitoring the voltage on 5VCC pin to prevent ISS= soft-start current=10µA wrong logic operations which may occur when 5VCC voltage is not high enough for the internal control cir- During soft-start stage, the under-voltage protection is cuitry to operate. The 5VCC POR has a rising threshold of 4.6V (typical) with 0.58V of hysteresis. After the inhibited; however, the over-voltage and over-current protection functions are enabled. If the output capacitor has 5VCC voltage exceeds its rising Power-On-Reset (POR) voltage threshold, the IC starts a start-up pro- residue voltage before start-up, both lower and upper MOSFETs are in off-state until the internal soft-start volt- cess and then ramps up the output voltage to the setting of output voltage. The 5VCC POR signal resets the age equals to the FB pin voltage. This will ensure the output voltage starts from its existing voltage level. fault latch, set by the under-voltage or over-current event, when the signal is at a low level. Reference Voltage Selection and Shutdown Control The APW7098 features a reference selection function to use either internal 0.6V or external reference voltage. During the beginning of soft-start, the voltage on Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 17 www.anpec.com.tw APW7098 Function Description (Cont.) Reference Voltage Selection and Shutdown Control (Cont.) PCIE +12V VCC PWM 1 converter REFIN/EN pin determines which reference voltage is used. If this REFIN/EN pin is driven by an external voltage ranged from 0.4V to 2V, the IC uses the VREFIN/EN External Power voltage as reference voltage of the converter with softstart control. If external reference is not available, con- Operation Phase Selection MODE VIN2 PWM 2 converter PHASE2 nect this pin to 5VCC for internal 0.6V reference used. Once the internal or external reference is selected, the 4V reference source is latched. Cycling the POR signal resets the latch. VIN2 sensing circuit Figure 2. VIN2 Sensing Circuit The other function of REFIN/EN pin is used to enable or shut off the IC. Pulling the VREFIN/EN voltage below 0.4V Over-Voltage Protection (OVP) The over-voltage protection function monitors the output (typical) shuts down the two-phase PWM controller. In the shutdown mode, the two-phase UGATE and LGATE voltage through the FB pin. When the FB voltage increases over 125% of the reference voltage (VR) due to signals are pulled to PHASE and PGND respectively, the the high-side MOSFET failure or other reasons, the overvoltage protection comparator designed with a 2µs output is floating. noise filter will force the low-side MOSFET gate drivers high. This action actively pulls down the output voltage Operation Phase Selection The MODE pin programs single- or two- phase operation. It has a typical value for rising threshold of 0.8V, VMODE_THR, and eventually attempts to trigger the over-current shutdown of an ATX power supply. As soon as the output with 0.16V of hysteresis (0.64V), VMODE_THF. When the MODE voltage is within regulation, the OVP comparator is disengaged. The chip will restore its normal operation. pin voltage is higher than VMODE_THR, the device operates in single-phase; when the MODE pin voltage is lower When the OVP occurs, the REFOUT/POK will drop to low as well. This OVP scheme only clamps the voltage overshoot, than VMODE_THF and VIN2 supply voltage is above approximate 4V, the device operates in two-phase operation. This function makes the APW7098 ideally suitable for dual power input applications like PCIE interfaced graphic and does not invert the output voltage when otherwise activated with a continuously high output from low-side cards. The figure 2 shows the power sources of the two channels. The input power of PWM1 converter is supplied by PCIE bus power and the input power of PWM2 MOSFETs driver, which is a common problem for OVP schemes with a latch. Under-Voltage Protection (UVP) In the process of operation, when a short-circuit occurs, converter is supplied by an external power. If the input power connector of PWM2 converter is not plugged into the output voltage will drop quickly. Before the over-current protection responds, the output voltage will fall the socket before start-up, the internal VIN2 sensing circuit can sense the absence of VIN2 and set the IC to operate in out of the required regulation range. The under-voltage continually monitors the VFB voltage after soft-start is single-phase mode with PWM2 disabled. When the IC operates in two-phase mode, it can switch the operating completed. If a load step is strong enough to pull the output voltage lower than the under-voltage threshold, mode from two-phase to single-phase operation. Once operating in single-phase mode, the operation mode is the IC shuts down converter’s output. Cycling the 5VCC POR or REFIN/EN signal resets the fault latch and starts latched. It is required to toggle SS, REFIN/EN, or 5VCC pin to reset the IC. a start-up process. The under-voltage threshold is 50% of the nominal output voltage. The under-voltage comparator has a built-in 2µs noise filter to prevent the chips from wrong UVP shutdown being caused by noise. Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 18 www.anpec.com.tw APW7098 Function Description (Cont.) Current Sharing Over-Current Protection (OCP) The APW7098 uses inductor’s DCRs and external net- Figure 3 shows the circuit of sensing inductor current. Connecting a series resistor (R S) and a capacitor (C S) works to sense the both currents flowing through the inductors of the PWM1 and PWM2 channels. The current network in parallel with the inductor and measuring the voltage (VC) across the capacitor can sense the inductor current. sharing circuit, with closed-loop control, uses the sensed currents to adjust the two-phase inductor currents. For VL L example, if the sensed current of PWM1 is bigger than PWM2, the duty of PWM1 will decrease and the duty of DCR PHASE IL Rs PWM2 will increase. Then, the device will reduce IL1 current and increase IL2 current for current sharing. Cs DROOP VC CSP In some high current applications, a requirement on CSN precisely controlled output impedance is imposed. This dependence of output voltage on load current is often R2 termed droop regulation. As shown in figure 4, the droop control block generates Figure 3. Illustration of Inductor Current Sensing Circuit The equations of the sensing network are: a voltage through external resistor R DROOP and then set the droop voltage. The droop voltage, VDROOP , is VL (s)=IL (s) × (SL+DCR) VC(S) = VL(S) × proportional to the total current in two channels. As shown in the following equation: 1 IL(S) × (SL + DCR ) = 1 + SRSCS 1 + SRSCS VDROOP = 0.05 × [(ICS1 + ICS 2 ) × RDROOP ] Take L DCR for example, if the above equation is true, the voltage R SC S = The VDROOP voltage is used the regulator to adjust the output voltage, therefore, it is equal to the reference voltage minus the droop voltage. across the capacitor CS is equal to voltage drop across the inductor DCR, and the voltage VC is proportional to the current IL. The sensing current through the resistor R2 can be expressed as the following equation: ICS = Droop Control IL × DCR R2 VDROOP RDROOP where ICS is the sensed current VR VREFIN/EN or 0.6V IL is the inductor current DCR is the inductor resistance R2 is the sense resistor Figure 4. Illustration of Droop Setting Function The APW7098 is a two-phase PWM controller; therefore, the IC has two sensed current parts, ICS1 and ICS2. When ICS1 plus ICS2 is greater than 120µA, the over current occurs. In over-current protection, the IC shuts off the converter and then initials a new soft-start process. After 3 overcurrent events are counted, the device turns off both highside and low-side MOSFETs and the converter’s output is latched to be floating. Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 19 www.anpec.com.tw APW7098 Function Description (Cont.) Over-Temperature Protection (OTP) When the junction temperature increases above the rising threshold temperature TOTR, the IC will enter the overtemperature protection state that suspends the PWM, which forces the LGATE and UGATE gate drivers to output low voltages and turns off the 5VCC linear regulator output. The thermal sensor allows the converters to start a start-up process and regulate the output voltage again after the junction temperature cools by 50oC. The OTP is designed with a 50oC hysteresis to lower the average TJ during continuous thermal overload conditions, which increases lifetime of the APW7098. Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 20 www.anpec.com.tw APW7098 Application Information Output Voltage Setting FLC The output voltage is adjustable from 0.6V to 2.5V with a resistor-divider connected with FB, AGND, and converter’s output. Using 1% or better resistors for the -40dB/dec GAIN (dB) resistor-divider is recommended. The output voltage is determined by: R VOUT = 0.6 × 1 + TOP R GND FESR Where 0.6 is the reference voltage, RTOP is the resistor connected from converter’s output to FB, and RGND is the -20dB/dec resistor connected from FB to the the AGND. Suggested RGND is in the range from 1K to 20kΩ. To prevent stray pickup, locate resistors R TOP and R GND close to the APW7098. Frequency(Hz) Figure 6. Frequency Resopnse of the LC filters PWM Compensation The PWM modulator is shown in figure 7. The input is the output of the error amplifier and the output is the PHASE The output LC filter of a step down converter introduces a double pole, which contributes with -40dB/decade gain slope and 180 degrees phase shift in the control loop. A node. The transfer function of the PWM modulator is given by : compensation network among COMP, FB, and V OUT should be added. The compensation network is shown GAINPWM = in Figure 8. The output LC filters consists of the output inductors and output capacitors. For two-phase convertor, when assuming VIN1=VIN2=VIN, L1=L2=L, the transfer function of the LC filter is given by: OSC Driver Figure 7. The PWM Modulator The compensation network is shown in figure 8. It provides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. The transfer function of error amplifier is given by : V OUT GAINAMP L2=L COUT V PHASE2 1 1 // R2 + VCOMP sC1 sC2 = = 1 VOUT R1// R3 + sC3 1 1 s + × s + R2 × C2 (R1 + R3) × C3 R1 + R3 = × C1 + C2 1 R1× R3 × C1 s s + × s + R2 × C1× C2 R3 × C3 ESR Figure 5. The Output LC Filter Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 PHASE Output of Error Amplifier the ESR of the output capacitors. L1=L PWM Comparator ∆VOSC 2 The FLC is the double-pole frequency of the two-phase LC filters, and FESR is the frequency of the zero introduced by V PHASE1 VIN Driver 1 + s × ESR × COUT 1 s × L × COUT + s × ESR × COUT + 1 2 The poles and zero of this transfer functions are: 1 FLC = 1 2× π× L × COUT 2 1 FESR = 2 × π × ESR × COUT GAINLC = VIN ∆VOSC 21 www.anpec.com.tw APW7098 Application Information (Cont.) PWM Compensation (Cont.) 4. Set the pole at the ESR zero frequency FESR: The pole and zero frequencies of the transfer function FP1 = FESR Calculate the C1 by the following equation: are: FZ1 = 1 2 × π × R2 × C2 C1 = 1 2 × π × (R1+ R3) × C3 1 FP1 = C1× C2 2 × π × R2 × C1 + C2 1 FP2 = 2 × π × R3 × C3 FZ2 = 5. Set the second pole FP2 at the half of the switching frequency and also set the second zero FZ2 at the output LC filter double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at FP2 with the capabilities of the error amplifier. C1 R3 C3 C2 2 × π × R2 × C2 × FESR − 1 R2 FP2 = 0.5 X FSW C2 FZ2 = FLC VOUT R1 FB Combine the two equations will get the following component calculations: VCOMP VREF R3 = R1 FSW −1 2 × FLC C3 = 1 π × R3 × FSW Figure 8. Compensation Network The closed loop gain of the converter can be written as: GAINLC X GAINPWM X GAINAMP Figure 9. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to FZ1 FZ2 FP1 FP2 design the compensation network. Using the below guidelines should give a compensation similar to the GAIN (dB) curve plotted. A stable closed loop has a -20dB/ decade slope and a phase margin greater than 45 degree. Compensation Gain 20log (R2/R1) 20log (VIN/ΔVOSC) 1. Choose a value for R1, usually between 1K and 5K. 2. Select the desired zero crossover frequency FO= (1/5 ~ 1/10) X FSW FLC Use the following equation to calculate R2: FESR ∆VOSC FO R2 = × × R1 VIN FLC PWM & Filter Gain Frequency(Hz) 3. Place the first zero FZ1 before the output LC filter double pole frequency FLC. Figure 9. Converter Gain and Frequency FZ1 = 0.75 X FLC Calculate the C2 by the equation: Output Inductor Selection The duty cycle (D) of a buck converter is the function of the input voltage and output voltage. Once an output volt- 1 C2 = 2 × π × R2 × FLC × 0.75 Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 Converter Gain age is fixed, it can be written as: 22 www.anpec.com.tw APW7098 Application Information (Cont.) Output Inductor Selection (Cont.) D= caused by the AC peak-to-peak sum of the inductor’s current. The ripple voltage of output capacitors can be VOUT VIN represented by: For two-phase converter, the inductor value (L) determines the sum of the two inductor ripple currents, ∆IP-P, and af- ∆VESR fects the load transient reponse. Higher inductor value These two components constitute a large portion of the total output voltage ripple. In some applications, multiple reduces the output capacitors’ripple current and induces lower output ripple voltage. The ripple current can be capacitors have to be paralleled to achieve the desired ESR value. If the output of the converter has to support approxminated by: ∆IP - P = ∆ IP − P 8 × COUT × FSW = ∆IP − P × RESR ∆VCOUT = VIN - 2VOUT VOUT × FSW × L VIN Where FSW is the switching frequency of the regulator. Although the inductor value and frequency are increased and the ripple current and voltage are reduced, a tradeoff exists between the inductor’s ripple current and the regulator load transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. Increasing the switching frequency (FSW ) also reduces the ripple current and voltage, but it will increase the switching loss of the MOSFETs and the power dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been chosen, select an inductor that is capable of carrying the required peak current without going into saturation. In some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. This results in a larger output ripple voltage. another load with high pulsating current, more capacitors are needed in order to reduce the equivalent ESR and suppress the voltage ripple to a tolerable level. A small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors are also must be considered. To support a load transient that is faster than the switching frequency, more capacitors are needed for reducing the voltage excursion during load step change. For getting same load transient response, the output capacitance of two-phase converter only needs around half of output capacitance of single-phase converter. Another aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than the rated RMS current specified on the capacitors in order to prevent the capacitor from overheating. Input Capacitor Selection Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge cur- Output Capacitor Selection rent needed each time high-side MOSFET turns on. Place the small ceramic capacitors physically close to the Output voltage ripple and the transient voltage deviation are factors that have to be taken into con- MOSFETs and between the drain of high-side MOSFET and the source of low-side MOSFET. sideration when selecting output capacitors. Higher capacitor value and lower ESR reduce the output ripple The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable and the load transient drop. Therefore, selecting high performance low ESR capacitors is recommended for operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and larg- switching regulator applications. In addition to high frequency noise related to MOSFET turn-on and turn-off, est RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the the output voltage ripple includes the capacitance voltage drop ∆VCOUT and ESR voltage drop ∆V ESR maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. For two-phase converter, the Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 23 www.anpec.com.tw APW7098 Application Information (Cont.) 2 Input Capacitor Selection (Cont.) Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW RMS current of the bulk input capacitor is roughly calculated as the following equation : Plow-side = IOUT (1+ TC)(RDS(ON))(1-D) 2 IRMS where I IOUT = × 2D ⋅ (1 - 2D) 2 is the load current OUT TC is the temperature dependency of RDS(ON) FSW is the switching frequency For a through hole design, several electrolytic capacitors may be needed. For surface mount design, solid tan- tSW is the switching interval D is the duty cycle talum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. Note that both MOSFETs have conduction losses while the high-side MOSFET includes an additional transi- MOSFET Selection tion loss. The switching interval, t SW , is the function of The APW7098 requires two N-Channel power MOSFETs on each phase. These should be selected based upon the reverse transfer capacitance CRSS. The (1+TC) term is a factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs. Temperature” curve RDS(ON), gate supply requirements, and thermal management requirements. of the power MOSFET. In high-current applications, the MOSFET power dissipation, package selection, and heatsink are the domi- Layout Consideration In any high switching frequency converter, a correct layout nant design factors. The power dissipation includes two loss components, conduction loss, and switching loss. is important to ensure proper operation of the regulator. With power devices switching at higher frequency, the The conduction losses are the largest component of power dissipation for both the high-side and the low- resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit side MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equa- elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off condition, the tions below). Only the high-side MOSFET has switching losses since the low-side MOSFETs body diode or an MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is freewheeling external Schottky rectifier across the lower MOSFET clamps the switching node before the synchronous rec- by the low side MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike tifier turns on. These equations assume linear voltagecurrent transitions and do not adequately model power during the switching interval. In general, using short and wide printed circuit traces should minimize interconnect- loss due the reverse-recovery of the low-side MOSFET body diode. The gate-charge losses are dissipated by ing impedances and the magnitude of voltage spike. Besides, signal and power grounds are to be kept sepa- the APW7098 and don’t heat the MOSFETs. However, large gate-charge increases the switching interval, tSW rating and finally combined using ground plane construction or single point grounding. The best tie-point between which increases the high-side MOSFET switching losses. Ensure that all MOSFETs are within their maxi- the signal ground and the power ground is at the negative side of the output capacitor on each channel, where mum junction temperature at high ambient temperature by calculating the temperature rise according to package there is less noise. Noisy traces beneath the IC are not recommended. Figure 10. illustrates the layout, with bold thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, lines indicating high current paths; these traces must be short and wide. Components along the bold lines should package type, ambient temperature and air flow. For the high-side and low-side MOSFETs, the losses are be placed lose together. Below is a checklist for your layout: approximately given by the following equations: Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 24 www.anpec.com.tw APW7098 Application Information (Cont.) Layout Consideration (Cont.) • Keep the switching nodes (UGATEx, LGATEx, BOOTx, and PHASEx) away from sensitive small signal nodes APW7098 since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible and there should be no other weak signal traces in parallel with theses traces on any layer. V IN1=V IN BOOT1 • The signals going through theses traces have both high dv/dt and high di/dt with high peak charging and UGATE1 discharging current. The traces from the gate drivers to the MOSFETs (UGATEx and LGATEx) should be short • L1 PHASE1 and wide. Place the source of the high-side MOSFET and the LGATE1 drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane be- CSP1 tween the two pads reduces the voltage bounce of the node. In addition, the large layout plane between CSN2 CSP2 • For experiment result of accurate current sensing, the LGATE2 current sensing components are suggested to place • CS1 V OUT CSN1 the drain of the MOSFETs (VIN and PHASEx nodes) can get better heat sinking. • RS1 close to the inductor part. To avoid the noise interference, the current sensing trace should be away PHASE2 from the noisy switching nodes. Decoupling capacitors, the resistor-divider, and boot UGATE2 capacitor should be close to their pins. (For example, place the decoupling ceramic capacitor close to the BOOT2 CS2 L O A D RS2 L2 drain of the high-side MOSFET as close as possible). The input bulk capacitors should be close to the drain of the high-side MOSFET, and the output bulk capacitors should be close to the loads. The input capaci- VIN2 =V IN Figure 10. Layout Guidelines tor’s ground should be close to the grounds of the output capacitors and low-side MOSFET. • Locate the resistor-divider close to the FB pin to minimize the high impedance trace. In addition, FB pin traces can’t be close to the switching signal traces (UGATEx, LGATEx, BOOTx, and PHASEx). Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 25 www.anpec.com.tw APW7098 Package Information QFN4x4-24A D b E A Pin 1 A1 D2 A3 L K E2 Pin 1 Corner e S Y M B O L QFN4x4-24A MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.80 1.00 0.031 0.039 A1 0.00 0.05 0.000 A3 b D D2 0.30 0.008 0.012 3.90 4.10 0.154 0.161 2.00 2.50 0.079 0.098 0.161 0.098 0.18 E 3.90 4.10 0.154 E2 2.00 2.50 0.079 0.45 0.014 e L K 0.002 0.008 REF 0.20 REF 0.50 BSC 0.35 0.020 BSC 0.20 Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 0.018 0.008 26 www.anpec.com.tw APW7098 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application QFN4x4-24A A H T1 C 12.4+2.00 13.0+0.50 -0.00 -0.20 d D 1.5 MIN. 20.2 MIN. W E1 12.0±0.30 1.75±0.10 F 330.0±2.00 50 MIN. 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 4.30±0.20 4.30±0.20 1.30± 0.20 (mm) Devices Per Unit Package Type QFN4x4-24A Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 Quantity 3000 27 www.anpec.com.tw APW7098 Taping Direction Information QFN4x4-24A USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 28 www.anpec.com.tw APW7098 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak (Tp)* package body Temperature Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 3 Package Thickness <2.5 mm ≥2.5 mm Volume mm ≥350 220 °C 220 °C Volume mm <350 235 °C 220 °C Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 29 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW7098 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.6 - Oct., 2009 30 www.anpec.com.tw