Features • Designed to Store Configurator Programs for Field Programmable System Level • • • • • • • • Integrated Circuits (FPSLICs) In-System Programmable (ISP) via 2-wire Bus Spare Memory Available for System Parameters Storage Low-power CMOS EEPROM Process Available in 6 mm x 6 mm x 1 mm 8-lead LAP Package (Pin Compatible Across Product Family) Emulation of Atmel’s AT24CXXX Serial EEPROMs Available in 3.3V ± 10% LV Low-power Standby Mode High-reliability – Endurance: 100,000 Write Cycles – Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for Commercial Parts (at 70°C) Description The FPSLIC Support Devices provide an easy-to-use, cost-effective configuration memory for programming Field Programmable System Level Integrated Circuits by using a simple serial-access procedure to configure one or more FPSLIC devices. See Table 1 for a list of supported FPSLIC devices. The FPSLIC Support Device can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable. Table 1. ATFS FPSLIC Support Devices FPSLIC Device FPSLIC Support Device Configuration Data Spare Memory AT94K05 ATFS05 226520 Bits 35624 Bits AT94K10 ATFS10 430488 Bits 93800 Bits AT94K40 ATFS40 815382 Bits 233194 Bits Support Device ATFS05 ATFS10 ATFS40 Advance Information Pin Configurations 8-lead LAP DATA CLK RESET/OE CE 1 2 3 4 8 7 6 5 VCC SER_EN CEO (A2) GND Rev. 3017C–FPSLI–07/02 1 Block Diagram SER_EN PROGRAMMING DATA SHIFT REGISTER PROGRAMMING MODE LOGIC ROW ADDRESS COUNTER ROW DECODER BIT COUNTER POWER ON RESET EEPROM CELL MATRIX COLUMN DECODER TC CLK Device Description RESET/OE CE CEO(A2) DATA The control signals for the FPSLIC Support Device (CE, RESET/OE and CCLK) interface directly with the FPSLIC control signals. All FPSLIC devices can control the entire configuration process and retrieve data from the FPSLIC Support Device without requiring an external intelligent controller. The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven Low, the configuration EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the FPSLIC Support Device. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE. When the FPSLIC Support Device has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to avoid contention with other FPSLIC Support Devices. Upon power-up, the address counter is automatically reset. 2 ATFS05/10/40 3017C–FPSLI–07/02 ATFS05/10/40 Pin Description 8 LAP Pin Name I/O Description 1 DATA I/O Tri-state DATA output for configuration. Open-collector bi-directional pin for programming. 2 CLK I Clock input. Used to increment the internal address and bit counter for reading and programming. 3 RESET/OE I Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data output driver. 4 CE I Chip Enable input (active Low). A Low level (with OE High) allows DCLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the 2-wire Serial Programming mode ( SER_EN Low). 5 GND Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended. A2 I Device selection input, A2. This is used to enable (or select) the device during programming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor. 7 SER_EN I Serial enable must be held High during FPSLIC loading operations. Bringing SER_EN Low enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC. 8 VCC 6 +3.3V power supply pin 3 3017C–FPSLI–07/02 FPSLIC Master Serial Mode Summary The I/O and logic functions of the FPSLIC devices are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the mode pins. In Master Mode, the FPSLIC automatically loads the configuration program from an external memory. The FPSLIC Support Device has been designed for compatibility with the Master Mode. Control of Configuration Most connections between the FPSLIC device and the FPSLIC Support Device are simple and self-explanatory: • The DATA output of the FPSLIC Support Device drives DIN of the FPSLIC devices. • The master FPSLIC CCLK output drives the CLK input of the FPSLIC Support Device. • SER_EN must be connected to VCC (except during ISP). Programming Mode The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. Standby Mode The FPSLIC Support Device enters a low-power standby mode whenever CE is asserted High. In this mode, the ATFS05 consumes less than 50 µA of current at 3.3V. The output remains in a high-impedance state regardless of the state of the OE input. 4 ATFS05/10/40 3017C–FPSLI–07/02 ATFS05/10/40 Example Circuits Figure 1. FPSLIC Support Device for Programming FPSLIC Devices FPSLIC Support Device AT94K RESET RESET DATA CLK CE RESET/OE DATA0 CCLK CON INIT M2 M1 M0 VCC SER_EN GND The FPSLIC’s bi-directional CON pin drives the CE input of the FPSLIC Support Device, while the RESET/OE input is driven by the FPSLIC’s bi-directional INIT pin. This connection works under all normal circumstances, even when the user aborts the configuration before CON has gone High. A Low level on the RESET/OE input, during FPSLIC reset, clears the FPSLIC Support Device’s internal address pointer so that the reconfiguration starts at the beginning. The spare memory can be accessed by in-system programming the ATFS through a two-wire serial interface built in the FPSLIC device. For more information, refer to the “C Code for Interfacing the FPSLIC AVR Core to AT17 Series Configuration Memories” application note, available on the Atmel web site (www.atmel.com). Figure 2. In-System Programming of FPSLIC Support Devices VCC VCC 4.7 kW 4.7 kW DATA 1 CLK 3 2 5 6 7 8 9 10 4 VCC GND AT94K RESET RESET M2 M1 M0 DATA0 CCLK CON INIT FPSLIC Support Device DATA CLK CE RESET/OE SER_EN SER_EN GND 5 3017C–FPSLI–07/02 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125 °C Storage Temperature ..................................... -65 °C to +150°C Voltage on Any Pin with Respect to Ground ..............................-0.1V to VCC +0.5V Supply Voltage (VCC ) .........................................-0.5V to +7.0V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Maximum Soldering Temp. (10 sec. @ 1/16 in.)............. 260°C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V Operating Conditions ATFS05/10/40 Symbol VCC 6 Description Min Max Units Commercial Supply voltage relative to GND -0°C to +70°C 3.0 3.6 V Industrial Supply voltage relative to GND -40°C to +85°C 3.0 3.6 V ATFS05/10/40 3017C–FPSLI–07/02 ATFS05/10/40 DC Characteristics – ATFS05 VCC = 3.3V ± 10% Symbol Description Min Max Units VIH High-level Input Voltage 2.0 VCC V VIL Low-level Input Voltage 0 0.8 V VOH High-level Output Voltage (IOH = -2.5 mA) VOL Low-level Output Voltage (IOL = +3 mA) VOH High-level Output Voltage (IOH = -2 mA) VOL Low-level Output Voltage (IOL = +3 mA) ICCA Supply Current, Active Mode IL Input or Output Leakage Current (VIN = VCC or GND) ICCS Supply Current, Standby Mode 2.4 V Commercial 0.4 V 2.4 V Industrial 0.4 V 5 mA 10 µA Commercial 50 µA Industrial 100 µA -10 DC Characteristics – ATFS10/40 VCC = 3.3V ± 10% Symbol Description Min Max Units VIH High-level Input Voltage 2.0 VCC V VIL Low-level Input Voltage 0.0 0.8 V VOH High-level Output Voltage (IOH = -2.5 mA) VOL Low-level Output Voltage (IOL = +3 mA) VOH High-level Output Voltage (IOH = -2 mA) VOL Low-level Output Voltage (IOL = +3 mA) ICCA Supply Current, Active Mode IL Input or Output Leakage Current (VIN = VCC or GND) ICCS Supply Current, Standby Mode 2.4 V Commercial 0.4 2.4 V V Industrial 0.4 V 5 mA 10 µA Commercial 100 µA Industrial 100 µA -10 7 3017C–FPSLI–07/02 AC Characteristics CE TSCE TSCE THCE RESET/OE TLC THOE THC CLK TOE TCAC TOH TDF TCE DATA TOH AC Characteristics When Cascading RESET/OE CE CLK TCDF DATA LAST BIT TOCK FIRST BIT TOOE TOCE CEO TOCE 8 ATFS05/10/40 3017C–FPSLI–07/02 ATFS05/10/40 AC Characteristics for ATFS05 VCC = 3.3V ± 10% Commercial Symbol Description TOE(1) OE to Data Delay TCE(1) TCAC (1) TOH TDF Max Units 50 55 ns CE to Data Delay 60 60 ns CLK to Data Delay 75 80 ns Data Hold from CE, OE, or CLK (2) Min Max Industrial 0 CE or OE to Data Float Delay Min 0 ns 55 55 ns TLC CLK Low Time 25 25 ns THC CLK High Time 25 25 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 35 60 ns THCE CE Hold Time from CLK (to guarantee proper counting) 0 0 ns THOE OE High Time (guarantees counter is reset) 25 25 ns FMAX Maximum Input Clock Frequency 10 10 MHz Notes: 1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels. AC Characteristics for ATFS05 when Cascading VCC = 3.3V ± 10% Commercial Symbol TCDF (1) FMAX Note: Description Min CLK to Data Float Delay Maximum Input Clock Frequency Max Industrial Min 60 8 Max Units 60 ns 8 MHz 1. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels. 9 3017C–FPSLI–07/02 AC Characteristics for ATFS10/40 VCC = 3.3V ± 10% Commercial Symbol Description TOE(1) OE to Data Delay TCE(1) TCAC (1) TOH TDF Max Units 50 55 ns CE to Data Delay 55 60 ns CLK to Data Delay 55 60 ns Data Hold From CE, OE, or CLK (2) Min Max Industrial 0 Min 0 CE or OE to Data Float Delay ns 50 50 ns TLC CLK Low Time 25 25 ns THC CLK High Time 25 25 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 30 35 ns THCE CE Hold Time from CLK (to guarantee proper counting) 0 0 ns THOE OE High Time (guarantees counter is reset) 25 25 ns FMAX MAX Input Clock Frequency 15 10 MHz Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels. AC Characteristics for ATFS10/40 when Cascading VCC = 3.3V ± 10% Commercial Symbol TCDF (1) FMAX Note: 10 Description Min CLK to Data Float Delay MAX Input Clock Frequency Max Industrial Min 50 12.5 Max Units 50 ns 10 MHz 1. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels. ATFS05/10/40 3017C–FPSLI–07/02 ATFS05/10/40 Thermal Resistance Coefficients(1) Device Package Type ATFS05 Leadless Array Package (LAP) ATFS10/40 Leadless Array Package (LAP) Note: θJC [°C/W] θJA [°C/W] Airflow = 0 ft/min 8CN4 45 115.71 8CN4 45 135.71 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages” application note, available on the Atmel web site. 11 3017C–FPSLI–07/02 Ordering Information Package Operation Range ATFS05-CC ATFS10-CC ATFS40-CC 8CN4 8CN4 8CN4 Commercial (0°C to 70°C) ATFS05-CI ATFS10-CI ATFS40-CI 8CN4 8CN4 8CN4 Industrial (-40°C to 85°C) Ordering Code Package Type 8CN4 12 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP) ATFS05/10/40 3017C–FPSLI–07/02 ATFS05/10/40 Packaging Information 8CN4 – LAP Marked Pin1 Indentifier E A A1 D Top View Side View Pin1 Corner L1 0.10 mm TYP 8 1 e COMMON DIMENSIONS (Unit of Measure = mm) 2 7 3 6 b 5 4 e1 L Bottom View SYMBOL MIN NOM MAX A 0.94 1.04 1.14 A1 0.30 0.34 0.38 b 0.45 0.50 0.55 D 5.89 5.99 6.09 E 4.89 5.99 6.09 e 1.27 BSC e1 1.10 REF NOTE 1 L 0.95 1.00 1.05 1 L1 1.25 1.30 1.35 1 Note: 1. Metal Pad Dimensions. 11/14/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP) DRAWING NO. 8CN4 REV. A 13 3017C–FPSLI–07/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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