Features • Utilizes the AVR® Enhanced RISC Architecture • 121 Powerful Instructions - Most Single Clock Cycle Execution • 128K bytes of In-System Reprogrammable Flash ATmega103/L • • • • • • • • • • • • • • • • • 64K bytes of In-System Reprogrammable Flash ATmega603/L – SPI Interface for In-System Programming – Endurance: 1,000 Write/Erase Cycles 4K bytes EEPROM ATmega103/L 2K bytes of EEPROM ATmega603/L – Endurance: 100,000 Write/Erase Cycles 4K bytes Internal SRAM 32 x 8 General Purpose Working Registers + Peripheral Control Registers 32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines Programmable Serial UART + SPI Serial Interface VCC Supply – 2.7 - 3.6V ATmega603L/ATmega103L – 4.0 - 5.5V ATmega603/ATmega103 Fully Static Operation – 0 - 6 MHz ATmega603/ATmega103 – 0 - 4 MHz ATmega603L/ATmega103L Up to 6 MIPS Throughput at 6 MHz RTC with Separate Oscillator Two 8-Bit Timer/Counters with Separate Prescaler and PWM One 16-Bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and Dual 8-, 9- or 10-Bit PWM Programmable Watchdog Timer with On-Chip Oscillator On-Chip Analog Comparator 8-Channel, 10-Bit ADC Low Power Idle, Power Save and Power Down Modes Software Selectable Clock Frequency Programming Lock for Software Security Pin Configuration TQFP 8-Bit Microcontroller with 64K/128K Bytes In-System Programmable Flash ATmega603 ATmega603L ATmega103 ATmega103L Preliminary ATmega103/L ATmega103/L Rev. 0945BS–09/98 Note: This is a summary document. For the complete 92 page document, please visit our web site at 1 www.atmel.com or e-mail at [email protected] and request literature #0945B. Block Diagram Figure 1. The ATmega603/103 Block Diagram PF0 - PF7 PA0 - PA7 PC0 - PC7 PORTA DRIVER/BUFFERS PORTC DRIVERS VCC GND PORTF BUFFERS AVCC ANALOG MUX ADC DATA REGISTER PORTA DATA REGISTER PORTC DATA DIR. REG. PORTA 8-BIT DATA BUS AGND XTAL1 AREF INTERNAL OSCILLATOR OSCILLATOR XTAL1 PROGRAM COUNTER STACK POINTER WATCHDOG TIMER OSCILLATOR TOSC2 PROGRAM FLASH SRAM MCU CONTROL REGISTER TIMING AND CONTROL TOSC1 INSTRUCTION REGISTER INSTRUCTION DECODER + - ANALOG COMPARATOR CONTROL LINES DATA REGISTER PORTE DATA DIR. REG. PORTE RESET ALE TIMER/ COUNTERS GENERAL PURPOSE REGISTERS WR RD X Y Z INTERRUPT UNIT ALU EEPROM STATUS REGISTER PROGRAMMING LOGIC SPI UART DATA REGISTER PORTB DATA DIR. REG. PORTB PEN DATA REGISTER PORTD DATA DIR. REG. PORTD VCC PORTE DRIVER/BUFFERS PORTB DRIVER/BUFFERS PORTD DRIVER/BUFFERS GND PE0 - PE7 PB0 - PB7 PD0 - PD7 Description The ATmega603/103 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega603/103 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core is based on an enhanced RISC architecture that combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture 2 is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega603/103 provides the following features: 64K/128K bytes of In-system Programmable Flash, 2K/4K bytes EEPROM, 4K bytes SRAM, 32 general purpose I/O lines, 8 Input lines, 8 Output lines, 32 general purpose working registers, 4 flexible timer/counters with compare modes and PWM, UART, programmable Watchdog Timer with internal oscillator, an SPI serial port and three software selectable power saving modes. The Idle Mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The Power ATmega603(L) and ATmega103(L) ATmega603(L) and ATmega103(L) Down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power Save mode, the timer oscillator continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The device is manufactured using Atmel’s high-density non-volatile memory technology. The on-chip ISP Flash allows the program memory to be reprogrammed in-system through a serial interface or by a conventional nonvolatile memory programmer. By combining an 8-bit RISC CPU with a large array of ISP Flash on a monolithic chip, the Atmel ATmega603/103 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega603/103 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. Comparison Between ATmega 603 and ATmega 103 The ATmega603 has 64K bytes of In-System Programmable Flash, 2K bytes of EEPROM, and 4K bytes of internal SRAM. The ATmega603 does not have the ELPM instruction. The ATmega103 has 128K bytes of In-System Programmable Flash, 4K bytes of EEPROM, and 4K bytes of internal SRAM. The ATmega103 has the ELPM instruction, necessary to reach the upper half of the Flash memory for constant table lookup. Table 1 summarizes the different memory sizes for the two devices. Table 1. Memory Size Summary Part Flash EEPROM SRAM ATmega603 64K bytes 2K bytes 4K bytes ATmega103 128K bytes 4K bytes 4K bytes Pin Descriptions VCC Supply voltage GND Ground Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers can sink 20 mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. Port A serves as Multiplexed Address/Data bus when using external SRAM. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O pins with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source current if the pull-up resistors are activated. Port B also serves the functions of various special features. Port C (PC7..PC0) Port C is an 8-bit Output port. The Port C output buffers can sink 20 mA. Port C also serves as Address output when using external SRAM. Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Port D also serves the functions of various special features. Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port E output buffers can sink 20 mA. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. Port E also serves the functions of various special features. Port F (PF7..PF0) Port F is an 8-bit Input port. Port F also serves as the analog inputs for the ADC. RESET input. A low on this pin for two machine cycles while the oscillator is running resets the device. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier TOSC1 Input to the inverting Timer/Counter oscillator amplifier TOSC2 Output from the inverting Timer/Counter oscillator amplifier WR External SRAM Write Strobe. RD External SRAM Read Strobe. ALE ALE is the Address Latch Enable used when the External Memory is enabled. The ALE strobe is used to latch the low-order address (8 bits) into an address latch during the 3 first access cycle, and the AD0-7 pins are used for data during the second access cycle. Figure 3. External Clock Drive Configuration AVCC This is the supply voltage to the A/D Converter. It should be externally connected to V CC via a low-pass filter. See page 53 for details on operation of the ADC. NC XTAL2 AREF This is the analog reference input for the ADC converter. For ADC operations, a voltage in the range AGND to AVCC must be applied to this pin. EXTERNAL OSCILLATOR SIGNAL XTAL1 GND AGND If the board has a separate analog ground plane, this pin should be connected to this ground plane. Otherwise, connect to GND. PEN This is a programming enable pin for the low-voltage serial programming mode. By holding this pin low during a poweron reset, the device will enter the serial programming mode. Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3. For the Timer Oscillator pins, OSC1 and OSC2, the crystal is connected directly between the pins. No external capacitors are needed. The oscillator is optimized for use with a 32,768Hz watch crystal. An external clock signal applied to this pin goes through the same amplifier having a bandwidth of 256kHz. The external clock signal should therefore be in the interval 0Hz - 256kHz. Figure 2. Oscillator Connections C2 XTAL2 C1 XTAL1 ATmega603/103 Architectural Overview The fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look up function. These added function registers are the 16-bit X-register, Y-register and Z-register. The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 4 shows the ATmega603/103 AVR Enhanced RISC microcontroller architecture. In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses, allowing them to be accessed as though they were ordinary memory locations. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D-converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the register file, $20 - $5F. GND 4 ATmega603(L) and ATmega103(L) ATmega603(L) and ATmega103(L) Figure 4. The ATmega603/103 AVR Enhanced RISC Architecture AVR ATmega603/103 Architecture Data Bus 8-bit 32K/64K x 16 Program Memory Program Counter Status and Test 32 x 8 General Purpose Registers Instruction Register Peripherals IndirectAddressing Control Lines DirectAddressing Instruction Decoder ALU 4K x 8 Data SRAM 2K/4K x 8 EEPROM The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program memory is executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system programmable Flash memory. With a few exceptions, AVR instructions have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction. During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 16-bit stack pointer SP is read/write accessible in the I/O space. The 4000 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority. The memory spaces in the AVR architecture are all linear and regular memory maps. The General Purpose Register File Figure 5 shows the structure of the 32 general purpose working registers in the CPU. 5 ATmega603/103 Register Summary Address $3F ($5F) 6 Name SREG Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Page I T H S V N Z C page 14 page 14 $3E ($5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 $3D ($5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 14 $3C ($5C) XDIV XDIVEN XDIV6 XDIV5 XDIV4 XDIV3 XDIV2 XDIV1 XDIV0 page 16 page 15 $3B ($5B) RAMPZ $3A ($5A) EICR $39 ($59) EIMSK - - - - - - - RAMPZ0 ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 page 23 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 page 22 $38 ($58) EIFR INTF7 INTF6 INTF5 INTF4 - - - - page 22 $37 ($57) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 page 23 $36 ($56) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 page 24 $35 ($55) MCUCR SRE SRW SE SM1 SM0 - - - page 15 $34 ($54) MCUSR - - - - - - EXTRF PORF page 21 $33 ($53) TCCR0 - PWM0 COM01 COM00 CTC0 CS02 CS01 CS00 page 28 $32 ($52) TCNT0 Timer/Counter0 (8 Bit) $31 ($51) OCR0 Timer/Counter0 Output Compare Register page 30 $30 ($50) ASSR $2F ($4F) TCCR1A page 30 - - - - AS0 TCN0UB OCR0UB TCR0UB page 32 COM1A1 COM1A0 COM1B1 COM1B0 - - PWM11 PWM10 page 34 ICNC1 ICES1 - - CTC1 CS12 CS11 CS10 $2E ($4E) TCCR1B $2D ($4D) TCNT1H Timer/Counter1 - Counter Register High Byte page 36 $2C ($4C) TCNT1L Timer/Counter1 - Counter Register Low Byte page 36 $2B ($4B) OCR1AH Timer/Counter1 - Output Compare Register A High Byte page 37 $2A ($4A) OCR1AL Timer/Counter1 - Output Compare Register A Low Byte page 37 $29 ($49) OCR1BH Timer/Counter1 - Output Compare Register B High Byte page 37 $28 ($48) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte page 37 $27 ($47) ICR1H Timer/Counter1 - Input Capture Register High Byte page 37 $26 ($46) ICR1L Timer/Counter1 - Input Capture Register Low Byte $25 ($45) TCCR2 - PWM2 COM21 page 37 page 37 COM20 CTC2 CS22 CS21 CS20 page 28 $24 ($44) TCNT2 Timer/Counter2 (8 Bit) $23 ($43) OCR2 $21 ($47) WDTCR Timer/Counter2 Output Compare Register - $1F ($3F) EEARH $1E ($3E) EEARL EEPROM Address Register L $1D ($3D) EEDR EEPROM Data Register $1C ($3C) EECR - - - - EERIE EEMWE EEWE EERE $1B ($3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 page 57 $1A ($3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 page 57 $19 ($39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 page 57 $18 ($38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 59 $17 ($37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 59 $16 ($36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 59 $15 ($35) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 page 65 $12 ($32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 page 66 $11 ($31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 page 66 $10 ($30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 page 66 - - page 30 - page 30 WDTOE WDE WDP2 WDP1 WDP0 - EEAR11 EEAR10 EEAR9 EEAR8 page 40 page 41 page 41 page 41 SPI Data Register page 41 $0F ($2F) SPDR $0E ($2E) SPSR SPIF WCOL - - - - - - page 46 $0D ($2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 $0C ($2C) UDR $0B ($2B) USR RXC TXC UDRE FE OR - - - page 49 $0A ($2A) UCR RXCIE TXCIE UDRIE RXEN TXEN CHR9 RXB8 TXB8 page 50 $09 ($29) UBRR $08 ($28) ACSR ACO ACI ACIE ACIC ACIS1 ACIS0 page 52 UART I/O Data Register - page 45 page 49 UART Baud Rate Register ACD page 46 page 51 $07 ($27) ADMUX - - - - - MUX2 MUX1 MUX0 page 54 $06 ($26) ADCSR ADES ABSY ADRF ADIF ADIE ADPS2 ADPS1 ADPS0 page 54 $05 ($25) ADCH - - - - - - ADC9 ADC8 page 55 $04 ($24) ADCL ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 page 55 $03 ($23) PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 page 69 $02 ($22) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 page 69 $01 ($21) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 page 69 $00 ($20) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 page 73 ATmega603(L) and ATmega103(L) ATmega603(L) and ATmega103(L) ATmega603/103 Instruction Set Summary Mnemonics Operands Description Operation Flags Rd ← Rd + Rr Z,C,N,V,H #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract Constant from Register SBC Rd, Rr Subtract with Carry two Registers SBCI Rd, K Subtract with Carry Constant from Reg. SBIW Rdl,K AND ANDI OR Rd, Rr Logical OR Registers ORI Rd, K Logical OR Register and Constant Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd - Rr Rd ← Rd - K 1 Z,C,N,V,H 1 Z,C,N,V,S 2 Z,C,N,V,H 1 Z,C,N,V,H 1 Rd ← Rd - Rr - C Z,C,N,V,H 1 Z,C,N,V,H 1 Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 Rd, Rr Logical AND Registers Rd Z,N,V 1 Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 Z,N,V 1 Rd ← Rd v K Z,N,V 1 Z,N,V 1 EOR Rd, Rr Exclusive OR Registers COM Rd One’s Complement NEG Rd Two’s Complement SBR Rd,K Set Bit(s) in Register CBR Rd,K Clear Bit(s) in Register INC Rd Increment DEC Rd Decrement TST Rd Test for Zero or Minus CLR Rd Clear Register SER Rd Set Register Rd ← Rd - K - C ← Rd • Rr Rd ← Rd v Rr Rd ← Rd ⊕ Rr Rd ← $FF - Rd Z,C,N,V 1 Rd ← $00 - Rd Z,C,N,V,H 1 Z,N,V 1 Rd ← Rd • ($FF - K) Z,N,V 1 Z,N,V 1 Z,N,V 1 Rd ← Rd v K Rd ← Rd + 1 Rd ← Rd - 1 Rd ← Rd • Rd Z,N,V 1 Rd Z,N,V 1 None 1 ← Rd ⊕ Rd Rd ← $FF BRANCH INSTRUCTIONS RJMP k IJMP Relative Jump Indirect Jump to (Z) JMP k Direct Jump RCALL k Relative Subroutine Call ICALL CALL Indirect Call to (Z) k Direct Subroutine Call RET Subroutine Return RETI Interrupt Return PC ← PC + k + 1 PC ← Z PC ← k PC ← PC + k + 1 PC ← Z PC ← k PC ← STACK PC ← STACK None 2 None 2 None 3 None 3 None 3 None 4 None 4 I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None CP Rd,Rr Compare Rd - Rr Z, N,V,C,H CPC Rd,Rr Compare with Carry Rd - Rr - C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd - K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared SBRS Rr, b Skip if Bit in Register is Set SBIC P, b Skip if Bit in I/O Register Cleared SBIS P, b Skip if Bit in I/O Register is Set BRBS s, k Branch if Status Flag Set BRBC s, k Branch if Status Flag Cleared BREQ k Branch if Equal BRNE k Branch if Not Equal BRCS k Branch if Carry Set BRCC k Branch if Carry Cleared BRSH k Branch if Same or Higher BRLO k Branch if Lower BRMI k Branch if Minus BRPL k Branch if Plus BRGE k Branch if Greater or Equal, Signed BRLT k Branch if Less Than Zero, Signed BRHS k Branch if Half Carry Flag Set BRHC k Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3 if (P(b)=0) PC ← PC + 2 or 3 if (P(b)=1) PC ← PC + 2 or 3 if (SREG(s) = 1) then PC←PC+k + 1 if (SREG(s) = 0) then PC←PC+k + 1 if (Z = 1) then PC ← PC + k + 1 if (Z = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (N = 1) then PC ← PC + k + 1 if (N = 0) then PC ← PC + k + 1 if (N ⊕ V= 0) then PC ← PC + k + 1 if (N ⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC ← PC + k + 1 if (H = 0) then PC ← PC + k + 1 if (T = 1) then PC ← PC + k + 1 if (T = 0) then PC ← PC + k + 1 if (V = 1) then PC ← PC + k + 1 if (V = 0) then PC ← PC + k + 1 if ( I = 1) then PC ← PC + k + 1 if ( I = 0) then PC ← PC + k + 1 1/2 1 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 None 1/2 7 ATmega603/103 Instruction Set Summary (Continued) DATA TRANSFER INSTRUCTIONS ELPM() Extended Load Program Memory MOV Rd, Rr Move Between Registers LDI Rd, K Load Immediate LD Rd, X Load Indirect LD Rd, X+ Load Indirect and Post-Inc. LD Rd, - X Load Indirect and Pre-Dec. LD Rd, Y Load Indirect LD Rd, Y+ Load Indirect and Post-Inc. LD Rd, - Y Load Indirect and Pre-Dec. LDD Rd,Y+q Load Indirect with Displacement LD Rd, Z Load Indirect R0 ← (Z+RAMPZ) 1 Rd None 1 None 2 IN Rd, P In Port OUT P, Rr Out Port PUSH Rr Push Register on Stack POP Rd Pop Register from Stack I/O(P,b) ← 1 LD Rd, Z+ Load Indirect and Post-Inc. Rd, -Z Load Indirect and Pre-Dec. LDD Rd, Z+q Load Indirect with Displacement LDS Rd, k Load Direct from SRAM ST X, Rr Store Indirect ST X+, Rr Store Indirect and Post-Inc. ST - X, Rr Store Indirect and Pre-Dec. ST Y, Rr Store Indirect ST Y+, Rr Store Indirect and Post-Inc. ST - Y, Rr Store Indirect and Pre-Dec. STD Y+q,Rr Store Indirect with Displacement ST Z, Rr Store Indirect ST Z+, Rr Store Indirect and Post-Inc. ST -Z, Rr Store Indirect and Pre-Dec. STD Z+q,Rr Store Indirect with Displacement STS k, Rr Store Direct to SRAM LPM Load Program Memory 3 None ←K Rd ← (X) Rd ← (X), X ← X + 1 X ← X - 1, Rd ← (X) Rd ← (Y) Rd ← (Y), Y ← Y + 1 Y ← Y - 1, Rd ← (Y) Rd ← (Y + q) Rd ← (Z) Rd ← (Z), Z ← Z+1 Z ← Z - 1, Rd ← (Z) Rd ← (Z + q) Rd ← (k) (X) ← Rr (X) ← Rr, X ← X + 1 X ← X - 1, (X) ← Rr (Y) ← Rr (Y) ← Rr, Y ← Y + 1 Y ← Y - 1, (Y) ← Rr (Y + q) ← Rr (Z) ← Rr (Z) ← Rr, Z ← Z + 1 Z ← Z - 1, (Z) ← Rr (Z + q) ← Rr (k) ← Rr R0 ← (Z) Rd ← P P ← Rr STACK ← Rr Rd ← STACK LD None Rd ← Rr None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 2 None 3 None 1 None 1 None 2 None 2 None 2 None 2 Z,C,N,V 1 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register CBI P,b Clear Bit in I/O Register LSL Rd Logical Shift Left LSR Rd Logical Shift Right ROL Rd Rotate Left Through Carry ROR Rd Rotate Right Through Carry ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Flag Set BCLR s Flag Clear BST Rr, b Bit Store from Register to T BLD Rd, b Bit load from T to Register SEC Set Carry CLC Clear Carry SEN Set Negative Flag CLN Clear Negative Flag SEZ Set Zero Flag CLZ Clear Zero Flag SEI Global Interrupt Enable CLI Global Interrupt Disable SES Set Signed Test Flag CLS Clear Signed Test Flag SEV Set Twos Complement Overflow. CLV Clear Twos Complement Overflow SET Set T in SREG CLT Clear T in SREG I/O(P,b) ← 0 Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← Rd(n+1), Rd(7) ← 0 Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Rd(n) ← Rd(n+1), n=0..6 Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) Z,C,N,V 1 Z,C,N,V 1 Z,C,N,V 1 Z,C,N,V 1 None 1 SREG(s) ← 1 SREG(s) 1 SREG(s) 1 T ← Rr(b) T 1 None 1 SREG(s) ← 0 Rd(b) ← T C←1 C 1 C←0 C 1 N 1 N←0 N 1 Z 1 Z←0 Z 1 I 1 I 1 N←1 Z←1 I←1 I←0 S←1 S 1 S←0 S 1 V 1 V←0 V 1 T 1 T←0 T 1 H 1 H←0 H 1 V←1 T←1 H←1 SEH Set Half Carry Flag in SREG CLH Clear Half Carry Flag in SREG NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 3 WDR Watchdog Reset (see specific descr. for WD timer) None 1 8 ATmega603(L) and ATmega103(L) ATmega603(L) and ATmega103(L) Ordering Information Speed (MHz) Power Supply 4 2.7 - 3.6V 6 4 6 4.0 - 5.5V 2.7 - 3.6V 4.0 - 5.5V Ordering Code Package Operation Range ATmega603L-4AC 64A Commercial (0°C to 70°C) ATmega603L-4AI 64A Industrial (-40°C to 85°C) ATmega603-6AC 64A Commercial (0°C to 70°C) ATmega603-6AI 64A Industrial (-40°C to 85°C) ATmega103L-4AC 64A Commercial (0°C to 70°C) ATmega103L-4AI 64A Industrial (-40°C to 85°C) ATmega103-6AC 64A Commercial (0°C to 70°C) ATmega103-6AI 64A Industrial (-40°C to 85°C) Package Type 64A 64-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 9 Packaging Information 64A, 64-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches)* 16.25(0.640) SQ 15.75(0.620) PIN 1 ID 0.45(0.018) 0.30(0.012) 0.80(0.031) BSC 14.10(0.555) SQ 13.90(0.547) 0.20(0.008) 0.10(0.004) 1.20 (.047) MAX 0-7 0.75(0.030) 0.45(0.018) 0.15(0.006) 0.05(0.002 ) *Controlling dimension: millimeters 10 ATmega603(L) and ATmega103(L)