1/4 STRUCTURE Silicon Monolithic Integrated Circuit NAME OF PRODUCT DC-AC Inverter Control IC TYPE ＢＤ９８９８Ｆ、ＢＤ９８９８ＦＶ FUNCTION ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ 36V High voltage process 1ch control with Full-Bridge Lamp current and voltage sense feed back control Sequencing easily achieved with Soft Start Control Short circuit protection with Timer Latch Under Voltage Lock Out Mode-selectable the operating or stand-by mode by stand-by pin For slave IC, Synchronous operating with BD9215F/FV BURST mode controlled by PWM and DC input Output liner Control by external DC voltage ○Absolute Maximum Ratings（Ta = 25℃） Parameter Supply Voltage BST pin SW pin BST-SW voltage difference Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Power Dissipation Symbol VCC BST SW BST-SW Topr Tstg Tjmax Pd Limits 36 40 36 15 -40～+85 -55～+150 +150 749*1(BD9898F) 1062*2(BD9898FV) Unit V V V V ℃ ℃ ℃ mW *1 Pd derate at 6.0mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm) *2 Pd derate at 8.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm) 〇Operating condition Parameter Supply voltage BST voltage BST-SW voltage difference DRIVER frequency BCT oscillation frequency Symbol Limits Unit VCC BST BST-SW FOUT fBCT 16.0～30.0 ※ 5.0～37.5 5.0～14.0 30～110 0.05～1.00 V V V kHz kHz ※For Operation condition of Supply voltage, Please see NOTE FOR USE(4page), more information. Status of this document The Japanese version of this document is the official specification. Please use the translation version of this document as a reference to expedite understanding of the official version. If these are any uncertainty in translation version of this document, official version takes priority. REV. B 2/4 ○Electric Characteristics（Ta=25℃、VCC=24V、STB=UVLO=3.0V） Parameter （（WHOLE DEVICE）） Operating current Stand-by current （（STAND BY CONTROL）） Stand-by voltage H Stand-by voltage L （（UVLO BLOCK））） Operating voltage (UVLO) Hesteresis width (UVLO) （（REG BLOCK）） REG output voltage REG source current （（OSC BLOCK）） RT pin Voltage Soft start current SS operation start Voltage SS term END Voltage SRT ON resistance （（BOSC BLOCK）） BOSC Max voltage BOSC Min voltage BOSC constant current BOSC frequency （（FEED BACK BLOCK）） IS threshold voltage 1 IS threshold voltage 2 VS threshold voltage IS source current 1 IS source current 2 VS source current IS COMP detect voltage 1 IS COMP detect voltage 2 VREF input voltage range （（OUTPUT BLOCK）） LN output sink resistance LN output source resistance HN output sink resistance HN output source resistance MAX DUTY OFF period Drive output frequency （（TIMER LATCH BLOCK）） Timer Latch setting voltage Timer Latch setting current （（COMP BLOCK）） COMP over voltage detect voltage Hysterisis width (COMP) ((Synchronous Block)) High voltage Low voltage CT_SYNC_OUT sink resistance CT_SYNC_OUT source resistance High voltage input range Low voltage input range Symbol MIN. Limits TYP. MAX. Unit Icc1 Icc2 － － 5.5 60 10 140 mA μA VstH VstL 2 -0.3 － － VCC 0.8 V V Vuvlo ⊿Vuvlo 2.16 0.085 2.25 0.110 2.34 0.135 V V VREG IREG 7.35 20 7.50 － 7.65 － V mA VRT ISS VSS_ST VSS_ED RSRT 1.05 1.7 0.18 1.35 － 1.50 2.2 0.20 1.50 85 1.95 2.7 0.22 1.65 170 V μA V V Ω VBCTH VBCTL IBCT fBCT 1.94 0.4 1.35/BRT 291 2 0.5 1.5/BRT 300 2.06 0.6 1.65/BRT 309 V V A Hz VIS1 VIS2 VVS IIS1 IIS2 IVS VISCOMP1 VISCOMP2 VREFIN 1.225 － 1.22 － 40 － 0.606 － 0.6 1.25 VREFIN 1.25 － 50 － 0.625 0.50 － 1.275 VIS1 1.28 0.9 60 0.9 0.644 － 1.6 V V V μA μA μA V V V RsinkLN RsourceLN RsinkHN RsourceLN MAX DUTY TOFF FOUT 1.8 4.5 1.8 4.5 46.0 100 57.9 3.5 9.0 3.5 9.0 48.5 200 60 7.0 18.0 7.0 18.0 49.5 400 62.1 Ω Ω Ω Ω % ns kHz VCP ICP 3.88 1.6 4.0 2.1 4.12 2.6 V μA VCOMPH ⊿VCOMPH 3.88 0.15 4.0 0.20 4.12 0.25 V V VCT_SYNCH VCT_SYNCL 3.8 － － － 2.5 -0.3 4.0 － 150 300 － － 4.2 0.5 300 400 V V Ω Ω V V RSYNC_OUT_sink RSYNC_OUT_source VCT_SYNC_IN_H VCT_SYNC_IN_L （This product is not designed to be radiation-resistant.） REV. B VCT_SYNCH 1 Conditions FOUT=60kHz, FB=GND, BST=OPEN System ＯＮ System ＯＦＦ fBCT=0.3kHz fBCT=0.3kHz VBCT=0.2V (BRT=37.8kΩ BCT=0.047μF) VREF applying voltage DUTY=2.2V DUTY=0V IS=1.0V VREFIN≧1.25V VREFIN= 1V No effect at VREF＞1.25V VBST-VSW=7.0V VBST-VSW=7.0V FOUT=60kHz RT=21k Ω VSS＞1.65V 3/4 〇Package Dimensions Device Mark BD9898FV BD9898F １ １ Lot No. SSOP-B28 (Unit:mm) SOP28 (Unit:mm) 〇Pin Description PIN No. PIN NAME 1 PGND 2 LN2 NMOS FET driver 3 HN2 NMOS FET driver 4 SW2 Lower rail voltage for HN2 output 5 BST2 Boot-Strap input for HN2 output 6 CT_SYNC_IN CT synchronous signal input pin 7 CT_SYNC_OUT 8 SRT 〇Block Diagram REV. B FUNCTION Ground for FET drivers CT synchronous signal output pin External adjusting External adjusting resistor from SRT to RT for the start-up triangle oscillator resistor from RT to GND for the triangle oscillator 9 RT 10 GND 11 BCT 12 BRT 13 DUTY 14 STB 15 CP 16 VREF 17 VS Error amplifier input 18 IS Error amplifier input 19 FB Error amplifier output 20 SS External capacitor from SS to GND for Soft Start Control 21 COMP 22 VCC 23 UVLO 24 REG Internal regulator output 25 BST1 Boot-Strap input for HN1 output 26 SW1 Lower rail voltage for HN1 output 27 HN1 NMOS FET driver 28 LN1 NMOS FET driver GROUND External capacitor from BCT to GND for adjusting the BURST triangle oscillator External resistor from BRT to GND for adjusting the BURST triangle oscillator Control PWM mode and BURST mode Stand-by switch External capacitor from CP to GND for Timer Latch Reference voltage input pin for Error amplifier Over voltage detect pin Supply voltage input External Under Voltage Lock Out 4/4 〇NOTE FOR USE １. This product is produced with strict quality control, but might be destroyed if used beyond its absolute maximum ratings. Once IC is destroyed, failure mode will be difficult to determine, like short mode or open mode. Therefore, physical protection countermeasure, like fuse is recommended in case operating conditions go beyond the expected absolute maximum ratings. ２. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however the variation will be small. When it is used in between STB-UVLO Diode short etc., the IC can operate VCC≧9V. Please refer to a Technical Note in detail. ３. Mounting failures, such as misdirection or miscounts, may harm the device. ４. A strong electromagnetic field may cause the IC to malfunction. ５. The GND pin should be the location within ±0.3V compared with the PGND pin. ALL Pin (except BST1, BST2, HN1, HN2,) Voltage should be under VCC voltage +0.3V ６. BD9898F, BD9898FV incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation of the thermal shutdown circuit is assumed. ７. When modifying the external circuit components, make sure to leave an adequate margin for external components actual value and tolerance as well as dispersion of the IC. ８. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching. Make sure to leave adequate margin for this IC variation. ９. Under operating CP charge (under error mode) analog dimming and burst dimming are not operate. 10. Under operating Slow Start Control (SS is less than 1.5V), It does not operate Timer Latch. 11. By STB voltage, BD9898F, BD9898FV are changed to 2 states. Therefore, do not input STB pin voltage between one state and the other state (0.8～2.0V). 12. The pin connected a connector need to connect to the resistor for electrical surge destruction. 13. This IC is a monolithic IC which (as shown is Fig-1) has P+ substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, ○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) ○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin. Transistor (NPN) Resistance (PinA) (PinB) B E C Ｃ GND P P＋ N P＋ N Ｎ N Ｎ P substrate GND Parasitic diode N P substrate GND Parasitic diode (PinB) (PinA) B CＣ Ｂ EＥ Parasitic diode GND GND Other adjacent components Parasitic diode Fig-1 Simplified structure of a Bipolar IC REV. B Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. 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