IRF IRLI530NPBF

PD - 95635
IRLI530NPbF
Logic-Level Gate Drive
l Advanced Process Technology
l Isolated Package
l High Voltage Isolation = 2.5KVRMS …
l Sink to Lead Creepage Dist. = 4.8mm
l Fully Avalanche Rated
l Lead-Free
Description
HEXFET® Power MOSFET
l
D
VDSS = 100V
RDS(on) = 0.10Ω
G
S
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use
in a wide variety of applications.
The TO-220 Fullpak eliminates the need for additional
insulating hardware in commercial-industrial
applications. The moulding compound used provides
a high isolation capability and a low thermal resistance
between the tab and external heatsink. This isolation
is equivalent to using a 100 micron mica barrier with
standard TO-220 product. The Fullpak is mounted to
a heatsink using a single clip or by a single screw
fixing.
ID = 12A
TO-220 FULLPAK
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current †
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy‚†
Avalanche Current†
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt Ġ
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
Max.
Units
12
8.6
60
41
0.27
± 16
150
9.0
4.1
5.0
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
300 (1.6mm from case )
10 lbf•in (1.1N•m)
°C
Thermal Resistance
Parameter
RθJC
RθJA
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Junction-to-Case
Junction-to-Ambient
Typ.
Max.
Units
–––
–––
3.7
65
°C/W
1
07/23/04
IRLI530NPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
∆V(BR)DSS/∆TJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
100
–––
–––
–––
–––
1.0
7.7
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
LS
Internal Source Inductance
–––
Ciss
Coss
Crss
C
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Drain to Sink Capacitance
–––
–––
–––
–––
V(BR)DSS
IGSS
Typ.
–––
0.122
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
7.2
53
30
26
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA†
0.100
VGS = 10V, ID = 9.0A „
0.120
Ω
VGS = 5.0V, I D = 9.0A „
0.150
VGS = 4.0V, I D = 8.0A „
2.0
V
VDS = VGS , ID = 250µA
–––
S
VDS = 50V, ID = 9.0A†
25
VDS = 100V, VGS = 0V
µA
250
VDS = 80V, V GS = 0V, TJ = 150°C
100
VGS = 16V
nA
-100
VGS = -16V
34
ID = 9.0A
4.8
nC VDS = 80V
20
VGS = 5.0V, See Fig. 6 and 13 „†
–––
VDD = 50V
–––
ID = 9.0A
ns
–––
RG = 6.0Ω, VGS = 5.0V
–––
RD = 5.5Ω, See Fig. 10 „†
Between lead,
4.5 –––
6mm (0.25in.)
nH
G
from package
7.5 –––
and center of die contact
800 –––
VGS = 0V
160 –––
VDS = 25V
pF
90 –––
ƒ = 1.0MHz, See Fig. 5†
12 –––
ƒ = 1.0MHz
D
S
Source-Drain Ratings and Characteristics
IS
I SM
VSD
trr
Q rr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) †
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
‚ Starting TJ = 25°C, L = 3.1mH
RG = 25Ω, IAS = 9.0A. (See Figure 12)
ƒ ISD ≤ 9.0A, di/dt ≤ 540A/µs, VDD ≤ V(BR)DSS,
T J ≤ 175°C
2
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
12
––– –––
showing the
A
G
integral reverse
––– –––
60
p-n junction diode.
S
––– ––– 1.3
V
TJ = 25°C, IS = 6.6A, V GS = 0V „
––– 140 210
ns
TJ = 25°C, IF = 9.0A
––– 740 1100 nC
di/dt = 100A/µs „†
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
… t=60s, ƒ=60Hz
† Uses IRL530N data and test conditions
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IRLI530NPbF
100
100
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
ID , Drain-to-Source Current (A)
ID , Drain-to-Source Current (A)
10
1
2.5V
20µs PULSE WIDTH
T J = 25°C
0.1
0.1
1
10
10
2.5V
1
A
100
3.0
R DS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
10
1
V DS = 50V
20µs PULSE WIDTH
4
5
6
7
8
9
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
A
100
Fig 2. Typical Output Characteristics,
100
3
1
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics,
0.1
20µs PULSE WIDTH
T J = 175°C
0.1
0.1
VDS , Drain-to-Source Voltage (V)
2
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
TOP
TOP
10
A
I D = 15A
2.5
2.0
1.5
1.0
0.5
VGS = 10V
0.0
-60 -40 -20
0
20
40
60
A
80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRLI530NPbF
1400
V GS , Gate-to-Source Voltage (V)
1200
C, Capacitance (pF)
15
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd
C oss = C ds + C gd
800
600
Coss
400
Crss
200
0
A
1
10
V DS = 80V
V DS = 50V
V DS = 20V
12
Ciss
1000
I D = 9.0A
9
6
3
FOR TEST CIRCUIT
SEE FIGURE 13
0
100
0
VDS , Drain-to-Source Voltage (V)
30
40
A
50
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
100
1000
OPERATION IN THIS AREA LIMITED
BY R DS(on)
I D , Drain Current (A)
ISD , Reverse Drain Current (A)
20
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
TJ = 175°C
10
TJ = 25°C
VGS = 0V
1
0.4
0.6
0.8
1.0
1.2
VSD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10
A
1.4
100
10µs
10
100µs
1ms
TC = 25°C
TJ = 175°C
Single Pulse
1
1
10ms
10
100
A
1000
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRLI530NPbF
12
RD
V DS
VGS
ID , Drain Current (A)
9
D.U.T.
RG
+
-VDD
5.0V
6
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
3
VDS
90%
0
25
50
75
100
125
150
175
TC , Case Temperature ( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
D = 0.50
1
0.20
0.10
0.05
0.1
0.02
0.01
PDM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
15V
L
VDS
D.U.T
RG
IAS
10V
tp
DRIVER
+
V
- DD
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
EAS , Single Pulse Avalanche Energy (mJ)
IRLI530NPbF
350
TOP
300
BOTTOM
250
200
150
100
50
0
VDD = 25V
25
50
A
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
V(BR)DSS
tp
ID
3.7A
6.4A
9.0A
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
Current Regulator
Same Type as D.U.T.
Fig 12b. Unclamped Inductive Waveforms
50KΩ
12V
.2µF
QG
.3µF
5.0 V
QGS
D.U.T.
QGD
+
V
- DS
VGS
VG
3mA
IG
Charge
Fig 13a. Basic Gate Charge Waveform
6
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRLI530NPbF
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
ƒ
+
‚
-
-
„
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
Period
P.W.
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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7
IRLI530NPbF
TO-220 Full-Pak Package Outline
Dimensions are shown in millimeters (inches)
TO-220 Full-Pak Part Marking Information
E XAMP L E :
T H IS IS AN IR F I840G
WIT H AS S E MB L Y
L OT CODE 3432
AS S E MB L E D ON WW 24 1999
IN T H E AS S E MB L Y L IN E "K "
P AR T N U MB E R
IN T E R N AT IONAL
R E CT IF IE R
L OGO
IR F I840G
924K
34
Note: "P" in assembly line
position indicates "Lead-Free"
AS S E MB L Y
L OT CODE
32
D AT E COD E
YE AR 9 = 1999
WE E K 24
L IN E K
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/04
8
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