CYPRESS CY62138FV30

CY62138FV30 MoBL®
2-Mbit (256K x 8) Static RAM
Features
Functional Description
The CY62138FV30[1] is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Place the device into standby mode reducing
power consumption when deselected (CE1 HIGH or CE2 LOW).
■
Very High-speed: 45 ns
■
Temperature ranges
❐ Industrial: –40 °C to 85 °C
❐ Automotive-A: –40 °C to 85 °C
■
Wide voltage range: 2.20 V to 3.60 V
■
Pin compatible with CY62138CV25/30/33
■
Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 5 A
■
Ultra low active power
❐ Typical active current: 1.6 mA at f = 1 MHz
■
Easy memory expansion with CE1, CE2, and OE Features
■
Automatic power down when deselected
■
complementary metal oxide semiconductor (CMOS) for
Optimum speed and power
■
Offered in Pb-free 36-Ball VFBGA, 32-Pin TSOP II, 32-Pin
SOIC, 32-Pin TSOP I and 32-Pin STSOP Packages
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A17).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW and CE2 HIGH and WE
LOW).
Logic Block Diagram
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-08029 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 4, 2010
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CY62138FV30 MoBL®
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Electrical Characteristics ................................................ 4
Capacitance ...................................................................... 4
Thermal Resistance.......................................................... 5
Data Retention Characteristics ....................................... 5
Switching Characteristics ................................................ 6
Switching Waveforms ...................................................... 7
Truth Table ........................................................................ 8
Ordering Information........................................................ 9
Document #: 001-08029 Rev. *I
Ordering Code Definition............................................. 9
Package Diagrams .......................................................... 10
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
Page 2 of 16
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CY62138FV30 MoBL®
Pin Configuration
36-Ball VFBGA (Top View) [2]
32-Pin SOIC/TSOP II (Top View)
3
4
5
6
A6
A8
A
A7
I/O0
B
I/O1
C
VSS
VCC
D
VCC
VSS
E
I/O2
F
1
2
A0
A1
CE2
A3
I/O4
A2
WE
A4
NC
A5
I/O5
I/O6
NC
A17
I/O7
OE
CE1
A16
A15
I/O3
G
A9
A10
A11
A12
A13
A14
H
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
32-Pin TSOP I (Top View)
A11
A9
A8
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP I
Top View
(not to scale)
1
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
32
31
2
3
4
30
29
5
6
28
27
26
25
7
8
9
10
24
23
22
11
12
13
14
15
16
21
20
19
18
17
32-Pin STSOP (Top View)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
25
26
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
STSOP
Top View
(not to scale)
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Product Portfolio
Product
CY62138FV30LL
Range
Ind’l/Auto-A
Speed
(ns)
VCC Range (V)
Min
Typ[3]
Max
2.2
3.0
3.6
45
Power Dissipation
Operating ICC (mA)
f = 1 MHz
f = fmax
Standby ISB2 (A)
Typ[3]
Max
Typ[3]
Max
Typ[3]
Max
1.6
2.5
13
18
1
5
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C.
Document #: 001-08029 Rev. *I
Page 3 of 16
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CY62138FV30 MoBL®
DC input voltage [4, 5] ......................................–0.3 V to 3.9 V
Maximum Ratings
Output current into outputs (LOW) .............................. 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage......................................... > 2001 V
(MIL-STD-883, Method 3015)
Storage temperature................................. –65 °C to +150 °C
Latch-up current ..................................................... > 200 mA
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Product
Supply voltage to ground
potential ..........................................................–0.3 V to 3.9 V
Ambient
Temperature
Range
VCC [6]
CY62138FV30LL Ind’l/Auto-A –40 °C to +85 °C 2.2 V to 3.6 V
DC voltage applied to outputs
in High-Z State [4, 5] ........................................–0.3 V to 3.9 V
Electrical Characteristics (Over the Operating Range)
Parameter
Description
Output HIGH voltage
VOH
Test Conditions
45 ns (Ind’l/Auto-A)
Unit
Min
Typ [7]
Max
IOH = –0.1 mA
2.0
–
–
V
IOH = –1.0 mA, VCC > 2.70 V
2.4
–
–
V
–
–
0.4
V
VOL
Output LOW voltage
IOL = 0.1 mA
–
0.4
V
VIH
Input HIGH voltage
VCC = 2.2 V to 2.7 V
1.8
–
VCC + 0.3V
V
VCC= 2.7 V to 3.6 V
2.2
–
VCC + 0.3V
V
VCC = 2.2 V to 2.7 V For BGA package
–0.3
–
0.6
V
VCC= 2.7 V to 3.6 V
–0.3
–
0.8
V
VCC = 2.2 V to 3.6 V For other packages
–0.3
–
0.6
V
IOL = 2.1 mA, VCC > 2.70 V
Input LOW voltage
VIL
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VO < VCC,
output disabled
–1
–
+1
A
ICC
VCC Operating supply current
f = fmax = 1/tRC
VCC = VCCmax
IOUT = 0 mA
CMOS levels
–
13
18
mA
–
1.6
2.5
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
–
1
5
A
–
1
5
A
f = 1 MHz
ISB1[8]
Automatic CE Power-down
Current CMOS inputs
VIN > VCC – 0.2 V, VIN < 0.2 V),
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = 3.60 V
ISB2
[8]
Automatic CE Power-down
Current CMOS inputs
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
Capacitance
Parameter[9]
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ.)
Max
Unit
10
pF
10
pF
Notes
4. VIL(min) = –2.0V for pulse durations less than 20 ns.
5. VIH(max) = VCC+0.75V for pulse durations less than 20 ns.
6. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C
8. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-08029 Rev. *I
Page 4 of 16
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CY62138FV30 MoBL®
Thermal Resistance
Parameter[10]
Description
JA
Thermal resistance
(Junction to Ambient)
JC
Thermal resistance
(Junction to Case)
Test Conditions
SOIC
VFBGA
TSOP II
STSOP
TSOP I
Unit
Still air, soldered on a 3 x
4.5 inch, two layer
printed circuit board
44.53
38.49
44.16
59.72
50.19
C/W
24.05
17.66
11.97
15.38
14.59
C/W
Figure 1. AC Test Loads and Waveforms
R1
VCC
OUTPUT
ALL INPUT PULSES
VCC
R2
30 pF
INCLUDING
JIG AND
SCOPE
90%
10%
GND
Rise Time = 1 V/ns
Equivalent to:
90%
10%
Fall Time = 1 V/ns
THEVENIN EQUIVALENT
OUTPUT
RTH
V
Parameter
2.5 V (2.2 V to 2.7 V)
3.0 V (2.7 V to 3.6 V)
Unit
R1
16667
1103

R2
15385
1554

RTH
8000
645

VTH
1.20
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Typ[11]
Max
Unit
1.5
–
–
V
–
1
4
A
Chip deselect to data retention time
0
–
–
ns
Operation recovery time
45
–
–
ns
Conditions
VCC for data retention
[12]
Data retention current
tCDR [10]
tR
Min
Description
[13]
VCC = 1.5 V,
CE1 > VCC 0.2 V or CE2 < 0.2
V, VIN > VCC 0.2 V or VIN < 0.2 V
Ind’l/Auto-A
Figure 2. Data Retention Waveform [14]
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 1.5V
VCC(min)
tR
CE
Notes
10. Tested initially and after any design or process changes that may affect these parameters.
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 2 5°C
12. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating
13. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
14. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
Document #: 001-08029 Rev. *I
Page 5 of 16
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CY62138FV30 MoBL®
Switching Characteristics (Over the Operating Range)
Parameter[15]
45 ns (Ind’l/Auto-A)
Description
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
tLZOE
OE LOW to Low-Z [16]
5
–
ns
OE HIGH to High-Z
tHZOE
tLZCE
[16,17]
–
18
ns
[16]
10
–
ns
[16,17]
–
18
ns
CE1 LOW and CE2 HIGH to Low Z
tHZCE
CE1 HIGH or CE2 LOW to High-Z
tPU
CE1 LOW and CE2 HIGH to Power-up
0
–
ns
CE1 HIGH or CE2 LOW to Power-down
–
45
ns
tWC
Write cycle time
45
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
35
–
ns
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to Write Start
0
–
ns
tPWE
WE pulse Width
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
–
18
ns
10
–
ns
tPD
Write Cycle
[18]
[16,17]
tHZWE
WE LOW to High-Z
tLZWE
WE HIGH to Low-Z [16]
Notes
15. Test conditions for all parameters other than tristate parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 5.
16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
17. tHZOE, tHZCE, and tHZWE transitions are measured when the output enters a high impedance state.
18. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write.
Document #: 001-08029 Rev. *I
Page 6 of 16
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CY62138FV30 MoBL®
Switching Waveforms
Figure 3. Read Cycle 1 (Address transition controlled) [20, 21]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 4. Read Cycle No. 2 (OE controlled) [21, 22, 25]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tHZCE
tLZOE
HIGH IMPEDANCE
DATA OUT
DATA VALID
tLZCE
tPD
tPU
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
50%
50%
ICC
ISB
Figure 5. Write Cycle No. 1 (WE controlled)
[19, 23, 24, 25]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
OE
tSD
DATA I/O
NOTE 26
tHD
DATA VALID
tHZOE
Notes
19. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write
20. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
21. WE is HIGH for read cycle.
22. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.
23. Data I/O is high impedance if OE = VIH.
24. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
25. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
26. During this period, the I/Os are in output state. Do not apply input signals
Document #: 001-08029 Rev. *I
Page 7 of 16
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CY62138FV30 MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle No. 2 (CE1 or CE2 controlled) [27, 28, 29, 30]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
Figure 7. Write Cycle No. 3 (WE controlled, OE LOW) [27, 30]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tHD
tSD
NOTE 31
DATA I/O
DATA VALID
tLZWE
tHZWE
Truth Table
CE1
CE2
WE
OE
H
X[32]
Inputs/Outputs
Mode
Power
X
X
High-Z
Deselect / Power-down
Standby (ISB)
X[32]
L
X
X
High-Z
Deselect/Power-down
Standby (ISB)
L
H
H
L
Data out
Read
Active (ICC)
L
H
H
H
High-Z
Output disabled
Active (ICC)
L
H
L
X
Data in
Write
Active (ICC)
Notes
27. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
28. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write
29. Data I/O is high impedance if OE = VIH.
30. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains iin high impedance state.
31. During this period, the I/Os are in output state. Do not apply input signals.
32. The ‘X’ (Don’t care) state for the Chip enables (CE1 and CE2) in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
pins is not permitted.
Document #: 001-08029 Rev. *I
Page 8 of 16
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CY62138FV30 MoBL®
Ordering Information
Speed
(ns)
45
Package
Diagram
Ordering Code
Package Type
CY62138FV30LL-45BVXI
51-85149
36-ball VFBGA (Pb-free)
CY62138FV30LL-45ZSXI
51-85095
32-pin TSOP II (Pb-free)
CY62138FV30LL-45ZAXI
51-85094
32-pin STSOP (Pb-free)
CY62138FV30LL-45ZXI
51-85056
32-pin TSOP I (Pb-free)
CY62138FV30LL-45SXI
51-85081
32-pin SOIC (Pb-free)
CY62138FV30LL-45ZAXA
51-85094
32-pin STSOP (Pb-free)
Operating
Range
Industrial
Automotive-A
Ordering Code Definition
CY
621
3
8F
V30
LL
45
XXX
X
Temperature Grades
I = Industrial, A = Auto A
Package Type BVX: VFBGA (Pb-free)
ZSX: TSOP II (Pb-free)
ZAX: STSOP (Pb-free)
ZX : TSOP I (Pb-free)
SX : SOIC (Pb-free)
Speed Grade
Low Power
Voltage Range = 3 V typical
Bus Width = x8
F = 90nm Technology
Density = 2 Mbit
MoBL SRAM Family
Coimpany ID: CY = Cypress
Document #: 001-08029 Rev. *I
Page 9 of 16
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CY62138FV30 MoBL®
Package Diagrams
Figure 8. 36-Ball VFBGA (6 x 8 x 1 mm), 51-85149
51-85149 *D
Document #: 001-08029 Rev. *I
Page 10 of 16
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CY62138FV30 MoBL®
Figure 9. 32-Pin TSOP II, 51-85095
51-85095 *A
Document #: 001-08029 Rev. *I
Page 11 of 16
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CY62138FV30 MoBL®
Figure 10. 32-Pin (450 Mil) Molded SOIC, 51-85081
51-85081 *C
Document #: 001-08029 Rev. *I
Page 12 of 16
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CY62138FV30 MoBL®
Figure 11. 32-Pin TSOP I (8 x 20 mm), 51-85056
51-85056 * E
Document #: 001-08029 Rev. *I
Page 13 of 16
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CY62138FV30 MoBL®
Figure 12. 32-Pin STSOP (8 x 13.4 mm), 51-85094
51-85094 * E
Acronyms
Document Conventions
Acronym
Description
CMOS
complementary metal oxide semiconductor
I/O
input/output
SRAM
static random access memory
VFBGA
TSOP
Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
very fine ball grid array
A
microamperes
thin small outline package
mA
milliampere
MHz
megahertz
Document #: 001-08029 Rev. *I
ns
nanoseconds
pF
picofarads
V
volts

ohms
W
watts
Page 14 of 16
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CY62138FV30 MoBL®
Document History Page
Document Title: CY62138FV30 MoBL®, 2-Mbit (256K x 8) Static RAM
Document Number: 001-08029
Rev.
ECN No.
Submission
Date
Orig. of
Change
Description of Change
**
463660
See ECN
NXR
New data sheet
*A
467351
See ECN
NXR
Added 32-pin TSOP II package, 32 pin TSOP I and 32 pin STSOP packages
Changed ball A3 from NC to CE2 in 36-ball FBGA pin out
*B
566724
See ECN
NXR
Converted from Preliminary to Final
Corrected typo in 32 pin TSOP II pin configuration diagram on page #2 (changed
pin 24 from CE1to OE and pin 22 from CE to CE1)
Changed the ICC(max) value from 2.25 mA to 2.5 mA for test condition f=1 MHz
Changed the ISB2(typ) value from 0.5 A to 1 A
Changed the ISB2(max) value from 2.5 A to 5 A
Changed the ICCDR(typ) value from 0.5 A to 1 A and ICCDR(max) value from 2.5
A to 4 A
*C
797956
See ECN
VKN
Added 32-pin SOIC package
Updated VIL spec for SOIC, TSOP-II, TSOP-I, and STSOP packages on
Electrical characteristics table
*D
809101
See ECN
VKN
Corrected typo in the Ordering Information table
*E
940341
See ECN
VKN
Added footnote #7 related to ISB2 and ICCDR
*F
2769239
09/25/09
*G
3055119
10/12/2010
RAME
Updated and converted all tablenotes into Footnote
Added Acronyms and Units of Measure table
Added Ordering Code Definition
Updated All Package Diagrams.
Updated datasheet as per new template.
*H
3061313
10/15/2010
RAME
Minor changes: Corrected “IO” to “I/O”
*I
3078557
11/04/2010
RAME
Corrected 55 C to -55C in Ambient Temperature with Power applied in Maximum
Ratings Section
Document #: 001-08029 Rev. *I
VKN/AESA Included Automotive-A information
Page 15 of 16
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CY62138FV30 MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
psoc.cypress.com/solutions
cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-08029 Rev. *I
Revised November 4, 2010
Page 16 of 16
All products and company names mentioned in this document may be the trademarks of their respective holders.
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