データシート

ASAHI KASEI
[AK4370]
AK4370
Output Mixer & HP-AMP
AK4370
24bit D/A
I/F
DAC
16
40mW
ON/OFF
24pin QFN (4mm
†
†
†8
†
†
†
†
†
†
†
†
4mm)
ΔΣ
DAC
- 8kHz ∼ 48kHz
FIR
: 20kHz
: ±0.02dB
: 54dB
: 32kHz, 44.1kHz, 48kHz
:
- 256fs/384fs/512fs/768fs/1024fs
AC
I/F
: MSB First, 2’s Complement
, 24bit/20bit/16bit
- I2S, 24bit
: LR, LL, RR, (L+R)/2
:4
or
- S/N: [email protected]
: +6 to –24dB (or 0 to –30dB), 2dB step
†
: 40mW x 2ch @16Ω, 3.3V
- S/N: [email protected]
ON/OFF
: +0 ∼ –63dB & +12/+6/0dB Gain
1.5dB step (0 ∼ –30dB), 3dB step (–30 ∼ –63dB)
†
:3
/I2C
†
: 1.6V ∼ 3.6V
†
: 3.8mA @1.8V (6.8mW, DAC+HP,
)
† Ta: −30 ∼ 85°C
†
: 24pin QFN (4mm x 4mm, 0.5mm pitch)
† AK4368
MS0595-J-00
2007/03
-1-
ASAHI KASEI
[AK4370]
■
LIN1/IN− LIN2
MCKI
BICK
LRCK
SDATA
Audio
Interface
VSS1
Clock
Divider
VCOM
VCOM
DVDD
VSS2
AVDD
DAC
Digital
Volume
Deemphasis
Bass
Boost
Digital
Filter
LOUT
(Lch)
ROUT
DAC
(Rch)
PDN
I2C
HDP
Amp
MUTE
HPL
HDP
Amp
MUTE
HPR
CAD0/CSN
SCL/CCLK
Serial I/F
SDA/CDTI
RIN1/IN+ RIN2
HVDD
MUTET
Figure 1.
MS0595-J-00
2007/03
-2-
ASAHI KASEI
[AK4370]
■
AK4370VN
AKD4370
−30 ∼ +85°C
AK4370
24pin QFN (0.5mm pitch)
VSS1
HVDD
AVDD
VCOM
ROUT
LOUT
18
17
16
15
14
13
■
PDN
LIN2
22
Top View
9
CSN/CAD0
RIN1/IN+
23
8
CCLK/SCL
LIN1/IN−
24
7
CDTI/SDA
6
10
VSS2
AK4370VN
5
21
DVDD
RIN2
4
I2C
MCKI
11
3
20
LRCK
HPL
2
MUTET
BICK
12
1
19
SDATA
HPR
MS0595-J-00
2007/03
-3-
ASAHI KASEI
[AK4370]
■ AK4368
1. Function
Function
AK4368
Analog Mixing
1-Stereo + 1-Mono
Single-ended Input
MCKI at EXT Mode
256fs/512fs/1024fs,
12.288MHz(max)
HP-Amp Output Volume
No
HP-Amp Hi-Z Setting
PLL
3D Enhancement
ALC
Package
No
Yes
Yes
Yes
41BGA (4mm x 4mm)
2.
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
(AK4368
Register Name
Power Management
Clock Control 0
Clock Control 1
Mode Control 0
Mode Control 1
DAC Lch ATT
DAC Rch ATT
Headphone Out Select 0
Lineout Select 0
Lineout ATT
Reserved
Reserved
Reserved
Headphone Out Select 1
Headphone ATT
Lineout Select 1
Mono Mixing
Differential Select
Reserved
Reserved
AK4370
2-Stereo
Single-ended Input
or Full-differential Input
256fs/384fs/512fs/768fs/1024fs,
24.576MHz(max)
0 to –63dB & +12/+6/0dB
1.5dB step (0 to –30dB)
3dB step (–30 to –63dB)
Yes
No
No
No
24QFN (4mm x 4mm)
)
D7
0
FS3
0
0
ATS
ATTL7
ATTR7
HPG1
0
0
REF7
0
0
0
0
0
0
0
0
0
D6
PMPLL
FS2
0
MONO1
DATTC
ATTL6
ATTR6
HPG0
LOG
0
REF6
0
0
0
HPZ
0
0
0
0
0
AK4370
AK4370
D5
PMLO
FS1
M/S
MONO0
LMUTE
ATTL5
ATTR5
LIN2HR
LIN2R
0
REF5
ALC
0
0
HMUTE
0
0
0
0
0
MS0595-J-00
D4
MUTEN
FS0
MCKAC
BCKP
SMUTE
ATTL4
ATTR4
LIN2HL
LIN2L
0
REF4
ROTM1
0
0
ATTH4
0
0
0
0
1
D3
PMHPR
PLL3
BF
LRP
BST1
ATTL3
ATTR3
RIN1HR
RIN1R
ATTS3
REF3
ROTM0
DP1
RIN2HR
ATTH3
RIN2R
L2M
0
0
0
D2
PMHPL
PLL2
PS0
DIF2
BST0
ATTL2
ATTR2
LIN1HL
LIN1L
ATTS2
REF2
LMAT1
DP0
RIN2HL
ATTH2
RIN2L
L2HM
0
0
0
D1
PMDAC
PLL1
PS1
DIF1
DEM1
ATTL1
ATTR1
DARHR
DARR
ATTS1
REF1
LMAT0
3D1
LIN1HR
ATTH1
LIN1R
L1M
LDIFH
0
0
D0
PMVCM
PLL0
MCKO
DIF0
DEM0
ATTL0
ATTR0
DALHL
DALL
ATTS0
REF0
RATT
3D0
RIN1HL
ATTH0
RIN1L
L1HM
LDIF
0
0
2007/03
-4-
ASAHI KASEI
No.
[AK4370]
I/O
1
SDATA
2
BICK
I/O
3
LRCK
I/O
4
5
6
MCKI
DVDD
VSS2
SDA
CDTI
SCL
CCLK
CAD0
CSN
I
I/O
I
I
I
I
I
7
8
9
10
PDN
I
L/R
, 1.6 ∼ 3.6V
VSS1
2
(I2C
0
: I2C pin = “H”)
(3
: I2C pin = “L”)
(I2C
: I2C pin = “H”)
(3
: I2C pin = “L”)
: I2C pin = “H”)
(3
: I2C pin = “L”)
(I2C
&
“L”
I
“L”
11
I2C
I
12
MUTET
O
13
14
LOUT
ROUT
O
O
15
VCOM
O
16
17
18
19
20
21
22
AVDD
HVDD
VSS1
HPR
HPL
RIN2
LIN2
RIN1
IN+
LIN1
IN−
O
O
I
I
I
I
I
I
23
24
Note 1.
“H”: I2C
, “L”: 3
VSS1 pin
Lch
Rch
VSS1 pin
2.2μF
, 1.6 ∼ 3.6V
, 1.6 ∼ 3.6V
1
Rch HP-Amp
Lch HP-Amp
Rch
Lch
Rch
Lch
2
2
1
(LDIF bit = “0” :
(LDIF bit = “1” :
)
1
(LDIF bit = “0” :
(LDIF bit = “1” :
)
)
)
(I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN)
MCKI pin
PDN pin = “L”
MS0595-J-00
2007/03
-5-
ASAHI KASEI
[AK4370]
■
Analog
Digital
LOUT, ROUT, MUTET, HPL, HPR, LIN2, RIN2
RIN1/IN+, LIN1/IN−
MCKI
VSS2
(VSS1, VSS2 = 0V; Note 2, Note 3)
Parameter
Symbol
min
max
Units
Power Supplies Analog
AVDD
4.6
V
−0.3
Digital
DVDD
4.6
V
−0.3
HP-Amp
HVDD
4.6
V
−0.3
Input Current (any pins except for supplies)
IIN
mA
±10
Analog Input Voltage (Note 4)
VINA
(AVDD+0.3) or 4.6
V
−0.3
Digital Input Voltage (Note 5)
VIND
(DVDD+0.3)
or
4.6
V
−0.3
Ambient Temperature
Ta
85
−30
°C
Storage Temperature
Tstg
150
−65
°C
Note 2.
Note 3. VSS1, VSS2
Note 4. LIN1/IN−, RIN1/IN+, LIN2 and RIN2 pins. Max (AVDD+0.3V)
4.6V
Note 5. SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN and I2C pins. Max (DVDD+0.3V)
4.6V
:
(VSS1, VSS2 = 0V; Note 2)
Parameter
Power Supplies Analog
(Note 6)
Digital (Note 7)
HP-Amp
Difference
Note 2.
Note 6. AVDD DVDD
OFF
HVDD
Note 7. Max (AVDD+0.2V)
Symbol
AVDD
DVDD
HVDD
AVDD−HVDD
min
1.6
1.6
1.6
−0.3
DVDD
AVDD
AVDD HVDD
1.6V
DVDD
typ
2.4
2.4
2.4
0
max
3.6
(AVDD+0.2) or 3.6
3.6
+0.3
Units
V
V
V
V
AVDD
AVDD HVDD
OFF
3.6V
:
MS0595-J-00
2007/03
-6-
ASAHI KASEI
[AK4370]
(
Ta=25°C; AVDD=DVDD=HVDD=2.4V, VSS1=VSS2= 0V; fs=44.1kHz; BOOST OFF; Slave
Mode; Signal Frequency =1kHz; Measurement band width=20Hz ∼ 20kHz; Headphone-Amp: RL =16Ω, CL=220μF
(Figure 38
))
Parameter
min
typ
max
Units
24
bit
DAC Resolution
Headphone-Amp: (HPL/HPR pins) (Note 8)
Analog Output Characteristics
THD+N
dB
−3dBFS Output, 2.4V, Po=10mW@16Ω
−50
−40
dB
0dBFS Output, 3.3V, Po=40mW@16Ω
−20
82
90
dB
D-Range
−60dBFS Output, A-weighted, 2.4V
92
dB
−60dBFS Output, A-weighted, 3.3V
S/N
A-weighted, 2.4V
82
90
dB
A-weighted, 3.3V
92
dB
Interchannel Isolation
60
80
dB
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
Load Resistance (Note 9)
Load Capacitance
Output Voltage −3dBFS Output (Note 10)
0dBFS Output, 3.3V,
Po=40mW@16Ω
Output Volume: (HPL/HPR pins)
Step Size
0 ∼ –30dB
(HPG1-0 bits = “00”)
–30 ∼ –63dB
Gain Control Range
Max (ATT4-0 bits = “00H”)
(HPG1-0 bits = “00”)
Min (ATT4-0 bits = “1FH”)
Stereo Line Output: (LOUT/ROUT pins, RL=10kΩ) (Note 11)
Analog Output Characteristics:
THD+N (0dBFS Output)
S/N
A-weighted, 2.4V
A-weighted, 3.3V
DC Accuracy
Gain Drift
Load Resistance (Note 9)
Load Capacitance
Output Voltage (0dBFS Output) (Note 12)
Output Volume: (LOUT/ROUT pins)
Step Size
Gain Control Range
Max (ATTS3-0 bits = “FH”)
(LOG1-0 bit = “0”)
Min (ATTS3-0 bits = “0H”)
16
1.04
0.3
200
1.16
0.8
300
1.28
dB
ppm/°C
Ω
pF
Vpp
-
0.8
-
Vrms
0.1
0.1
-
1.5
3
0
−63
2.9
5.9
-
dB
dB
dB
dB
80
-
−60
87
90
−50
-
dB
dB
dB
10
1.32
200
1.47
25
1.61
ppm/°C
kΩ
pF
Vpp
1
-
2
0
−30
3
-
dB
dB
dB
Note 8. DALHL=DARHR bits = “1”, LIN1HL=RIN1HL=LIN2HL=RIN2HL=IN1HR=RIN1HR=LIN2HR=RIN2HR
bits = “0”
Note 9. AC
Note 10.
AVDD
Vout = 0.48 x AVDD(typ)@−3dBFS.
Note 11.DALL = DARR bits = “1”, LIN1L= RIN1L=LIN2L=RIN2L=LIN1R=RIN1R=LIN2R=RIN2R bits = “0”
Note 12.
AVDD
Vout = 0.61 x AVDD(typ)@0dBFS.
MS0595-J-00
2007/03
-7-
ASAHI KASEI
[AK4370]
Parameter
LINEIN: (LIN1/RIN1/LIN2/RIN2 pins)
Analog Input Characteristics
)
Input Resistance (Figure 21, Figure 22
LIN1 pin
LIN1HL=LIN1HR=LIN1L=LIN1R bits = “1”
LIN1HL bit = “1”, LIN1HR=LIN1L=LIN1R bits = “0”
LIN1HR bit = “1”, LIN1HL=LIN1L=LIN1R bits = “0”
LIN1L bit = “1”, LIN1HL=LIN1HR=LIN1R bits = “0”
LIN1R bit = “1”, LIN1HL=LIN1HR=LIN1L bits = “0”
RIN1 pin
RIN1HL=RIN1HR=RIN1L=RIN1R bits = “1”
RIN1HL bit = “1”, RIN1HR=RIN1L=RIN1R bits = “0”
RIN1HR bit = “1”, RIN1HL=RIN1L=RIN1R bits = “0”
RIN1L bit = “1”, RIN1HL=RIN1HR=RIN1R bits = “0”
RIN1R bit = “1”, RIN1HL=RIN1HR=RIN1L bits = “0”
LIN2 pin
LIN2HL=LIN2HR=LIN2L=LIN2R= bits = “1”
LIN2HL bit = “1”, LIN2HR=LIN2L=LIN2R bits = “0”
LIN2HR bit = “1”, LIN2HL=LIN2L=LIN2R bits = “0”
LIN2L bit = “1”, LIN2HL=LIN2HR=LIN2R bits = “0”
LIN2R bit = “1”, LIN2HL=LIN2HR=LIN2L bits = “0”
RIN2 pin
RIN2HL=RIN2HR=RIN2L=RIN2R bits = “1”
RIN2HL bit = “1”, RIN2HR=RIN2L=RIN2R bits = “0”
RIN2HR bit = “1”, RIN2HL=RIN2L=RIN2R bits = “0”
RIN2L bit = “1”, RIN2HL=RIN2HR=RIN2R bits = “0”
RIN2R bit = “1”, RIN2HL=RIN2HR=RIN2L bits = “0”
Gain
LIN1/LIN2/RIN1/RIN2 Æ LOUT/ROUT
LIN1/LIN2/RIN1/RIN2 Æ HPL/HPR
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”) (Note 13)
AVDD+DVDD
HVDD
Power-Down Mode (PDN pin = “L”) (Note 14)
min
typ
max
Units
14
-
25
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
14
-
25
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
14
-
25
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
14
-
25
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
−1
−0.05
0
+0.95
+1
+1.95
dB
dB
-
3.8
1.2
1
5.5
2.5
100
mA
mA
μA
Note 13. PMDAC=PMHPL=PMHPR=PMLO bits = “1”, MUTEN bit = “1”, HP-Amp
PMDAC=PMHPL=PMHPR= “1”, PMLO bit= “0” , AVDD+DVDD+HVDD=4.0mA (typ) @2.4V, 3.8mA
(typ) @1.8V.
Note 14.
(MCKI, BICK, LRCK)
VSS2
MS0595-J-00
2007/03
-8-
ASAHI KASEI
[AK4370]
(Ta=25°C; AVDD, DVDD, HVDD=1.6 ∼ 3.6V; fs=44.1kHz; De-emphasis = “OFF”)
Parameter
Symbol
min
typ
DAC Digital Filter: (Note 15)
Passband (Note 16)
PB
0
−0.05dB
22.05
−6.0dB
Stopband (Note 16)
SB
24.1
Passband Ripple
PR
Stopband Attenuation
SA
54
Group Delay (Note 17)
GD
22
Group Delay Distortion
0
ΔGD
DAC Digital Filter + Analog Filter: (Note 15) (Note 18)
Frequency Response
FR
0 ∼ 20.0kHz
±0.5
Analog Filter: (Note 19)
Frequency Response
FR
0 ∼ 20.0kHz
±1.0
BOOST Filter: (Note 18) (Note 20)
Frequency Response
20Hz
FR
5.76
MIN
100Hz
2.92
1kHz
0.02
20Hz
FR
10.80
MID
100Hz
6.84
1kHz
0.13
20Hz
FR
16.06
MAX 100Hz
10.54
1kHz
0.37
Note 15. BOOST OFF (BST1-0 bit = “00”)
Note 16.
fs (
)
PB=0.4535fs(@−0.05dB) SB=0.546fs(@−54dB)
Note 17.
max
Units
20.0
±0.02
-
kHz
kHz
kHz
dB
dB
1/fs
µs
-
dB
-
dB
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
Note 18. DAC Æ HPL, HPR, LOUT, ROUT
Note 19. LIN1/LIN2/RIN1/RIN2 Æ HPL/HPR/LOUT/ROUT
Note 20.
fs
Boost Filter (fs=44.1kHz)
20
MAX
15
Gain [dB]
MID
10
MIN
5
0
-5
10
100
1000
10000
Frequency [Hz]
Figure 2. Boost Frequency (fs=44.1kHz)
MS0595-J-00
2007/03
-9-
ASAHI KASEI
[AK4370]
DC
(Ta=25°C; AVDD, DVDD, HVDD=1.6 ∼ 3.6V)
Parameter
High-Level Input Voltage
2.2V≤DVDD≤3.6V
1.6V≤DVDD<2.2V
Low-Level Input Voltage
2.2V≤DVDD≤3.6V
1.6V≤DVDD<2.2V
Input Voltage at AC Coupling (Note 21)
High-Level Output Voltage
(Iout=−200μA)
Low-Level Output Voltage
(Except SDA pin: Iout=200μA)
(SDA pin, 2.0V≤DVDD≤3.6V: Iout=3mA)
(SDA pin, 1.6V≤DVDD<2.0V: Iout=3mA)
Input Leakage Current
Note 21. MCKI pin
Symbol
VIH
VIH
VIL
VIL
VAC
VOH
min
70%DVDD
80%DVDD
0.4
DVDD−0.2
typ
-
max
30%DVDD
20%DVDD
-
Units
V
V
V
V
Vpp
V
VOL
VOL
VOL
Iin
-
-
0.2
0.4
20%DVDD
±10
V
V
V
μA
(Figure 38
MS0595-J-00
)
2007/03
- 10 -
ASAHI KASEI
[AK4370]
(Ta=25°C; AVDD, DVDD, HVDD=1.6 ∼ 3.6V; CL = 20pF; unless otherwise specified)
Parameter
Symbol
min
Master Clock Input Timing
Frequency
fCLK
2.048
Pulse Width Low (Note 22)
tCLKL
0.4/fCLK
Pulse Width High (Note 22)
tCLKH
0.4/fCLK
AC Pulse Width (Note 23)
tACW
20.3
LRCK Timing
Frequency
fs
8
Duty Cycle: Slave Mode
Duty
45
Master Mode
Duty
Serial Interface Timing (Note 24)
Slave Mode (M/S bit = “0”):
BICK Period (Note 25)
tBCK
312.5 or 1/(64fs)
BICK Pulse Width Low
tBCKL
100
Pulse Width High
tBCKH
100
tLRB
50
LRCK Edge to BICK “↑” (Note 26)
tBLR
50
BICK “↑” to LRCK Edge (Note 26)
SDATA Hold Time
tSDH
50
SDATA Setup Time
tSDS
50
Master Mode (M/S bit = “1”):
BICK Frequency (BF bit = “1”)
fBCK
(BF bit = “0”)
fBCK
BICK Duty
dBCK
tMBLR
BICK “↓” to LRCK
−50
SDATA Hold Time
tSDH
50
SDATA Setup Time
tSDS
50
Control Interface Timing (3-wire Serial mode)
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
tCSW
150
tCSS
50
CSN “↑” to CCLK “↑”
tCSH
50
CCLK “↑” to CSN “↑”
typ
max
Units
-
24.576
-
MHz
ns
ns
ns
44.1
50
48
55
-
kHz
%
%
-
1/(32fs)
-
ns
ns
ns
ns
ns
ns
ns
64fs
32fs
50
-
50
-
Hz
Hz
%
ns
ns
ns
-
-
ns
ns
ns
ns
ns
ns
ns
ns
Note 22. AC
Note 23. MCKI
(Figure 3
Note 24.
Note 25. 312.5
Note 26.
1/(64fs)
LRCK
)
BICK
“↑”
MS0595-J-00
2007/03
- 11 -
ASAHI KASEI
[AK4370]
Parameter
Control Interface Timing (I2C Bus mode): (Note 27)
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 28)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Capacitive Load on Bus
Pulse Width of Spike Noise Suppressed by Input Filter
Power-down & Reset Timing
PDN Pulse Width (Note 29)
Note 27. I2C Philips Semiconductors
Note 28.
300ns (SCL
Note 29.
PDN pin “L”
Symbol
min
typ
max
Units
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
tSP
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
400
0.3
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
tPD
150
-
-
ns
)
“H”
MS0595-J-00
2007/03
- 12 -
ASAHI KASEI
[AK4370]
■
1/fCLK
tACW
1000pF
tACW
Measurement
Point
MCKI Input
VAC
100kΩ
VSS2
VSS2
Figure 3. MCKI AC Coupling Timing
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 4. Clock Timing
MS0595-J-00
2007/03
- 13 -
ASAHI KASEI
[AK4370]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDATA
VIL
Figure 5. Serial Interface Timing (Slave Mode)
50%DVDD
LRCK
tMBLR
BICK
50%DVDD
tSDH
tSDS
VIH
SDATA
VIL
Figure 6. Serial Interface Timing (Master mode)
MS0595-J-00
2007/03
- 14 -
ASAHI KASEI
[AK4370]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
CDTI
C1
tCDH
C0
R/W
VIH
A4
VIL
Figure 7. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
D3
CDTI
D2
D1
VIH
D0
VIL
Figure 8. WRITE Data Input Timing
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Figure 9. I2C Bus Mode Timing
tPD
PDN
VIL
Figure 10. Power-down & Reset Timing
MS0595-J-00
2007/03
- 15 -
ASAHI KASEI
[AK4370]
■
I/F
2
AK4370
M/S bit
(See Table 1.)
M/S bit
(PDN pin = “L”)
“1”
“0”
“1”
M/S bit “1”
AK4370 LRCK, BICK pin
M/S bit
Mode
1
Master Mode
0
Slave Mode
AK4370
LRCK, BICK pin
100kΩ
MCKI pin
BICK pin
LRCK pin
Output
Output
FS3-0 bits
(1fs)
(BF bit
)
Input
Input
FS3-0 bits
(1fs)
(32fs ∼ 64fs)
Table 1. Clock pins state in Clock Mode
MCKI pin
FS3-0 bits
(Table 2)
DAC
Figure
Figure 11
Figure 12
default
(PMDAC bit = “1”)
“0”
“1”)
(M/S bit = “1”)
MCKI pin
LRCK
DAC
BICK
AK4370
(Figure 11)
(PMDAC bit =
(PMDAC bit = “0”)
AK4370
DSP or μP
MCKI
BICK
LRCK
256fs, 384fs, 512fs,
768fs or 1024fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTO
SDATA
Figure 11. Master Mode
MS0595-J-00
2007/03
- 16 -
ASAHI KASEI
[AK4370]
MCKI, BICK, LRCK
(Figure 12) MCKI
DAC
(PMDAC bit = “1”)
(M/S bit = “0”)
LRCK
(MCKI, BICK, LRCK)
DAC
(PMDAC bit = “0”)
AK4370
DSP or μP
256fs, 384fs, 512fs,
768fs or 1024fs
MCKI
32fs ~ 64fs
BICK
BCLK
1fs
LRCK
MCLK
LRCK
SDTO
SDATA
Figure 12. Slave Mode
Mode
0
1
2
4
5
6
8
9
10
12
13
Others
FS3
0
0
0
0
0
0
1
1
1
1
1
MCKI pin
BICK pin
LRCK pin
FS2
0
0
0
1
1
1
0
0
0
1
1
Others
Table 2.
FS1
0
0
1
0
0
1
0
0
1
0
0
FS0
0
1
0
0
1
0
0
1
0
0
1
fs
8kHz ∼ 48kHz
8kHz ∼ 48kHz
8kHz ∼ 24kHz
8kHz ∼ 48kHz
8kHz ∼ 48kHz
8kHz ∼ 24kHz
8kHz ∼ 48kHz
8kHz ∼ 48kHz
8kHz ∼ 24kHz
8kHz ∼ 48kHz
8kHz ∼ 24kHz
N/A
MCKI
MCKI
256fs
512fs
1024fs
256fs
512fs
1024fs
256fs
512fs
1024fs
384fs
768fs
N/A
Default
Master Mode (M/S bit = “1”)
Power Up (PMDAC bit = “1”)
Power Down (PMDAC bit = “0”)
Refer to Table 2.
Input or
fixed to “L” or “H” externally
BF bit = “1”: 64fs output
“L”
BF bit = “0”: 32fs output
Output
“L”
Table 3. Clock Operation in Master mode
MS0595-J-00
2007/03
- 17 -
ASAHI KASEI
MCKI pin
BICK pin
LRCK pin
[AK4370]
Slave Mode (M/S bit = “0”)
Power Up (PMDAC bit = “1”)
Power Down (PMDAC bit = “0”)
Refer to Table 2.
Input or fixed to “L” or “H” externally
Input
Fixed to “L” or “H” externally
Input
Fixed to “L” or “H” externally
Table 4. Clock Operation in Slave mode
DR, S/N
Table 5
DR, S/N
MCKI
DAC
DR,
S/N
MCKI
256fs/384fs/512fs
768fs/1024fs
Table 5. MCKI
DR, S/N (BW=20kHz, A-weight)
fs=8kHz
fs=16kHz
56dB
75dB
75dB
90dB
DR, S/N
(2.4V)
MS0595-J-00
2007/03
- 18 -
ASAHI KASEI
[AK4370]
■
SDATA, BICK, LRCK 3pin
(Table 6) DIF2-0 bits
Mode 1 Mode 0 20bit
2
3
LSB
5
Mode 0
16bitDAC
Mode 4 Mode 0 24bit
Mode 3 I2S
LSB
17∼24bit
8
16bit
21∼24bit
4
Mode 2
“0”
“0”
BICK=32fs(BF bit = “0”)
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
ADC
DSP
BICK≥48fs Mode
20bit
DIF0
0
1
0
1
0
Mode 1, 2, 4
BICK
32fs ≤ BICK ≤ 64fs
40fs ≤ BICK ≤ 64fs
48fs ≤ BICK ≤ 64fs
BICK=32fs or 48fs ≤ BICK ≤ 64fs
48fs ≤ BICK ≤ 64fs
0: 16bit,
1: 20bit,
2: 24bit,
3: I2S
4: 24bit,
Table 6.
Figure 13
Figure 14
Figure 15
Figure 16
Figure 14
Default
1
14
LRCK
BICK
(32fs)
SDATA
Mode 0
15
14
6
5
4
3
2
15
14
1
0
15
14
0
Don’t care
6
5
4
3
2
0
15
14
0
19
0
19
0
15
BICK
SDATA
Mode 0
Don’t care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 13. Mode 0
(LRP = BCKP bits = “0”)
LRCK
BICK
SDATA
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19:MSB, 0:LSB
SDATA
Mode 4
Don’t care
23
22
21
20
23
22
21
20
23:MSB, 0:LSB
Lch Data
Figure 14. Mode 1, 4
Rch Data
(LRP = BCKP bits = “0”)
MS0595-J-00
2007/03
- 19 -
ASAHI KASEI
[AK4370]
Rch
Lch
LRCK
BICK
SDATA
15
14
0
19
18
4
1
0
23
22
8
3
4
Don’t
care
15
14
0
Don’t
care
19
18
4
1
0
Don’t
care
23
22
8
3
4
Don’t
care
15
14
Don’t
care
19
18
Don’t
care
23
22
16bit
SDATA
20bit
SDATA
1
0
1
0
24bit
Figure 15. Mode 2
(LRP = BCKP bits = “0”)
Lch
LRCK
Rch
BICK
SDATA
16bit
SDATA
20bit
SDATA
15
14
0
19
18
4
1
0
23
22
8
3
4
1
0
15
14
6
5
4
3
2
Don’t
care
15
14
0
Don’t
care
19
18
4
1
0
Don’t
care
23
22
8
3
4
1
15
14
6
5
4
3
Don’t
care
15
Don’t
care
19
0
Don’t
care
23
2
1
24bit
BICK
(32fs)
SDATA
16bit
0
Figure 16. Mode 3
1
0
0
15
(LRP = BCKP bits = “0”)
MS0595-J-00
2007/03
- 20 -
ASAHI KASEI
[AK4370]
■
AK4370
MUTE
0.5dB
DAC
(Table 7) DATTC bit “1”
DATTC bit “0”
Lch, Rch
256
(DATT)
0dB
ATTL7-0 bit Lch, Rch
−127dB
ATTL7-0
Attenuation
ATTR7-0
FFH
0dB
FEH
−0.5dB
FDH
−1.0dB
FCH
−1.5dB
:
:
:
:
02H
−126.5dB
01H
−127.0dB
00H
Default
MUTE (−∞)
Table 7. Digital Volume ATT
ATT7-0
ATT
@fs=44.1kHz)
“0”
ATS bit 1061/fs 7424/fs
1062
FFH(0dB)
PDN pin “L”
ATT7-0 00H
00H
PMDAC bit “1”
ATS
0
1
Table 8.
ATT speed
0dB to MUTE
1 step
1061/fs
4/fs
7424/fs
29/fs
ATT7-0
MS0595-J-00
(Table 8) ATS bit = “0”
00H(MUTE)
1061/fs (24ms
ATT7-0 PMDAC bit
Default
2007/03
- 21 -
ASAHI KASEI
[AK4370]
■
×ATT
−∞
ATT
SMUTE bit
−∞ (“0”)
(Table 8)
×ATT
“1”
ATT
SMUTE bit
−∞
ATT
ATT
“0”
ATT
SMUTE bit
ATS bit
ATS bit
(1)
(1)
ATT Level
(3)
Attenuation
-∞
GD
(2)
GD
Analog Output
Figure 17.
Notes:
(1) ATT
3712/fs
(2)
(3)
×ATT
(Table 8)
ATS bit = “1”
ATT
“128”(−63.5dB)
(GD)
−∞
ATT
MS0595-J-00
2007/03
- 22 -
ASAHI KASEI
[AK4370]
■
IIR
3
DEM1-0 bit
(32kHz, 44.1kHz, 48kHz)
DEM1 bit
0
0
1
1
Table 9.
(50/15µs
(Table 9)
DEM0 bit
0
1
0
1
De-emphasis
44.1kHz
OFF
48kHz
32kHz
)
Default
■
BST1-0 bit
DAC
(Table 10)
BST1 bit
0
0
1
1
BST0 bit
0
1
0
1
Table 10.
BOOST
OFF
MIN
MID
MAX
Default
■
MONO1-0 bit
(Table 11)
DAC
MONO1 bit
0
0
1
1
Lch/Rch
MONO0 bit
0
1
0
1
Table 11.
Lch
L
L
R
(L+R)/2
Rch
R
L
R
(L+R)/2
Default
■
PDN pin = “L”
PDN pin = “L”
AK4370
VCOM, DAC, HPL, HPR, LOUT, ROUT
DAC
PMDAC bit
“1”
150ns
PDN pin
MCKI
MCKI
MS0595-J-00
2007/03
- 23 -
ASAHI KASEI
[AK4370]
■
(HPL, HPR pins)
HVDD
PMHPL=PMHPR bits = “1”
MUTEN bit “0”
16Ω
tr:
tf:
(VCOM/2
(VCOM/2
Table 12.
: MUTET pin
MUTET pin
MUTEN bit
“1”
VCOM(=0.475 x AVDD)
VSS1
70k x C (typ)
60k x C (typ)
)
)
C=1μF
(VCOM/2
(VCOM/2
): tr = 70k x 1μ = 70ms(typ)
): tf = 60k x 1μ = 60ms(typ)
PMHPL, PMHPR bits “0”
HPL, HPR pins VSS1
PMHPL/R bit
MUTEN bit
HPL/R pin
VCOM
VCOM/2
tf
tr
(1) (2)
(3)
(4)
Figure 18.
(1)
(2)
(PMHPL, PMHPR bits = “1”)
VSS1
(MUTEN bit = “1”) MUTET
MUTET pin
“C”
(tr)
70k x C(typ)
(3)
VSS1
VCOM/2
(4)
VCOM/2
(tf)
(MUTEN bit = “0”) MUTET
MUTET pin
60k x C(typ)
(PMHPL, PMHPR bits = “0”)
VSS1
MS0595-J-00
“C”
2007/03
- 24 -
ASAHI KASEI
[AK4370]
(fc)
Table 13
(fc)
AVDD=2.4, 3.0, 3.3V
RL 16Ω
0.48 x AVDD (Vpp)
@−3dBFS
HP-AMP
R
C
Headphone
16Ω
AK4370
Figure 19.
R [Ω]
0
6.8
16
C [μF]
fc [Hz]
BOOST=OFF
fc [Hz]
BOOST=MIN
220
100
100
47
100
47
45
100
70
149
50
106
17
43
28
78
19
47
Table 13.
Output Power [mW]
,
2.4V
3.0V
3.3V
21
33
40
10
16
20
5
8
10
f
Wired OR
PMVCM=PMHPL=PMHPR bits = “0”, HPZ bit = “1”
200kΩ(typ) VSS1
OR
PMVCM
x
0
1
1
PMHPL/R
0
0
1
1
HP-Amp
AK4370 HP-Amp
HPMTN
HPZ
Mode
x
0
Power-down & Mute
x
1
Power-down
0
x
Mute
1
x
Normal Operation
Table 14. HP-Amp Mode Setting (x: Don’t care)
HPL, HPR pins
HP-Amp Wired
HPL/R pins
VSS1
Pull-down by 200kΩ
VSS1
Normal Operation
Default
HPL pin
AK4370
Headphone
HPR pin
Another
HP-Amp
Figure 20.
Wired OR
MS0595-J-00
2007/03
- 25 -
ASAHI KASEI
[AK4370]
HPL
ON/OFF
DALHL, LIN1HL, RIN1HL, LIN2HL, RIN2HL bits
ON/OFF
DARHR, LIN1HR, RIN1HR, LIN2HR, RIN2HR bits
L1HM=L2HM=bits = “0”, HPG1-0 bits = “00” (R1H= R2H = RDH= 100k), ATTH4-0 bits = “00H”(0dB)
+0.95dB(typ)
HPG1-0 bit = “01” (RDH= 50k)
DAC
+6.95dB(typ)
HPG1-0 bit = “10” (RDH= 25k)
DAC
L1HM, L2HM bit
LIN1/RIN1, LIN2/RIN2
(L+R)/2
HPL/R
(R1H= R2H= 200k)
LDIF=LDIFH=LIN1L=RIN1R bits = “1”
HPL/R pins
LIN1/RIN1 pins
IN−/+ pins
LIN1HL, RIN1HL, LIN1HR, RIN1HR bits
OFF
VCOM
HPR
+12.95dB(typ)
“0”
(= 0.475 x AVDD)
Figure 39
100k(typ)
Figure 23
LDIFH bit
R1H
LIN1 pin
LIN1HL bit
R1H
RIN1 pin
RIN1HL bit
R2H
LIN2 pin
LIN2HL bit
R2H
RIN2 pin
100k(typ)
1.11RH
RIN2HL bit
RDH
DAC Lch
DALHL bit
−
RH
+
−
HPL pin
+
HP-Amp
100k(typ)
Figure 23
LDIFH bit
R1H
LIN1 pin
LIN1HR bit
R1H
RIN1 pin
RIN1HR bit
R2H
LIN2 pin
LIN2HR bit
R2H
100k(typ)
RIN2 pin
1.11RH
RIN2HR bit
RDH
DAC Rch
DARHR bit
−
RH
+
−
+
HPR pin
HP-Amp
Figure 21. HPL/R
MS0595-J-00
2007/03
- 26 -
ASAHI KASEI
[AK4370]
■
HPL/HPR
HMUTE bit = “0”
ATTH4-0 bit
+6dB ∼ −57dB or 0dB ∼ −63dB, 1.5dB or 3dB step Table 15)
HMUTE
0
1
ATTH4-0
00H
01H
02H
03H
:
:
12H
13H
14H
15H
16H
:
:
1DH
1EH
1FH
x
HPG1-0 bits = “10”
HPG1-0 bits = “01”
HPG1-0 bits = “00”
(DAC Only)
(DAC Only)
+12dB
+6dB
0dB
+10.5dB
+4.5dB
−1.5dB
+9dB
+3dB
−3dB
+7.5dB
+1.5dB
−4.5dB
:
:
:
:
:
:
−15dB
−21dB
−27dB
−16.5dB
−22.5dB
−28.5dB
−18dB
−24dB
−30dB
−21dB
−27dB
−33dB
−24dB
−30dB
−36dB
:
:
:
:
:
:
−45dB
−51dB
−57dB
−48dB
−54dB
−60dB
−51dB
−57dB
−63dB
MUTE
MUTE
MUTE
Table 15. HPL/HPR Volume ATT values (x: Don’t care)
MS0595-J-00
(+12dB ∼ −51dB or
STEP
Default
1.5dB
3dB
2007/03
- 27 -
ASAHI KASEI
[AK4370]
■
(LOUT, ROUT pins)
0.475 x AVDD
10kΩ
PMLO bit = “1”
ON/OFF
DALL, LIN1L, RIN1L, LIN2L, RIN2L bits
ON/OFF
DARR, LIN1R, RIN1R, LIN2R, RIN2R bits
bit = “0” (R1L= R2L = RDL= 100k), ATTS3-0 bits = “0FH”(0dB)
LOG bit = “1” (RDL= 50k)
DAC
+6dB
LIN1/RIN1, LIN2/RIN2
(L+R)/2
LOUT/ROUT
200k)
OFF
VCOM
LOUT
ROUT
L1M=L2M bits = “0”, LOG
0dB(typ)
L1M, L2M bit
(R1L= R2L=
(= 0.475 x AVDD)
Figure 39
R1L
LIN1 pin
LIN1L bit
R1L
RIN1 pin
RIN1L bit
R2L
LIN2 pin
LIN2L bit
R2L
100k(typ)
RIN2 pin
RL
RIN2L bit
RDL
DAC Lch
DALL bit
−
RL
+
−
LOUT pin
+
R1L
LIN1 pin
LIN1R bit
R1L
RIN1 pin
RIN1R bit
R2L
LIN2 pin
LIN2R bit
R2L
100k(typ)
RIN2 pin
RL
RIN2R bit
RDL
DAC Rch
DARR bit
−
RL
+
−
+
ROUT pin
Figure 22. LOUT/ROUT
MS0595-J-00
2007/03
- 28 -
ASAHI KASEI
[AK4370]
LDIF=LIN1L=RIN1R bits = “1”
LOUT/ROUT pins
LIN1/RIN1 pins
IN−/+ pins
LOUT/ROUT pins
OFF
VCOM
(= 0.475 x AVDD)
Figure 39
Figure 21
R1L
IN− pin
100k(typ)
HPL/R pins
LDIFH bit
RL
LIN1L bit
100k(typ)
LDIF bit
−
RL
+
−
LOUT pin
+
RL
R1L
IN+ pin
100k(typ)
RL
RIN1R bit
−
−
ROUT pin
+
+
Figure 23. LOUT/ROUT
(
LOG bit = “0”
)
■
(+6dB ∼ −24dB or
LOUT/ROUT
LMUTE bit = “0”
ATTS3-0 bit
0dB ∼ −30dB, 2dB step, Table 16) LOUT/ROUT
LMUTE
0
1
LOG bit = “1”
LOG bit = “0”
(DAC Only)
FH
+6dB
0dB
EH
+4dB
−2dB
DH
+2dB
−4dB
CH
0dB
−6dB
:
:
:
:
:
:
1H
−22dB
−28dB
0H
−24dB
−30dB
x
MUTE
MUTE
Table 16. LOUT/ROUT Volume ATT (x: Don’t care)
ATTS3-0
MS0595-J-00
Default
2007/03
- 29 -
ASAHI KASEI
[AK4370]
■
1) DAC → HP-Amp
(10)
Power Supply
(1)
>150ns
PDN pin
Don’t care
(2) >0s
PMVCM bit
Don’t care
(3)
Don’t care
Don’t care
Clock Input
PMDAC bit
DAC Internal
State
PD
Normal Operation
PD
Normal Operation
PD
SDTI pin
DALHL,
DARHR bits
(4) >0s
PMHPL,
PMHPR bits
(4) >0s
(5) >2ms
(5) >2ms
MUTEN bit
ATTL7-0
ATTR7-0 bits
00H(MUTE)
FFH(0dB)
(8) GD (9) 1061/fs
FFH(0dB)
00H(MUTE)
(8)
(8) (9)
(6)
(9)
00H(MUTE)
(8) (9)
(6)
(7)
(7)
HPL/R pin
Figure 24. DAC
(1) AVDD
DVDD
AVDD HVDD
150ns
(2) PDN pin “H”
(3) DAC
HP-amp
DVDD
1.6V
AVDD
PDN pin “H”
PMVCM, PMDAC bit “1”
(MCKI, BICK, LRCK)
(4) PMVCM, PMDAC bits “1”
(5) DALHL, DARHR bits “1”
PMHPL, PMHPR, MUTEN bits “1”
(6)
(tr) 70k x C(typ)
C=1μF
(7)
(tf) 60k x C(typ)
C=1μF
DARHR bits
)
AVDD
HVDD
PMDAC bit = “0”
DALHL, DARHR bits
2ms
(VCOM pin
“1”
MUTET pin
(C)
tr 70ms(typ)
MUTET pin
(C)
tf 60ms(typ)
PMHPL, PMHPR “0”
2.2μF
)
VCOM/2
VCOM/2
DALHL,
“0”
(8)
(9)
(10)
22/fs(=499µs@fs=44.1kHz)
(GD)
ATS bit
1061/fs(=24ms@fs=44.1kHz)
OFF
AVDD DVDD
DVDD
AVDD HVDD
AVDD
HVDD
(Don’t care: Hi-Z
AVDD
MS0595-J-00
2007/03
- 30 -
ASAHI KASEI
[AK4370]
2) DAC → Lineout
Power Supply
(1) >150ns
PDN pin
(2)
>0s
PMVCM bit
Don’t care
(5)
Clock Input
Don’t care
Don’t care
(4) >0s
PMDAC bit
DAC Internal
State
PD
Normal Operation
PD(Power-down)
Normal Operation
SDTI pin
DALL,
DARR bits
(3) >0s
PMLO bit
ATTL/R7-0 bits
LMUTE,
ATTS3-0 bits
FFH(0dB)
00H(MUTE)
Figure 25. DAC
FFH(0dB)
0FH(0dB)
10H(MUTE)
(7) GD
LOUT/ROUT pins
00H(MUTE)
(8) 1061/fs (7)
(6)
(8)
(7)
(Hi-Z)
(8)
(6)
(6)
(Hi-Z)
Lineout
(Don’t care: Hi-Z
)
(1) AVDD
(2)
(3)
(4)
(5)
(6)
(7)
(8)
DVDD
DVDD 1.6V
AVDD
AVDD HVDD
AVDD HVDD
150ns
PDN pin “H”
PDN pin “H”
PMVCM bit “1”
PMVCM bit “1”
DALL, DARR bits “1”
DALL, DARR bits “1”
PMDAC, PMLO bits “1”
DAC
(MCKI, BICK, LRCK)
PMDAC bit = “0”
LOUT/ROUT
PMLO bit
LOUT, ROUT pins
22/fs(=499µs@fs=44.1kHz)
(GD)
ATS bit
1061/fs(=24ms@fs=44.1kHz)
MS0595-J-00
2007/03
- 31 -
ASAHI KASEI
[AK4370]
3) LIN1/RIN1/LIN2/RIN2 → HP-Amp
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LIN1HL, LIN2HL,
RIN1HR, RIN2HR bits
(3) >0s
PMHPL/R bits
(5) >2ms
(5) >2ms
MUTEN bit
(4)
LIN1/RIN1/
LIN2/RIN2 pins
(Hi-Z)
(Hi-Z)
(7)
(6)
(6)
HPL/R pins
Figure 26. LIN1/RIN1/LIN2/RIN2
HP-amp
(1) AVDD
(2)
(3)
(4)
(5)
(6)
(7)
DVDD
DVDD 1.6V
AVDD
AVDD HVDD
AVDD HVDD
150ns
PDN pin “H”
DAC
(MCKI, BICK, LRCK)
PDN pin “H”
PMVCM bit “1”
PMVCM bit “1”
LIN1HL, LIN2HL, RIN1HR, RIN2HR bits “1”
LIN1HL, LIN2HL, RIN1HR, RIN2HR bits “1”
LIN1, RIN1, LIN2, RIN2
pin 0.475 x
AVDD
LIN1HL, LIN2HL, RIN1HR, RIN2HR bits “1”
2ms
(VCOM pin
2.2μF
)
PMHPL, PMHPR, MUTEN bits “1”
MUTET pin
(C)
VCOM/2
(tr) 70k x C(typ)
C=1μF
tr 70ms(typ)
MUTET pin
(C)
VCOM/2
(tf) 60k x C(typ)
C=1μF
tf 60ms(typ)
PMHPL, PMHPR bits “0”
LIN1HL,
LIN2HL, RIN1HR, RIN2HR bits “0”
MS0595-J-00
2007/03
- 32 -
ASAHI KASEI
[AK4370]
4) LIN1/RIN1/LIN2/RIN2 → Lineout
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
(3) >0s
LIN1L, RIN1R,
LIN2L, RIN2R bits
PMLO bit
(5) >2ms
(5) >2ms
(Hi-Z)
(4)
LIN1/RIN1/
LIN2/RIN2 pins
LMUTE,
ATTS3-0 bits
LOUT/ROUT pins
(Hi-Z)
0FH(0dB)
10H(MUTE)
(6)
(6)
(Hi-Z)
Figure 27. LIN1/RIN1/LIN2/RIN2
(6)
(Hi-Z)
LOUT/ROUT
(1) AVDD
DVDD
DVDD 1.6V
AVDD HVDD
AVDD HVDD
150ns
PDN pin “H”
DAC
(MCKI, BICK, LRCK)
(2) PDN pin “H”
PMVCM bit “1”
(3) PMVCM bit “1”
LIN1L, LIN2L, RIN1R, RIN2R bits “1”
(4) LIN1L, LIN2L, RIN1R, RIN2R bits “1”
LIN1, RIN1, LIN2, RIN2
(5) LIN1L, LIN2L, RIN1R, RIN2R bits “1”
PMLO bits “1”
(6) PMLO bit
LOUT, ROUT pins
2ms
MS0595-J-00
(VCOM pin
AVDD
pin
0.475 x AVDD
2.2μF
)
2007/03
- 33 -
ASAHI KASEI
[AK4370]
■
(1) 3
(I2C pin = “L”)
3
I/F
: CSN, CCLK, CDTI
I/F
Chip
address(2bits, “01”
), Read/Write(1bit, Fixed to “1”, Write only), Register address(MSB first, 5bits), Control
data(MSB first, 8bits)
CCLK
CCLK 16
1
CSN
“H”
CCLK
5MHz(max)
PDN pin = “L”
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “01”)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 28. 3
I/F
MS0595-J-00
2007/03
- 34 -
ASAHI KASEI
(2) I2C
AK4370
[AK4370]
(I2C pin = “H”)
Fast-mode (max:400kHz, Ver1.0)
I2C
(2)-1. WRITE
I2C
(Start Condition)
(Figure 35)
8bit
IC
AK4370
SCL
IC
“H”
SDA
“L”
7bit
(R/W)
CAD0 pin
6bit “001000”
(Figure 30)
1bit
(Acknowledge)
SDA
“1”
2
(Figure 31)
(Figure 32)
“L”
Figure 29
“H”
(Figure 36) R/W
(
3
AK4370
“0”
)
8bit MSB first
(Stop Condition)
(Figure 35)
“H”
R/W
SCL
AK4370
3bit
8bit MSB first
“H”
“0”
SDA
1
“13H”
“00H”
“H”
SDA
SCL
“L”
(Figure 37)
“H”
SCL
“L”
“H”
SDA
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
Data(n)
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 29. I2C
0
0
1
0
0
0
CAD0
R/W
A3
A2
A1
A0
D3
D2
D1
D0
(CAD0 pin
Figure 30. 1
0
0
0
A4
Figure 31.
D7
D6
D5
Figure 32.
)
2
D4
3
MS0595-J-00
2007/03
- 35 -
ASAHI KASEI
[AK4370]
(2)-2. READ
R/W
“1”
AK4370
READ
“13H”
“00H”
AK4370
2
READ
(2)-2-1.
AK4370
AK4370
(READ
WRITE
“n+1”
(R/W = “1”)
READ
)
“n”
1
READ
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
Data(n+2)
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 33. CURRENT ADDRESS READ
(2)-2-2.
READ
(R/W bit= “1”)
“0”)
WRITE
WRITE
AK4370
(R/W bit= “1”)
READ
(R/W =
AK4370
1
READ
S
T
A
R
T
SDA
S
S
T
A
R
T
R/W= “0”
Sub
Address(n)
Slave
Address
A
C
K
S
A
C
K
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 34. RANDOM ADDRESS READ
MS0595-J-00
2007/03
- 36 -
ASAHI KASEI
[AK4370]
SDA
SCL
S
P
start condition
stop condition
Figure 35.
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 36. I2C
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 37. I2C
MS0595-J-00
2007/03
- 37 -
ASAHI KASEI
[AK4370]
■
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
Register Name
Power Management
Clock Control 0
Clock Control 1
Mode Control 0
Mode Control 1
DAC Lch ATT
DAC Rch ATT
Headphone Out Select 0
Lineout Select 0
Lineout ATT
Reserved
Reserved
Reserved
Headphone Out Select 1
Headphone ATT
Lineout Select 1
Mono Mixing
Differential Select
Reserved
Reserved
PDN pin = “L”
PDN pin “L”
14H
1FH
“0”
“1”
D7
D6
D5
D4
D3
D2
D1
D0
0
FS3
0
0
ATS
ATTL7
ATTR7
HPG1
0
0
0
0
0
0
0
0
0
0
0
0
0
FS2
0
MONO1
DATTC
ATTL6
ATTR6
HPG0
LOG
0
0
0
0
0
HPZ
0
0
0
0
0
PMLO
FS1
M/S
MONO0
LMUTE
ATTL5
ATTR5
LIN2HR
LIN2R
0
0
0
0
0
HMUTE
0
0
0
0
0
MUTEN
FS0
MCKAC
BCKP
SMUTE
ATTL4
ATTR4
LIN2HL
LIN2L
0
0
0
0
0
ATTH4
0
0
0
0
1
PMHPR
0
BF
LRP
BST1
ATTL3
ATTR3
RIN1HR
RIN1R
ATTS3
0
0
0
RIN2HR
ATTH3
RIN2R
L2M
0
0
0
PMHPL
0
0
DIF2
BST0
ATTL2
ATTR2
LIN1HL
LIN1L
ATTS2
0
0
0
RIN2HL
ATTH2
RIN2L
L2HM
0
0
0
PMDAC
0
0
DIF1
DEM1
ATTL1
ATTR1
DARHR
DARR
ATTS1
0
0
0
LIN1HR
ATTH1
LIN1R
L1M
LDIFH
0
0
PMVCM
0
0
DIF0
DEM0
ATTL0
ATTR0
DALHL
DALL
ATTS0
0
0
0
RIN1HL
ATTH0
RIN1L
L1HM
LDIF
0
0
“1”
“0”
MS0595-J-00
2007/03
- 38 -
ASAHI KASEI
[AK4370]
■
Addr
00H
Register Name
Power Management 0
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
PMLO
R/W
0
D4
MUTEN
R/W
0
D3
PMHPR
R/W
0
D2
PMHPL
R/W
0
D1
PMDAC
R/W
0
D0
PMVCM
R/W
0
PMVCM: VCOM
0: Power OFF (Default)
1: Power ON
PMDAC: DAC
0: Power OFF (Default)
1: Power ON
OFF
ON
ATT
PMHPL: Lch
0: Power OFF (Default)
1: Power ON
HPL pin
VSS1 (0V)
PMHPR: Rch
0: Power OFF (Default)
1: Power ON
HPR pin
VSS1 (0V)
MUTEN:
0:
1:
(Default)
DC
VSS1(0V)
0.475 x AVDD
PMLO:
0: Power OFF (Default)
1: Power ON
ON/OFF
PDN pin
Hi-Z
“1” /“0”
“L”
PMVCM, PMDAC, PMHPL, PMHPR, PMLO bits
“0”
20μA(typ)
(typ. 1μA)
PDN pin = “L”
MS0595-J-00
2007/03
- 39 -
ASAHI KASEI
Addr
01H
[AK4370]
Register Name
Clock Control 0
R/W
Default
D7
FS3
R/W
1
D6
FS2
R/W
0
D5
FS1
R/W
0
D4
FS0
R/W
0
D7
0
RD
0
D6
0
RD
0
D5
M/S
R/W
0
D4
MCKAC
R/W
0
D6
MONO1
R/W
0
D5
MONO0
R/W
0
D4
BCKP
R/W
0
D3
0
RD
0
D2
0
RD
0
D1
0
RD
0
D0
0
RD
0
D3
BF
R/W
0
D2
0
RD
0
D1
0
RD
0
D0
0
RD
0
D2
DIF2
R/W
0
D1
DIF1
R/W
1
D0
DIF0
R/W
0
FS3-0:
See Table 2
Addr
02H
Register Name
Clock Control 1
R/W
Default
BF:
BICK
0: 32fs (Default)
1: 64fs
MCKAC: MCKI
0: CMOS
1: AC
M/S:
(Default)
/
0:
1:
Addr
03H
(Default)
Register Name
Mode Control 0
R/W
Default
D7
0
RD
0
DIF2-0:
D3
LRP
R/W
0
(Table 6)
Default: “010” (Mode 2)
LRP: LRCK
0:
1:
(
(Default)
BCKP: BICK
(
0:
(Default)
1:
MONO1-0:
Default: “00” (LR)
)
)
(Table 11)
MS0595-J-00
2007/03
- 40 -
ASAHI KASEI
Addr
04H
[AK4370]
Register Name
Mode Control 1
R/W
Default
D7
ATS
R/W
0
DEM1-0:
Default: “01” (OFF)
D6
DATTC
R/W
0
D5
LMUTE
R/W
1
D4
SMUTE
R/W
0
D3
BST1
R/W
0
D2
BST0
R/W
0
D1
DEM1
R/W
0
D0
DEM0
R/W
1
(Table 9)
BST1-0:
(Table 10)
Default: “00” (OFF)
SMUTE: DAC
0:
1: DAC
(Default)
LMUTE: LOUT/ROUT
0:
ATTS3-0 bits
1: Mute ATTS3-0 bits
(Table 16)
(Default)
DATTC:
0: Independent (Default)
1: Dependent
“0” Lch, Rch
DATTC bit = “1”
ATS:
“1” Lch ATT
ATTR7-0 bit
ATTL7-0 bit
Rch
ATT
(Table 8)
0: 1061/fs (Default)
1: 7424/fs
Addr
05H
06H
Register Name
DAC Lch ATT
DAC Rch ATT
R/W
Default
D7
ATTL7
ATTR7
R/W
0
D6
ATTL6
ATTR6
R/W
0
D5
ATTL5
ATTR5
R/W
0
ATTL7-0: DAC Lch
ATTR7-0: DAC Rch
Default: “00H” (MUTE)
D4
ATTL4
ATTR4
R/W
0
D3
ATTL3
ATTR3
R/W
0
D2
ATTL2
ATTR2
R/W
0
D1
ATTL1
ATTR1
R/W
0
D0
ATTL0
ATTR0
R/W
0
(Table 7)
(Table 7)
MS0595-J-00
2007/03
- 41 -
ASAHI KASEI
Addr
07H
Register Name
Headphone Out Select 0
R/W
Default
[AK4370]
D7
HPG1
R/W
0
D6
HPG0
R/W
0
D5
LIN2HR
R/W
0
DALHL: DAC Lch
0: OFF (Default)
1: ON
Lch
DARHR: DAC Rch
0: OFF (Default)
1: ON
Rch
D4
LIN2HL
R/W
0
LIN1HL: LIN1 pin
0: OFF (Default)
1: ON
Lch
RIN1HR: RIN1 pin
0: OFF (Default)
1: ON
Rch
LIN2HL: LIN2 pin
0: OFF (Default)
1: ON
Lch
LIN2HR: LIN2 pin
0: OFF (Default)
1: ON
Rch
D3
RIN1HR
R/W
0
D2
LIN1HL
R/W
0
D1
DARHR
R/W
0
D0
DALHL
R/W
0
HPG1-0: DAC Æ HPL/R Gain (Table 15)
Default: “00”: +0.95dB
MS0595-J-00
2007/03
- 42 -
ASAHI KASEI
Addr
08H
[AK4370]
Register Name
Lineout Select 0
R/W
Default
D7
0
RD
0
DALL: DAC Lch
0: OFF (Default)
1: ON
LOUT
DARR: DAC Rch
0: OFF (Default)
1: ON
ROUT
D6
LOG
R/W
0
LIN1L: LIN1 pin
0: OFF (Default)
1: ON
LOUT
RIN1R: RIN1 pin
0: OFF (Default)
1: ON
ROUT
LIN2L: LIN2 pin
0: OFF (Default)
1: ON
LOUT
LIN2R: LIN2 pin
0: OFF (Default)
1: ON
ROUT
D5
LIN2R
R/W
0
D4
LIN2L
R/W
0
D3
RIN1R
R/W
0
D2
LIN1L
R/W
0
D1
DARR
R/W
0
D0
DALL
R/W
0
D5
0
RD
0
D4
0
RD
0
D3
ATTS3
R/W
0
D2
ATTS2
R/W
0
D1
ATTS1
R/W
0
D0
ATTS0
R/W
0
LOG: DAC Æ LOUT/ROUT Gain
0: 0dB (Default)
1: +6dB
Addr
09H
Register Name
Lineout ATT
R/W
Default
D7
0
RD
0
D6
0
RD
0
ATTS3-0: LOUT/ROUT
(Table 16)
Default: LMUTE bit = “1”, ATTS3-0 bits = “0000” (MUTE)
ATTS3-0 bits
LMUTE bit
“0”
MS0595-J-00
2007/03
- 43 -
ASAHI KASEI
Addr
0DH
[AK4370]
Register Name
Headphone Out Select 1
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
RIN1HL: RIN1 pin
0: OFF (Default)
1: ON
Lch
LIN1HR: LIN1 pin
0: OFF (Default)
1: ON
Rch
RIN2HL: RIN2 pin
0: OFF (Default)
1: ON
Lch
RIN2HR: RIN2 pin
0: OFF (Default)
1: ON
Rch
Addr
0EH
Register Name
Headphone ATT
R/W
Default
D7
0
RD
0
D6
HPZ
R/W
0
D5
HMUTE
R/W
0
D4
ATTH4
R/W
0
D3
RIN2HR
R/W
0
D2
RIN2HL
R/W
0
D1
LIN1HR
R/W
0
D0
RIN1HL
R/W
0
D3
ATTH3
R/W
0
D2
ATTH2
R/W
0
D1
ATTH1
R/W
0
D0
ATTH0
R/W
0
ATTH4-0: HPL/HPR
(Table 15)
Default: HMUTE bit = “0”, ATTH4-0 bits = “00H” (0dB)
ATTH4-0 bits
HMUTE bit
HMUTE: HPL/HPR
0:
ATTH4-0 bits
1: Mute ATTH4-0 bits
HPZ: HP-Amp
0:
1: 200kΩ(typ)
“0”
(Table 15)
(Default)
(Default)
MS0595-J-00
2007/03
- 44 -
ASAHI KASEI
Addr
0FH
Register Name
Lineout Select
R/W
Default
[AK4370]
D7
0
RD
0
D6
0
RD
0
RIN1L: RIN1 pin
0: OFF (Default)
1: ON
LOUT
LIN1R: LIN1 pin
0: OFF (Default)
1: ON
ROUT
RIN2L: RIN2 pin
0: OFF (Default)
1: ON
LOUT
RIN2R: RIN2 pin
0: OFF (Default)
1: ON
ROUT
Addr
10H
Register Name
Mono Mixing
R/W
Default
D7
0
RD
0
D6
0
RD
0
L1HM: LIN1/RIN1 pins
0: OFF (Default)
1: ON
LDIFH: IN+/− pins
0: OFF (Default)
1: ON
D2
RIN2L
R/W
0
D1
LIN1R
R/W
0
D0
RIN1L
R/W
0
D5
0
RD
0
D4
0
RD
0
D3
L2M
R/W
0
D2
L2HM
R/W
0
D1
L1M
R/W
0
D0
L1HM
R/W
0
D2
0
RD
0
D1
LDIFH
R/W
0
D0
LDIF
R/W
0
(L+R)/2
L2M: LIN2/RIN2 pins
0: OFF (Default)
1: ON
LDIF: IN+/− pins
0: OFF (Default)
1: ON
LDIF bit = “1”
D3
RIN2R
R/W
0
(L+R)/2
L2HM: LIN2/RIN2 pins
0: OFF (Default)
1: ON
Register Name
Differential Select
R/W
Default
D4
0
RD
0
(L+R)/2
L1M: LIN1/RIN1 pins
0: OFF (Default)
1: ON
Addr
11H
D5
0
RD
0
(L+R)/2
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
HPL/R
LOUT/ROUT
HPL/R
LOUT/ROUT
D4
0
RD
0
D3
0
RD
0
LOUT/ROUT
LIN1/RIN1
IN+/IN−
HPL/R
(LDIF bit = “1”
MS0595-J-00
)
2007/03
- 45 -
ASAHI KASEI
[AK4370]
Figure 38
Analog Supply
+
1.6∼3.6V
10µ
0.1µ
Speaker
2.2µ
+
16
15
14
13
AVDD
VCOM
ROUT
LOUT
SPK-Amp
19 HPR
MUTET
12
20 HPL
I2C
11
8
24 LIN1
CDTI
7
VSS2
CCLK
6
23 RIN1
DVDD
9
5
CSN
MCKI
Top View
4
22 LIN2
LRCK
10
3
PDN
BICK
AK4370VN
SDATA
21 RIN2
2
Headphone
17
16Ω
1
16Ω
18
+
220µ
HVDD
220µ
+
VSS1
0.1µ
1µ
10
1000p
0.1µ
Analog Ground
Digital Ground
Audio Controller
:
- AK4370
-
- AVDD
0.1μF
µP
VSS1, VSS2
M/S bit
10Ω
Figure 38.
“1”
AK4370
DVDD
(MCKI
AC
MS0595-J-00
AK4370 LRCK, BICK pins
LRCK, BICK pins 100kΩ
DVDD
)
2007/03
- 46 -
ASAHI KASEI
[AK4370]
AVDD
AK4370
110k
LIN1 pin
HP-Amp
LIN1HL bit
100k
:
OFF
VCOM
(= 0.475 x AVDD)
Figure 39.
1.
AVDD, HVDD
AVDD
10Ω
DVDD
AVDD
HVDD
VSS1, VSS2
AVDD
1.6V
DVDD
AVDD
AVDD HVDD
OFF
HVDD
DVDD
DVDD
OFF
AVDD
PC
2.
AVDD
AVDD
VCOM 0.475 x AVDD
2.2μF
VCOM pin
AVDD pin
VSS1
0.1μF
(typ)
VSS1
VCOM pin
3.
DAC
VCOM
VCOM
0.48xAVDD(typ)@−3dBFS LOUT/ROUT
0.61xAVDD(typ)@0dBFS
2’s
800000H(@24bit)
VCOM
VCOM+ mV
DC
VCOM
(2
)
7FFFFFH(@24bit)
000000H(@24bit)
DC
MS0595-J-00
2007/03
- 47 -
ASAHI KASEI
[AK4370]
24pin QFN (Unit: mm)
4.0 ± 0.1
2.4 ± 0.15
13
18
19
2.4± 0.15
4.0 ± 0.1
12
A
Exposed
Pad
24
7
0.40 ± 0.1
6
1
B
0.2
0.08
0.5
:
0.10 M
PIN #1 ID
(0.35 x 45 )
0.75± 0.05
0.23 ± 0.05
(Exposed Pad)
■
:
:
:
MS0595-J-00
2007/03
- 48 -
ASAHI KASEI
[AK4370]
4370
XXXX
1
XXXX : Date code identifier (4 )
Date (YY/MM/DD)
07/03/23
Revision
00
Reason
Page
Contents
•
•
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•
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MS0595-J-00
2007/03
- 49 -