AK4552 Data Sheet

ASAHI KASEI
[AK4552]
AK4552
3V 96kHz 24Bit ∆Σ CODEC
GENERAL DESCRIPTION
The AK4552 is a low voltage 24bit 96kHz A/D & D/A converter for digital audio system. In the AK4552,
the loss of accuracy form clock jitter is also improved by using SCF techniques for on-chip post filter.
Analog signal input/output of the AK4552 are single-ended, therefore, any external filters are not
required. As the package is 16pin TSSOP, the AK4552 is a suitable for minimizing system.
FEATURES
† HPF for DC-offset cancel ([email protected]=44.1kHz)
† Single-ended ADC
- S/(N+D): [email protected]=3.0V
- Dynamic Range, S/N: [email protected]=3.0V
† Single-ended DAC
- Digital de-emphasis for 32kHz, 44.1kHz and 48kHz sampling
- S/(N+D): [email protected]=3.0V
- Dynamic Range, S/N: [email protected]=3.0V
† Audio I/F format: MSB First, 2’s Compliment
- ADC: 24bit MSB justified, DAC: 24bit LSB justified
† Input/Output Voltage: ADC = [email protected]=3.0V
DAC = [email protected]=3.0V
† Sampling Rate: 8kHz to 50kHz (Normal Speed)
50kHz to 100kHz (Double Speed, Double Speed Monitor)
100kHz to 200kHz (Quad Speed Monitor)
† Master Clock: 256fs, 384fs, 512fs or [email protected] Speed
256fs or [email protected] Speed
128fs or [email protected] Speed Monitor
64fs, 96fs, 128fs or [email protected] Speed Monitor
† Power Supply: 2.4 to 4.0V
† Power Supply Current: 14mA
† Ta = -40 to 85°C
† Very Small Package: 16pin TSSOP
VA
LIN
RIN
VCOM
VSS
VD
∆Σ
Modulator
Decimation
Filter
∆Σ
Modulator
Decimation
Filter
Clock
Divider
MCLK
LRCK
BCLK
Serial I/O
Interface
Common Voltage
SDTO
SDTI
DEM0
LOUT
ROUT
LPF
∆Σ
Modulator
Interpolator
LPF
∆Σ
Modulator
Interpolator
MS0055-E-01
8X
DEM1
8X
PDN
2001/02
-1-
ASAHI KASEI
[AK4552]
„ Ordering Guide
-40 ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4552
AK4552VT
AKD4552
„ Pin Layout
RIN
1
16
ROUT
LIN
2
15
LOUT
VSS
3
14
VCOM
VA
4
13
PDN
VD
5
12
BCLK
DEM0
6
11
MCLK
DEM1
7
10
LRCK
SDTO
8
9
SDTI
Top
View
PIN/FUNCTION
No.
Pin Name
I/O
Function
1
2
3
4
5
6
7
8
9
10
11
12
RIN
LIN
VSS
VA
VD
DEM0
DEM1
SDTO
SDTI
LRCK
MCLK
BCLK
I
I
I
I
O
I
I
I
I
13
PDN
I
14
15
16
VCOM
LOUT
ROUT
O
O
O
Rch Analog Input Pin
Lch Analog Input Pin
Ground Pin
Analog Power Supply Pin
Digital Power Supply Pin
De-emphasis Control Pin
De-emphasis Control Pin
Audio Serial Data Output Pin
Audio Serial Data Input Pin
Input/Output Channel Clock Pin
Master Clock Input Pin
Audio Serial Data Clock Pin
Power-Down & Reset Mode Pin
“L”: Power-down and Reset, “H”: Normal operation
Common Voltage Output Pin, 0.45 x VA
Lch Analog Output Pin
Rch Analog Output Pin
MS0055-E-01
2001/02
-2-
ASAHI KASEI
[AK4552]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter
Analog Power Supply
Power Supply
Digital Power Supply
Input Current (Any Pin Except Supplies)
Analog Input Voltage (LIN, RIN pin)
Digital Input Voltage
Ambient Temperature (power applied)
Storage Temperature
Symbol
VA
VD
IIN
VINA
VIND
Ta
Tstg
min
-0.3
-0.3
-0.3
-0.3
-40
-65
max
4.6
4.6
±10
VA+0.3
VD+0.3
85
150
Units
V
V
mA
V
V
°C
°C
Note: 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter
Power Supply Analog Power Supply
Digital Power Supply (Note 2)
Symbol
VA
VD
min
2.4
2.4 or VA-0.3
typ
3.0
3.0
max
4.0
4.0
Units
V
V
Note: 1. All voltages with respect to ground.
Note: 2. Min Value is high value either 2.4V or VA-0.3V.
*AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
MS0055-E-01
2001/02
-3-
ASAHI KASEI
[AK4552]
ANALOG CHARACTERISTICS
(Ta=25°C; VA, VD=3.0V; VSS=0V; fs=44.1kHz; Signal Frequency=1kHz; BCLK=64fs;
Measurement frequency=10Hz ∼ 20kHz at fs=44.1kHz, 20Hz ∼ 40kHz at fs=96kHz; unless otherwise specified)
Parameter
min
typ
max
ADC Analog Input Characteristics: (Note 3)
Resolution
24
S/(N+D)
(-0.5dB Input) fs=44.1kHz
80
89
fs=96kHz
80
89
D-Range
(-60dB Input) fs=44.1kHz, A-weighted
90
97
fs=96kHz
87
94
fs=96kHz, A-weighted
100
S/N
fs=44.1kHz, A-weighted
90
97
fs=96kHz
87
94
fs=96kHz, A-weighted
100
Interchannel Isolation
90
110
Interchannel Gain Mismatch
0.2
0.5
Input Voltage
(Note 4)
1.65
1.85
2.05
Input Resistance
fs=44.1kHz
20
34
fs=96kHz
14
24
DAC Analog Output Characteristics:
Resolution
24
S/(N+D)
(0dB Output)
fs=44.1kHz
78
88
fs=96kHz
75
85
fs=44.1kHz, A-weighted
93
100
D-Range
(-60dB Output)
fs=96kHz
88
96
fs=96kHz, A-weighted
100
fs=44.1kHz, A-weighted
93
100
S/N
fs=96kHz
88
96
fs=96kHz, A-weighted
100
Interchannel Isolation
90
110
Interchannel Gain Mismatch
0.2
0.5
Output Voltage
(Note 4)
1.56
1.75
1.94
Load Resistance
10
Load Capacitance
30
Power Supplies
Power Supply Current (VA+VD)
Power up
PDN = “H”
Power down
(Note 5)
fs=44.1kHz
fs=96kHz
PDN = “L”
14
18
10
Units
21
27
100
Bits
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Vpp
kΩ
kΩ
Bits
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Vpp
kΩ
pF
mA
mA
µA
Note: 3. The offset of ADC is removed by internal HPF.
Note: 4. Input/Output of ADC and DAC scales with VA voltage. (ADC = 0.617 x VA, DAC = 0.583 x VA)
Note: 5. In case of power-down mode, all digital input including clocks pins (MCLK, BCLK, LRCK) are held VD
or VSS. But PDN pin is held VSS.
MS0055-E-01
2001/02
-4-
ASAHI KASEI
[AK4552]
FILTER CHARACTERISTICS
(Ta=25°C; VA, VD=2.4 ∼ 4.0V; fs=44.1kHz; DEM0=“1”, DEM1=“0”)
Parameter
Symbol
min
ADC Digital Filter (Decimation LPF):
PB
0
Passband
(Note 6) ±0.1dB
-1.0dB
-3.0dB
Stopband
(Note 6)
SB
27.0
Passband Ripple
PR
Stopband Attenuation
SA
65
Group Delay
(Note 7)
GD
Group Delay Distortion
∆GD
ADC Digital Filter (HPF):
Frequency Response (Note 6) -3dB
FR
-0.5dB
-0.1dB
DAC Digital Filter:
PB
0
Passband
(Note 6) ±0.1dB
-6.0dB
Stopband
(Note 6)
SB
24.1
Passband Ripple
PR
Stopband Attenuation
SA
43
Group Delay
(Note 7)
GD
Group Delay Distortion
∆GD
DAC Digital Filter + Analog Filter
Frequency Response 0 ∼ 20.0kHz
FR
∼ 40.0kHz (Note 8)
typ
max
Units
17.4
17.0
0
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
3.4
10
22
Hz
Hz
Hz
20.0
21.1
±0.1
20.0
15.4
0
kHz
kHz
kHz
dB
dB
1/fs
µs
±0.5
±1.0
dB
dB
22.05
±0.06
Note: 6. The passband and stopband frequencies scale with fs (sampling frequency).
For examples, PB=20.0kHz(@ADC: -1.0dB, DAC: -0.1dB) are 0.454 x fs.
Note: 7. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to
setting the 24bit data of both channels to the output register for ADC. For DAC, this time is from setting the
24bit data of both channels on input register to the output of analog signal.
Note: 8. fs=96kHz.
DC CHARACTERISTICS
(Ta=25°C; VA, VD=2.4 ∼ 4.0V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout=-20µA)
Low-Level Output Voltage
(Iout=20µA)
Input Leakage Current
Symbol
VIH
VIL
VOH
VOL
Iin
MS0055-E-01
min
70%VD
VD-0.1
-
typ
-
max
30%VD
0.1
± 10
Units
V
V
V
V
µA
2001/02
-5-
ASAHI KASEI
[AK4552]
SWITCHING CHARACTERISTICS
(Ta=25°C; VA, VD=2.4 ∼ 4.0V; CL=20pF)
Parameter
Master Clock Timing
Frequency
Pulse Width Low
Pulse Width High
LRCK Frequency
Normal Speed
Double Speed
Quad Speed
Duty Cycle
Serial Interface Timing
BCLK Period
Normal Speed
Double Speed
Quad Speed
BCLK Pulse Width Low
Pulse Width High
LRCK Edge to BCLK “↑”
(Note 9)
BCLK “↑” to LRCK Edge
(Note 9)
LRCK Edge to SDTO (MSB)
BCLK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
Reset Timing
PDN Pulse Width
PDN “↑” to SDTO Valid
(Note 10)
Symbol
min
typ
max
fCLK
tCLKL
tCLKH
2.048
10
10
38.4
MHz
ns
ns
fsn
fsd
fsq
Duty
8
50
100
45
50
100
200
55
kHz
kHz
kHz
%
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tDLR
tDBS
tSDH
tSDS
1/96fsn
1/64fsd
1/64fsq
33
33
20
20
tPW
tPWV
150
40
40
20
20
2081
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
Note: 9. BCLK rising edge must not occur at the same time as LRCK edge.
Note: 10. These cycles are the number of LRCK rising from PDN rising.
MS0055-E-01
2001/02
-6-
ASAHI KASEI
[AK4552]
„ Timing Diagram
1/fCLK
VIH
VIL
MCLK
tCLKH
tCLKL
1/fs
VIH
VIL
LRCK
tBCK
VIH
VIL
BCLK
tBCKH
tBCKL
Figure 1. Clock Timing
VIH
VIL
LRCK
tBLR
tLRB
VIH
VIL
BCLK
tDLR
tDBS
SDTO
50%VD
tSDS
tSDH
VIH
VIL
SDTI
Figure 2. Audio Data Input/Output Timing
tPW
PDN
VIL
tPWV
SDTO
50%VD
Figure 3. Reset Timing
MS0055-E-01
2001/02
-7-
ASAHI KASEI
[AK4552]
OPERATION OVERVIEW
„ System Clock Input
The relationship between the clock applied to the MCLK input and sampling rate is defined Table 1. The AK4552 detects
the changes of normal speed, double speed and quad speed automatically, ADC and DAC operation in Table 2 are decided
by inputted MCLK. In case of double speed, there are normal output and 1/2 decimation output in DAC. Selected 1/2
decimation, ADC outputs “L”, but not power-down. In case of 4 times speed, there are 1/2 decimation and 1/4 decimation
output in DAC, but not normal output. Selected 1/2 and 1/4 decimation, ADC outputs “L” but not power-down. The LRCK
clock input must be synchronized with MCLK, however the phase is not critical. *fs is sampling frequency.
Changed MCLK in operation, the AK4552 need not reset by PDN pin because the AK4552 detects the change of MCLK
automatically. But ADC and DAC may occur click noise until the clock is stable. However, if the clock may be stopped
when it is changed, the AK4552 is powered down.
All external clocks (MCLK, BCLK, LRCK) must be present unless PDN = “L”. If these clocks are not provided, the
AK4552 may draw excess current and may not possibly operate properly because the device utilizes dynamic refreshed
logic internally.
MCLK
64fs
96fs
128fs
192fs
256fs
384fs
512fs
768fs
MCLK
64fs
96fs
128fs
192fs
256fs
384fs
512fs
768fs
Normal Speed
Double Speed
Quad Speed
(fs=44.1kHz)
(fs=88.2kHz)
(fs=176.4kHz)
N/A
N/A
11.2896MHz
N/A
N/A
16.9344MHz
N/A
11.2896MHz
22.5792MHz
N/A
16.9344MHz
33.8688MHz
11.2896MHz
22.5792MHz
N/A
16.9344MHz
33.8688MHz
N/A
22.5792MHz
N/A
N/A
33.8688MHz
N/A
N/A
Table 1. Master Clock Frequency Example
Normal Speed
Double Speed
Quad Speed
ADC
N/A
N/A
“L” Output
DAC
N/A
N/A
1/4 Decimation
ADC
N/A
N/A
“L” Output
DAC
N/A
N/A
1/4 Decimation
ADC
N/A
“L” Output
“L” Output
DAC
N/A
1/2 Decimation
1/2 Decimation
ADC
N/A
“L” Output
“L” Output
DAC
N/A
1/2 Decimation
1/2 Decimation
ADC
O
O
N/A
DAC
O
O
N/A
ADC
O
O
N/A
DAC
O
O
N/A
ADC
O
N/A
N/A
DAC
O
N/A
N/A
ADC
O
N/A
N/A
DAC
O
N/A
N/A
Table 2. Master Clock Frequency & ADC/DAC Operation
* In Table 2, “O” mark is normal output, N/A is “Not Available”.
MS0055-E-01
2001/02
-8-
ASAHI KASEI
[AK4552]
• About the data operation in internal DAC at Decimation
See the Figure 4. The 1/2 decimation takes in one data per 2 periods of LRCK, and the 1/4 decimation takes in one
data per 4 periods of LRCK. Therefore, 1/2 decimation outputs a signal which has bandwidth until fs/2, and 1/4
decimation outputs a signal which has bandwidth until fs/4.
LRCK
SDTI
Input Data
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
24bit, LSB justified
Normal Output
24bit, LSB justified
SDTI
1/2 Decimation
SDTI
1/4 Decimation
24bit, LSB justified
24bit, LSB justified
Figure 4. About the data operation in internal DAC at Decimation
MS0055-E-01
2001/02
-9-
ASAHI KASEI
[AK4552]
„ Audio Serial Interface Format
Data is shifted in/out the SDTI/SDTO pins using BCLK and LRCK inputs. The data is MSB first, 2’s compliment.
LRCK
0
1
2
8
9
10
24
21
31
0
1
2
8
9
10
24
21
31
0
1
BCLK(64fs)
SDTO(o)
SDTI(i)
23 22
16 15 14
Don’t Care
23:MSB, 0:LSB
23 22
0
23 22
12 11
1
0
16 15 14
Don’t Care
Lch Data
23 22
0
12 11
23
1
0
Rch Data
Figure 5. Audio Data I/F Timing
„ De-emphasis Filter
The DAC of AK4552 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. This filter corresponds to three
frequencies (32kHz, 44.1kHz, 48kHz). The de-emphasis filter selected by DEM0 and DEM1 is enabled for input audio
data. The de-emphasis is also disabled at DEM0=“1” and DEM1=“0”.
DEM1
DEM0
Mode
0
0
44.1kHz
0
1
OFF
1
0
48kHz
1
1
32kHz
Table 3. De-emphasis filter control
„ Digital High Pass Filter
The AK4552 has a Digital High Pass Filter (HPF) for DC-offset cancel. The cut-off frequency of the HPF is 3.4Hz at
fs=44.1kHz and the frequency response at 20Hz is -0.12dB. It also scales with the sampling frequency (fs).
MS0055-E-01
2001/02
- 10 -
ASAHI KASEI
[AK4552]
„ Power-down & Reset
The ADC and DAC of AK4552 are placed in the power-down mode by bringing power down pin, PDN = “L” and each
digital filter is also reset at the same time. These resets should always be done after power-up. In case of the ADC, an anlog
initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO becomes available after
2081 cycles of LRCK clock. This initialization cycle does not affect the DAC operation. Figure 6 shows the power-up
sequence.
PDN
2081/fs
ADC Internal
State
Normal Operation
DAC Internal
State
Normal Operation
Power-down
Init Cycle
Normal Operation
Normal Operation
Power-down
GD
GD
ADC In
(Analog)
ADC Out
(Digital)
“0”data
Idle Noise
DAC In
(Digital)
“0”data
GD
DAC Out
(Analog)
Idle Noise
GD
(1)
(1)
Clock In
MCLK,LRCK,BCLK
The clocks may be stopped.
External
Mute
Mute ON
Figure 6. Power-up Sequence
(1) Click noise occurs at the “↑↓” of PDN signal. Please mute the analog output external if the click noise influences
system application.
MS0055-E-01
2001/02
- 11 -
ASAHI KASEI
[AK4552]
SYSTEM DESIGN
Figure 7 shows the system connection diagram. An evaluation board [AKD4552] is available which demonstrates
application circuit, optimum layout, power supply arrangements and measurement results.
10u 0.1u
2.4V ~ 4.0V
Analog Supply
+
+
10 ohm
Mode
Control
1 RIN
ROUT 16
2 LIN
LOUT 15
3 VSS
VCOM 14
4 VA
5 VD
AK4552
PDN 13
+
1u
0.1u
Reset
BCLK 12
10u 0.1u
6 DEM0
MCLK 11
7 DEM1
LRCK 10
8 SDTO
SDTI 9
Audio
Controller
Figure 7. System Connection Diagram Example
Notes:
- When LOUT/ROUT drives some capacitive load, some resistor should be added in series between LOUT/ROUT and
capacitive load.
- Electrolytic capacitor value of VCOM depends on low frequency noise of supply voltage.
MS0055-E-01
2001/02
- 12 -
ASAHI KASEI
[AK4552]
1. Grounding and Power Supply Decoupling
The AK4552 requires careful attention to power supply and grounding arrangements. VA and VD are usually supplied
from analog supply in system. Alternatively if VA and VD are supplied separately, the power up sequence is not critical.
VSS of the AK4552 should be connected to analog ground plane. System analog ground and digital ground should be
connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be
as near to the AK4552 as possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference
The input to VA voltage sets the analog input/output range. A 0.1µF ceramic capacitor and a 10µF electrolytic capacitor is
connected to VA and VSS pins, normally. VCOM is a signal ground of this chip. An electrolytic less than 1µF (typ; max:
2.2µF) in parallel with a 0.1µF ceramic capacitor attached to these pins eliminates the effects of high frequency noise. No
load current may be drawn from VCOM pin. All signals, especially clock, should be kept away from the VA, VD and
VCOM pins in order to avoid unwanted coupling into the AK4552.
3. Analog Inputs
ADC inputs are single-ended and internally biased to VCOM. The input signal range scales with the supply voltage and
nominally 0.617 x VA Vpp (typ). The ADC output data format 2’s compliment. The output code is 7FFFFFH(@24bit) for
input above a positive full scale and 800000H(@24bit) for input below a negative full scale. The ideal code is
000000H(@24bit) with no input signal.
The AK4552 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of
64fs. A simple RC filter may be used to attenuate any noise around 64fs and most audio signals do not have significant
energy at 64fs.
4. Analog Outputs
The analog outputs are also single-ended and centered around the VCOM voltage. The input signal range scales with the
supply voltage and nominally 0.583 x VA Vpp (typ). The DAC input data format is 2’s compliment. The output voltage is
a positive full scale for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is VCOM
voltage for 000000H(@24bit). If the noise generated by the delta-sigma modulator beyond the audio band would be the
problem, the attenuation by external filter is required.
DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV.
MS0055-E-01
2001/02
- 13 -
ASAHI KASEI
[AK4552]
PACKAGE
16pin TSSOP (Unit: mm)
5.0
16
1.10max
9
4.4
6.4±0.2
A
1
0.22±0.1
8
0.17±0.05
0.65
0.1±0.1
Seating Plane
0.5±0.2
Detail A
0.10
0∼10°
„ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder plate
MS0055-E-01
2001/02
- 14 -
ASAHI KASEI
[AK4552]
MARKING
AKM
4552VT
XXYYY
1)
2)
3)
4)
Pin #1 indication
Date Code : XXYYY (5 digits)
XX:
lot#
YYY: Date Code
Marketing Code : 4552VT
Asahi Kasei Logo
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use or
application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor
concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support,
or other hazard related device or system, and AKM assumes no responsibility relating to any such use,
except with the express written consent of the Representative Director of AKM. As used here:
a. A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
b. A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing
it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold
AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
MS0055-E-01
2001/02
- 15 -