PAC7366 NTSC/PAL Digital Image SOC PAC7366 NTSC/PAL DIGITAL IMAGE SOC General Description The PAC7366 is a low voltage, highly integrated CMOS active-pixel digital image sensor. It provides high-quality color image and has outputs of NTSC/PAL interlaced composite analog video and parallel digital format that is embedded the new FinePixel™ sensor technology to perform the excellent image quality. It is available in CLCC-48L package. The PAC7366 can be programmed via I2CTM serial control bus or by an attached SPI or I2C flash memory at startup. By programming the internal register set, it performs the exposure time for different luminance condition, offset correction DAC, programmable gain control, and auto white balance. Features Output Format (analog composite video): z NTSC – 640x480 or 720x480 z PAL – 768x576 or 720x576 Output Format (parallel digital): z YUV/YCrCb 4:2:2 z RGB565/555/444 z BT656 Bayer-RGB color filter array On-chip 10-bit pipelined A/D converter Integrated video encoder for NTSC/PAL with overlay capability and DAC On-chip manual analog gain control I2CTM Interface Interface to EEPROM through I2CTM bus Interface to low cost Flash through SPI and I2C bus Power consumption: operating typ. 300 mW (full resolution @ 60fps) ABC (Automatic Background Compensation) Black sun cancellation DSP function: z AEC & AGC z AWB z Gamma z Color matrix z Sharpness z De-noise z Color saturation z Defect compensation z Lens shading compensation z Horizontal and vertical image flip z Zoom & windowing & sampling rate OSD (4 + 1 layers) PLL GPIO(configuration IO : pedestal, mirror, NTSC/PAL, SADDR, OSD on/off) Key Specifications Active Array Size: z 640x480 when NTSC_640x480, NTSC_720x480, PAL_720x576 z 768x576 when PAL_768x576 Optical format: z 1/3” or 1/4” Lens for NTSC_640x480, NTSC_720x480, PAL_720x576 z 1/3” Lens for PAL_768x576 Maximum Frame Rate: z NTSC: 60 fields per second z PAL: 50 fields per second Pixel Size: 5.6um * 5.6um Lens Chief Ray Angle: 0°~ 25° Scan Mode: Progressive Power Supply: z Analog: typ. 2.8V z Core: typ. 1.8V z I/O: 1.7V~3.3V input clock: typ. 27Mhz Pixel clock: 27Mhz Output interface: z Analog composite video out, single-ended or differential z 8-bit parallel digital output Sensitivity: 11500 mV/Lux-Sec S/N Ratio: 45 dB Dynamic range: 80 dB Package: CLCC-48L, 10.00mm x 10.00mm, 0.7mm pitch All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 1 V1.10 Dec. 2012 PAC7366 NTSC/PAL Digital Image SOC 1. Pin Assignment 7. SPI_SDO 42. DOUT4 8. VDDD 41. DOUT5 9. SCLK 40. DOUT6 10. SDATA 39. DOUT7 11. SPI_CS_N 38. DOUT_LSB1 12. RESET_N 37. DOUT_LSB0 36. VDDIO 13. VDDIO 35. VSSD 14. VSSD 34. PIXCLK 15. VDDD 33. FRAME_VALID 16. SADDR 32. LINE_VALID 17. GND_DAC 31. CONFIG_0 18. DAC_REF PAC7366 ~TOP VIEW~ Fig.1.1 Package Pin Assignment Pin No. 1 Name VDDD 2 CONFIG_2 Type Power Input 3 CONFIG_3 Input 4 FLASH_IF_SEL 5 SPI_SCLK 6 7 8 9 10 11 12 SPI_SDI SPI_SDO VDDD SCLK SDATA SPI_CS_N RESET_N Description Core voltage 1.8V Mode selection Mode selection 0: SPI Flash Input 1: I2C EEPROM Internal pull-down Output clock for interfacing an external SPI/I2C memory Output such as FLASH/EEPROM Input/PU Data in from SPI device. Internal pull-up. Output Data out to SPI device; SDA to I2C EEPROM Power Core voltage 1.8V, Input I2C clock Input/Output/OD I2C data, open drain type Output Chip select to SPI device. Input/PU Reset signal, active low, internal pull high. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 2 V1.10 Dec. 2012 PAC7366 NTSC/PAL Digital Image SOC 13 14 15 VDDIO VSSD VDDD Power GND Power 16 SADDR Input 17 GND_DAC GND 18 DAC_REF Output 19 DAC_POS Output 20 DAC_NEG Output 21 22 23 VDD_DAC VSS_PLL VDD_PLL Power GND Power 24 XTAL Output 25 CLKIN Input 26 27 28 29 30 31 VDDREF VDDAY_ DVDD28 AGND CONFIG_1 CONFIG_0 Power Power Power GND Input Input 32 LINE_VALID Input/Output 33 FRAME_VALID Input/Output 34 35 36 PIXCLK VSSD VDDIO Output GND Power 37 DOUT_LSB0 Input/Output 38 DOUT_LSB1 Input/Output 39 40 41 42 43 44 45 46 47 48 DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 VDDIO VSSD Output Output Output Output Output Output Output Output Power GND IO voltage , 2.8V Digital ground Core voltage 1.8V I2C device ID selection: 0 : 0x90 1: 0xBA Internal pull-down Video DAC ground External reference resistor for the video DAC. The DAC reference resistor should be 3.6 kOhm 1% for a 75 ohm video output load Positive video DAC output in differential mode, Video DAC output in single-ended mode. Negative video DAC output in differential mode, Connected a resistor to GND equal to the load resistor on DAC_POS Supply for Video DAC , 2.8V PLL ground Supply for PLL , 2.8V If XTAL is used, XTAL is served as XTAL_OUT, otherwise it is NC Master clock input (27MHz) square or served as XTAL_IN Regulator output (2.5V) for ADC VRT/VRB/VCM driver 2.5V regulator output Analog power : 2.8V Analog Ground Mode selection Mode selection CVBS mode – shall pull-up or pull-down externally Parallel output mode - Hsync CVBS mode – shall pull-up or pull-down externally Parallel output mode - Vsync pixel clock output Digital ground IO voltage , 2.8V CVBS mode – shall pull-up or pull-down externally Parallel output mode - 10bit data mode, these two extra bit make the {DOUT[7:0],DOUT_LSB1,DOUT_LSB0} as a 10 bit data for each pixel pixel data output pixel data output pixel data output pixel data output pixel data output pixel data output pixel data output pixel data output IO voltage , 2.8V Digital ground All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 3 V1.10 Dec. 2012 PAC7366 NTSC/PAL Digital Image SOC 2. Specifications Absolute Maximum Ratings -40℃ ~ 105℃ Operating Temperature -40℃ ~ 125℃ Ambient Storage Temperature VDDA 4.5V Supply Voltage ( with respect to ground ) VDDD 3.0V VDDIO 4.5V All Input / Output Voltage ( with respect to ground ) -0.3V to VDDIO + 0.5V 245℃ Lead-free temperature, Surface-mount process ESD rating, Human Body model 2000V DC Electrical Characteristics ( Ta = 0℃ ~ 70℃ ) Symbol Parameter Min. Typ. Max. Unit Type : POWER VDDA DC supply voltage – Analog 2.66 2.8 2.94 V VDDD DC supply voltage – Digital core 1.71 1.8 1.89 V VDDIO DC supply voltage – I/O 1.7 2.8 3.3 V IDDA Operating Current – Analog 71 mA IDDD Operating Current – Digital 55 mA Type : IN & I/O VDDIO VIH Input Voltage HIGH V * 0.7 VDDIO VIL Input Voltage LOW V * 0.3 Type : OUT & I/O VDDIO VOH Output Voltage HIGH V * 0.9 VDDIO V VOL Output Voltage LOW * 0.1 AC Operating Condition Symbol Parameter Min. Typ. Max. Unit fsysclk System clock frequency 27 MHz tsysclk_dc System clock duty cycle 45 55 % Sensor Characteristics Parameter Typ. Unit Sensitivity 11500 mV/Lux-Sec Signal to Noise Ratio 45 dB Dynamic Range 80 dB All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 4 V1.10 Dec. 2012 PAC7366 NTSC/PAL Digital Image SOC 3. I2CTM Bus PAC7366 supports I2C bus transfer protocol and acts as slave device. The 7-bits unique slave address is “1001000” or “1011101” and supports receiving / transmitting speed as maximum 400 kHz. I2C Bus Overview z Only two wires SDA ( serial data ) and SCL ( serial clock ) carry information between the devices connected to the I2C bus. Normally both SDA and SCL lines are open collector structure and pulled high by external pull-up resistors. z Only the master can initiates a transfer ( start ), generates clock signals, and terminates a transfer ( stop ). z Start and stop condition : A high to low transition of the SDA line while SCL is high defines a start condition. A low to high transition of the SDA line while SCL is high defines a stop condition. Please refer to Figure 3.1. z Valid data : The data on the SDA line must be stable during the high period of the SCL clock. Within each byte, MSB is always transferred first. Read / Write control bit is the LSB of the first byte. Please refer to Figure 3.2. z Both the master and slave can transmit and receive data from the bus. z Acknowledge : The receiving device should pull down the SDA line during high period of the SCL clock line when a complete byte was transferred by transmitter. In the case of a master received data from a slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master read cycle. Fig.3.1 Start and Stop conditions Fig.3.2 Valid Data All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 5 V1.10 Dec. 2012 PAC7366 NTSC/PAL Digital Image SOC Data Transfer Format Master transmits data to salve ( write cycle ) z S : Start. z A : Acknowledge by salve. z P : Stop. z RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW = 1 – Read cycle, RW = 0 – Write cycle. z SUBADDRESS : The address values of PAC7366 internal control registers. ( Please refer to PAC7366 register description ) Fig.3.3 Master-transmitter transmits to slave-receiver During write cycle, the master generates start condition and then places the 1st byte data that are combined slave address ( 7 bits ) with a read / write control bit to SDA line. After slave ( PAC7366 ) issues acknowledgment, the master places 2nd and 3rd byte ( Sub Address ) data on SDA line. Again follow the PAC7366 acknowledgment, the master places the 16 bits data on SDA line and transmit to PAC7366 control register ( address was assigned by 2nd and 3rd byte ). After PAC7366 issues acknowledgment, the master can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the PAC7366 sub-address is automatically increment after each DATA byte transferred. The data and A cycles is repeat until last byte write. Every control registers value inside PAC7366 can be programming via this way. Slave transmits data to master ( read cycle ) z The sub-address was taken from previous write cycle. z The sub-address is automatically increment after each byte read. z Am : Acknowledge by master. z Note there is no acknowledgment from master after last byte read. Fig.3.4 Slave-transmitter transmits to master-receiver During read cycle, the master generates start condition and then place the 1st byte data that are combined slave address ( 7 bits ) with a read / write control bit to SDA line. After issue acknowledgment, 16 bits DATA was also placed on SDA line by PAC7366. The 16 bits data was read from PAC7366 internal control register that address was assigned by previous write cycle. Follow the master acknowledgment, the PAC7366 place the next 16 bits data ( address is increment automatically ) on SDA line and then transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read, Am is no longer generated by master but instead by keep SDA line high. The slave ( PAC7366 ) must releases SDA line to master to generate STOP condition. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 6 V1.10 Dec. 2012 PAC7366 NTSC/PAL Digital Image SOC I2CTM Bus Timing Fig.3.5 Definition of timing for F/S-mode devices on the I2C-bus. I2CTM Bus Timing Specification Parameter Symbol Standard Mode Unit Min. Max fscl 10 400 KHz tHD:STA 4.0 - μs tLOW 4.7 - μs High period of the SCL clock. tHIGH 0.75 - μs Set-up time for a repeated START condition. tSU;STA 4.7 - μs Data hold time. For I2C-bus device. tHD;DAT 0 3.45 μs Data set-up time. tSU;DAT 250 - ns Rise time of both SDA and SCL signals. tr 30 N.D. ns ( notel ) Fall time of both SDA and SCL signals. tf 30 N.D. ns ( notel ) tSU;STO 4.0 - μs Bus free time between a STOP and START. tBUF 4.7 - μs Capacitive load for each bus line. Cb 1 15 pF Noise margin at LOW level for each connected device. ( Including hysteresis ) VnL 0.1 VDD - V Noise margin at HIGH level for each connected device. ( including hysteresis ) VnH 0.2 VDD - V SCL clock frequency. Hold time ( repeated ) Start condition. After this period, the first clock pulse is generated. Low period of the SCL clock. Set-up time for STOP condition. Note: It depends on the “high” period time of SCL. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 7 V1.10 Dec. 2012 PAC7366 NTSC/PAL Digital Image SOC 4. Register Table Address Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Hex Dec 0x00 0x01 0x02 0x03 0x0f 0x11 0x19 0x1a 0x1b 0x1c 0x1f 0x20 0x23 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0 1 2 3 15 17 25 26 27 28 31 32 35 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Bits Register Name Default Value [7:0] [7:0] [3:0] [3:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [4] [7:0] [7:0] [0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] PartID[15:8] PartID[7:0] VersionID[3:0] SubID[3:0] R_AWB_Window_X[7:0] R_AWB_Window_Y[7:0] R_AWB_DGnR_LB_by2[7:0] R_AWB_DGnR_UB_by2[7:0] R_AWB_DGnB_LB_by2[7:0] R_AWB_DGnB_UB_by2[7:0] R_DeNoiseEn R_DeNoise_Str__G[7:0] R_DeNoise_Str__RB[7:0] R_ISP_Gamma_EnH R_ISP_Y00 R_ISP_Y01 R_ISP_Y02 R_ISP_Y03 R_ISP_Y04 R_ISP_Y05 R_ISP_Y06 R_ISP_Y07 R_ISP_Y08 R_ISP_Y09 R_ISP_Y10 R_ISP_Y11 R_ISP_Y12 R_ISP_Y13 R_ISP_Y14 0x73 0x66 0x00 0x0a 0x90 0x64 0x30 0x49 0x3a 0x78 0x10 0x03 0x04 0x01 0x0d 0x19 0x2f 0x53 0x62 0x6f 0x7c 0x87 0x9a 0xaa 0xb8 0xc5 0xd8 0xe8 0xf5 Part ID Part ID VersionID SubID AWB window width (by4) AWB window height (by4) AWB digital gain lower bound for R AWB digital gain upper bound for B AWB digital gain lower bound for B AWB digital gain upper bound for R DeNoise Enable Denoise Strength (for color G) Denoise Strength (for color R/B) ISP gamma correction enable ISP Gamma Y0 ISP Gamma Y1 ISP Gamma Y2 ISP Gamma Y3 ISP Gamma Y4 ISP Gamma Y5 ISP Gamma Y6 ISP Gamma Y7 ISP Gamma Y8 ISP Gamma Y9 ISP Gamma Y10 ISP Gamma Y11 ISP Gamma Y12 ISP Gamma Y13 ISP Gamma Y14 Notes 0 0x47 71 [1:0] R_AWB_Speed 0x34 AWB adjust speed. The more, the slower 0: 1 x 1: 1/2 x 2: 1/4 x 3: 1/8 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x49 0x4a 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x63 0x66 0x6d 0x6f 0x72 0x79 0x7b 0x80 0x80 0x64 0x87 0x00 0x75 0x96 0xff 0x1e 0xff 0x20 0x00 0x3f 0x82 0x00 0x19 0x04 AWB B sum ratio = 128/X AWB R sum ratio = 128/X AWB region test Cb Low threshold -128 ~ +127 (2's complement) AWB region test Cr Low threshold -128 ~ +127 (2's complement) AWB region test Cb+Cr Low threshold -128 ~ +127 (2's complement) AWB region test Cb High threshold -128 ~ +127 (2's complement) AWB region test Cr High threshold -128 ~ +127 (2's complement) AWB region test Cb+Cr High threshold -128 ~ +127 (2's complement) Low bound of “light-pixel”Y in AWB High bound of “light-pixel”Y in AWB ISP enable AE enable AG_stage upper bound at max AE_stage 0~255, Target luminance of AE Auto-white balance enable ISP Hsize Offset ISP Vsize Offset 73 74 77 78 79 80 81 82 83 84 99 102 109 111 114 121 123 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [5] [4] [7:0] [7:0] [0] [7:0] [7:0] R_AWB_SumRatio_B R_AWB_SumRatio_R R_AWB_CbThdL[7:0] R_AWB_CrThdL[7:0] R_AWB_CbCrThdL[7:0] R_AWB_CbThdH[7:0] R_AWB_CrThdH[7:0] R_AWB_CbCrThdH[7:0] R_Ylow R_Yhigh R_ISP_EnH R_AE_EnH R_AG_stage_UB R_Ytar8bit R_AWB_EnH R_ISP_HOffset[7:0] R_ISP_VOffset[7:0] 0 0x81 129 [5:4] R_AE_Speed 0x00 AE speed, the more, the slower 0: 1 x 1: 1/2 x 2: 1/4 x 3: 1/8 x 0 0 0 0x8f 143 [7:0] R_ImgEffect_c0 0x90 144 [7:0] R_ImgEffect_c1 0x91 145 [7:0] R_ImgEffect_c2 0x00 0x00 0x00 Image Effect parameter 0 Image Effect parameter 1 Image Effect parameter 2 (ISP_UpdateFlag=1, update ) (ISP_UpdateFlag=1, update ) (ISP_UpdateFlag=1, update ) All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 8 V1.10 Dec. 2012 PAC7366 NTSC/PAL Digital Image SOC 0 0x93 147 [3:0] R_ImgEffectMode 0x00 0 0 0 0 0x94 0x97 0x98 0x98 0x00 0x01 0x00 0x00 0 0x99 153 [6:0] R_OffsetX_R[6:0] 0x00 0 0x9a 154 [6:0] R_OffsetY_R[6:0] 0x00 0 0x9b 155 [6:0] R_OffsetX_G[6:0] 0x00 0 0x9c 156 [6:0] R_OffsetY_G[6:0] 0x00 0 0x9d 157 [6:0] R_OffsetX_B[6:0] 0x00 0 0x9e 158 [6:0] R_OffsetY_B[6:0] 0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xe0 0xe1 0xe2 0xe3 0xed 0x00 0x00 0x00 0x50 0x50 0x50 0x04 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x02 0xe0 0x01 0x01 0 0xef 239 [2:0] R_RegBankSel 0x00 1 1 1 1 1 1 2 2 2 2 2 0x01 0x08 0x09 0x0A 0x22 0x25 0x08 0x09 0x0a 0x0b 0x2a 0x00 0x00 0x0 0x0 0x0 0x0 0x00 0x00 0x00 0x00 0x01 2 0x2f 47 [4:0] R_AE_stage_LL[4:0] 0x13 2 0x30 48 [4:0] R_AE_stage_NL[4:0] 0x11 2 0x32 50 [7:0] R_AG_stage_LL[7:0] 0x10 2 0x33 51 [7:0] R_AG_stage_NL[7:0] 0x00 148 151 152 152 159 160 161 162 163 164 165 166 167 168 204 205 206 207 208 209 224 225 226 227 237 1 8 9 10 34 37 8 9 10 11 42 [0] [4] [4] [5] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [2:0] [1:0] [1:0] [1:0] [7:0] [0] [7:0] [0] [7:0] [0] [7:0] [1:0] [7:0] [1:0] [0] [0] [4:0] [1:0] [1:0] [0] [0] [7:0] [7:0] [7:0] [0] [7] R_ISP_ImgEffect_En R_Shading_EnH R_VFLIP R_HFLIP R_LSC_R1[5:0] R_LSC_G1[5:0] R_LSC_B1[5:0] R_LSC_R2[5:0] R_LSC_G2[5:0] R_LSC_B2[5:0] R_LSFT_1[2:0] R_LSFT_2[1:0] R_LSFT_3[1:0] R_LSFT_4[1:0] DGn_R_vs[7:0] DGn_R_vs[8] DGn_G_vs[7:0] DGn_G_vs[8] DGn_B_vs[7:0] DGn_B_vs[8] R_ISP_HSize[7:0] R_ISP_HSize[9:8] R_ISP_VSize[7:0] R_ISP_Vsize[9:8] ISP_Update Cmd_Frame_Update_Flag Cmd_Global Cmd_fgh Cmd_ggh Cmd_HFlip Cmd_VFlip R_ImgEffect_Y_offset R_ImgEffect_U_offset R_ImgEffect_V_offset R_ISP_ImgEffect_1_En R_ISP_Edge_En0 Image Effect mode 0: monochrome 1: negative 2: x-ray 3: Sepia/Cold/Warm/Sunset 6: Solarize 10: Pixelate (ISP_UpdateFlag=1, update ) (ISP_UpdateFlag=1, update ) Lens shading enable Vertical flip Horizontal flip Horizontal distances between shading center and sensor array center of R-channel, MSB:sign bit, -63~+63 Vertical distances between shading center and sensor array center of R-channel, MSB:sign bit, -63~+63 Horizontal distances between shading center and sensor array center of G-channel, MSB:sign bit, -63~+63 Vertical distances between shading center and sensor array center of G-channel, MSB:sign bit, -63~+63 Horizontal distances between shading center and sensor array center of B-channel, MSB:sign bit, -63~+63 Vertical distances between shading center and sensor array center of B-channel, MSB:sign bit, -63~+63 Quartic parameter of R-channel Quartic parameter of G-channel Quartic parameter of B-channel Square parameter of R-channel Square parameter of G-channel Square parameter of B-channel Shift parameter of lens shading Shift parameter of lens shading Shift parameter of lens shading Shift parameter of lens shading R Digital Gain sync by vsync R Digital Gain sync by vsync G Digital Gain sync by vsync G Digital Gain sync by vsync B Digital Gain sync by vsync B Digital Gain sync by vsync ISP output Horizontal size(before skip function) ISP output Horizontal size(before skip function) ISP output Vertical size(before skip function) ISP output Vertical size(before skip function) ISP_UpdateFlag Register Bank Select 0: ISP1 Register Bank (default) 1: Sensor Register Bank 2: ISP2 Register Bank Frame Update Flag Global gain control signal Front gain control signal ; fgh=0/2/3 Coase tuning global gain control signal ; ggh=0/2/3 Horizontal Flip Vertical Flip Y offset in Imgage Effect Mode U offset in Imgage Effect Mode V offset in Imgage Effect Mode Enable Y/U/V offset in Imgage Effect Mode ISP edge enhancement enable (AE_stage >= R_AE_stage_LL) && (AG_stage >= R_AG_stage_LL) =>Low Light (AE_stage <= R_AE_stage_NL) && (AG_stage <= R_AG_stage_NL) =>Normal Light (AE_stage >= R_AE_stage_LL) && (AG_stage >= R_AG_stage_LL) =>Low Light (AE_stage <= R_AE_stage_NL) && (AG_stage <= R_AG_stage_NL) =>Normal Light All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 9 V1.10 Dec. 2012 PAC7366 86 87 88 90 91 92 94 95 96 98 NTSC/PAL Digital Image SOC 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0x56 0x57 0x58 0x5a 0x5b 0x5c 0x5e 0x5f 0x60 0x62 2 0xc0 192 [5:4] R_Format_Sel 0x00 2 2 2 3 3 3 3 3 3 3 3 3 3 3 0xc1 0xc1 0xc1 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 193 193 193 2 3 4 5 6 7 8 9 10 11 12 0x01 0x01 0x00 0x00 0x33 0x2c 0x2c 0x28 0x0b 0x39 0x44 0x40 0x34 0x0c 5 0x00 0 0x63 99 0x64 0x69 0x6a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 100 105 106 155 156 157 158 159 160 161 162 0xbf 191 0xc0 192 [4:0] [4:0] [4:0] [4:0] [7:0] [7:0] [4:0] [4:0] [4:0] [4:0] [3:0] [7:4] [0] [7:0] [7:0] [1:0] [7:0] [1:0] [7:0] [1:0] [7:0] [1:0] [7:0] [1] [2] [3:0] [0] [1] [2] [0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] R_EdgeRatio_Delta[4:0] R_EdgeRatio_LL[4:0] R_EdgeRatio_NL[4:0] R_Edge_th_Delta[4:0] R_Edge_th_LL[7:0] R_Edge_th_NL[7:0] R_Saturation_Delta[4:0] R_Saturation_LL[4:0] R_Saturation_NL[4:0] R_Shading_CP_R_Delta[4:0] R_Shading_CP_R_NL[3:0] R_Shading_CP_R_LL[3:0] R_Contrast_En R_Brightness_LL[7:0] R_Brightness_NL[7:0] R_ISP_WOI_HSize[9:8] R_ISP_WOI_HSize[7:0] R_ISP_WOI_VSize[9:8] R_ISP_WOI_VSize[7:0] R_ISP_WOI_HOffset[9:8] R_ISP_WOI_HOffset[7:0] R_ISP_WOI_VOffset[9:8] R_ISP_WOI_VOffset[7:0] R_UV_Swap R_YC_Swap R_RGB565_mode[3:0] R_Vsync_INV R_Hsync_INV R_Pxclk_INV R_CCMASign[8] R_CCMASign[7:0] R_CCMA0_0[7:0] R_CCMA0_1[7:0] R_CCMA0_2[7:0] R_CCMA1_0[7:0] R_CCMA1_1[7:0] R_CCMA1_2[7:0] R_CCMA2_0[7:0] R_CCMA2_1[7:0] R_CCMA2_2[7:0] [0] r_TXF_En 0x08 0x04 0x0a 0x08 0x0a 0x08 0x01 0x0b 0x16 0x02 0x0f 0x00 0x01 0x00 0x00 0x02 0x80 0x01 0xe0 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x0 6 0x00 0 [2:0] reg_tv_mode 0x0 6 7 7 7 7 7 7 7 7 7 7 7 7 7 7 0x01 0x00 1 0 0x0 0x1 0x1 0x1 0x1 0x1 0x1 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x12 18 0x97 0x98 0x99 0x9a 0x9b 0x9c 0xc1 0xc2 151 152 153 154 155 156 193 194 [0] [0] [0] [1] [2] [3] [4] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] reg_tv_e r_og_enable r_layer_show_1 r_layer_show_2 r_layer_show_3 r_layer_show_4 r_layer_show_5 r_Y_num_char[7:0] r_Cb_num_char[7:0] r_Cr_num_char[7:0] r_Y_num_back[7:0] r_Cb_num_back[7:0] r_Cr_num_back[7:0] r_number_char_2_1[7:0] r_number_char_4_37:0] Increment when AE/AG state change Edge ratio @Low Light Edge ratio @Normal Light Increment when AE/AG state change Edge threshold @ Low Light Edge threshold @ Normal Light Increment when AE/AG state change Color Saturation @ Low Light Color Saturation @ Normal Light Increment when AE/AG state change Shading compensation percentage @Normal Light Shading compensation percentage @Low Light Contrast Enable Brightness @ Low Light Brightness @ Normal Light (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) (ISP2_UpdateFlag=1, update ) U V Swap Y C Swap RGB565_mode Output Data format select 0:YUV 1:RGB565 2:RGB555 3:RGB444 (ISP2_UpdateFlag=1, update ) Vsync inverse Hsync inverse Pxclk inverse ACCM Base matrix coefficient ACCM Base matrix coefficient ACCM Base matrix coefficient ACCM Base matrix coefficient ACCM Base matrix coefficient ACCM Base matrix coefficient ACCM Base matrix coefficient ACCM Base matrix coefficient ACCM Base matrix coefficient ACCM Base matrix coefficient ACCM Base matrix coefficient 0: ccir656 output from ISP 1: ccir656 output from TXF NTSC_M=0; (pedestal on) NTSC_J=1; (pedestal off) PAL_M=2; PAL_N=4; (pedestal on) PAL_NC=5; PAL_BDGHI=6; (pedestal off) 1: TV Encoder Enable enable signal of overlay generator enable signal of layer 1 enable signal of layer 2 enable signal of layer 3 enable signal of layer 4 enable signal of layer 5 (number layer) Y value of word color in number layer Cb value of word color in number layer Cr value of word color in number layer Y value of background color in number layer Cb value of background color in number layer Cr value of background color in number layer [3:0] : 1st number character, [7:4] : 2nd number character [3:0] : 3rd number character, [7:4] : 4th number character All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 10 V1.10 Dec. 2012 PAC7366 195 196 197 198 199 200 201 202 203 204 NTSC/PAL Digital Image SOC 7 7 7 7 7 7 7 7 7 7 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc r_number_char_6_5[7:0] r_number_char_8_7[7:0] r_number_char_10_9[7:0] r_number_char_12_11[7:0] r_number_char_14_13[7:0] r_number_char_16_15[7:0] r_number_char_18_17[7:0] r_number_char_20_19[7:0] r_number_char_22_21[7:0] r_number_amount[4:0] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 7 0xcd 205 [1:0] r_transparency_h_num[1:0] 0x00 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xe0 0xe1 0xe2 0xe3 0xe4 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 206 207 208 209 210 211 212 213 214 215 224 225 226 227 228 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [4:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] r_transparency_num_word[7:0] r_transparency_num_back[7:0] r_target_image_num_1[7:0] r_target_image_num_1[15:8] r_target_image_num_2[7:0] r_target_image_num_2[15:8] r_target_image_num_3[7:0] r_target_image_num_3[15:8] r_target_image_num_4[7:0] r_target_image_num_4[15:8] r_flicker_period_1[7:0] r_flicker_period_2[7:0] r_flicker_period_3[7:0] r_flicker_period_4[7:0] r_flicker_period_5[7:0] [3:0] : 5th number character, [7:4] : 6th number character [3:0] : 7th number character, [7:4] : 8th number character [3:0] : 9th number character, [7:4] : 10th number character [3:0] : 11th number character, [7:4] : 12th number character [3:0] : 13th number character, [7:4] : 14th number character [3:0] : 15th number character, [7:4] : 16th number character [3:0] : 17th number character, [7:4] : 18th number character [3:0] : 19th number character, [7:4] : 20th number character [3:0] : 21th number character, [7:4] : 22th number character number amount in number layer [0] : bit 8 of transparency of number character, [1] : bit 8 of transparency of number background bit 0~7 of transparency of number character bit 0~7 of transparency of number background index of layer 1 overlay image index of layer 1 overlay image index of layer 2 overlay image index of layer 2 overlay image index of layer 3 overlay image index of layer 3 overlay image index of layer 4 overlay image index of layer 4 overlay image flicker time period of layer 1 flicker time period of layer 2 flicker time period of layer 3 flicker time period of layer 4 flicker time period of layer 5 All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 11 V1.10 Dec. 2012 PAC7366 NTSC/PAL Digital Image SOC 5. Reference Circuit Schematic Fig.5.1 Reference Schematic All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 12 V1.10 Dec. 2012 PAC7366 NTSC/PAL Digital Image SOC 6. Internal Block Diagram uC Flash 2 I2C Interface 4 SPI Interface PAC7366 I2C Slave Reg. Top Bank Ctrl I2C to SPI SPI Master Image Sensor Processor Sensor On Screen Display TV Encoder DAC Fig.6.1 Block Diagram 7. Digital Function z Mirror and Flip PAC7366 provides mirror and flip modes. Mirror mode reverses the sensor data read-out order horizontally, and flip mode provides reverses it vertically. Address Hex Dec Bits 1 0x22 34 [0] Cmd_HFlip 0x0 1 0x25 37 [0] Cmd_VFlip 0x0 Bank Original Image Register Name Default Value Mirrored Image Notes Horizontal Flip, 0 : mirror off 1 : mirror on Vertical Flip, 0 : flip off 1 : flip on Flipped Image Mirrored and Flipped Image Fig.7.1 Mirror and Flip Samples z Test Patterns generated from Image Sensor Processor, by programming a register PAC7366 provides fixed test patterns generated by image sensor processor for test purposes. Test patterns are accessible by programming a register. Bank 0 Address Hex Dec 0x0C 12 Bits [4:0] Register Name R_ISP_TestMod Default Value 0x00 Notes ISP test mode data generation Bit[4] : defect test pixel insertion Bit[3:0] : 0:no test; 1:white; 2:black; 3:red; 4:green; 5:blue; 6:vertical&horizontal color bar 7:random data 8:vertical gray bar 9:horizontal gray bar 12-15: motion test All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 13 V1.10 Dec. 2012 PAC7366 NTSC/PAL Digital Image SOC Vertical&horizontal color bar Random data Vertical gray bar Horizontal gray bar Fig.7.2 Test Patterns from Image Sensor z Test Patterns generated from TV encoder, by programming a register PAC7366 provides color bar test pattern generated by TV encoder for TV signal test purposes. Test patterns are accessible by programming a register. Color bars of NTSC and PAL are built-in to support hue and color saturation characterization and each consists of seven color bars (white, yellow, cyan, green, magenta, red, and blue) Bank 6 Address Hex Dec 0x11 17 Bits [2] Register Name reg_ccir656_src Default Value 0 Notes 0: CCIR656_SRC_Sensor 1: CCIR656_SRC_ColorBar NTSC 100% color bar PAL 100% color bar Fig.7.3 Test Patterns from TV Encoder All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 14 V1.10 Dec. 2012 PAC7366 NTSC/PAL Digital Image SOC 8. Sensor Pixel Array Structure The active pixel array is 640 x 480 pixels for NTSC_TV, 768 x 576 pixels for PAL_TV. The active border is for color interpolation, defect, denoise and edge enhancement. Fig.8.1 Sensor Pixel Array 9. Auto Exposure Control and Auto Gain Control z Auto Exposure Control Exposure time is manually set by registers when auto exposure control is off, instead it is controlled by auto exposure time algorithm when auto exposure control is on. Bank 0 Address Hex Dec 0x66 z 102 Bits [4] Register Name Default Value R_AE_EnH 1 Notes 0: Auto Exposure Control off 1: Auto Exposure Control on Auto Gain Stage Upper Bound Maximum gain is limited to upper bound. Bank 0 Address Hex Dec 0x6D 109 Bits Register Name [7:0] R_AG_stage_UB Default Value 0x96 Notes 48 : x16 64 : x32 80 : x64 96 : x128 Note : When AE is on. z Global gain control, Front gain control, Coase tuning global gain control Analog gain x1~x32. Address Hex Dec Bits Register Name Default Value 1 0x08 08 [4:0] Cmd_Global 0x00 1 0x09 09 [1:0] Cmd_fgh 0x00 1 0x0A 10 [1:0] Cmd_ggh 0x00 Bank Notes 1 + (Cmd_Global[4:0]/16) 0 : x1 2 : x2 3 : x4 0 : x1 2 : x2 3 : x4 Note : When AE is off All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 15 V1.10 Dec. 2012 PAC7366 NTSC/PAL Digital Image SOC 10. Digital Gain Digital gain x1, x2, x8. Bank 0 Address Hex Dec 0xdf 223 Bits Register Name [1:0] R_DG_manual_gain Default Value 0x00 Notes 0 : x1 1 : x2 2 : x8 11. NTSC / PAL Signal Parameters z NTSC : H_Timing Test Item H_Timing Line Frequency z Description Sync Rise Time Sync Fall Time Sync Width Sync Level Burst Level Sync to Burst Start Burst Width Front Porch Sync to SetUp Line Frequency Field Frequency Pattern 75% Color Bars Unit n sec n sec u sec IRE IRE u sec cycles u sec u sec kHz Hz L-Limit 100.00 100.00 4.50 37.90 35.00 5.20 8.50 0.50 8.00 15.734 59.94 H-Limit 300.00 300.00 4.90 42.00 43.40 5.40 9.50 2.50 11.00 15.734 59.94 Nominal 200.00 200.00 4.70 39.95 39.20 5.30 9.00 1.50 9.50 15.734 59.94 Measurement 133.0 131.0 4.7 40.9 38.0 5.4 9.0 1.5 9.2 15.734 59.94 Unit n sec n sec u sec mV mV u sec u sec kHz Hz L-Limit 100.00 100.00 4.50 288.00 250.00 5.50 2.00 15.625 50.00 H-Limit 300.00 300.00 4.90 315.00 310.00 5.70 2.50 15.625 50.00 Nominal 200.00 200.00 4.70 301.50 280.00 5.60 2.25 15.625 50.00 Measurement 139.00 138.00 4.64 303.40 278.20 5.59 2.32 15.625 50.00 PAL : H_Timing Test Item H_Timing Pattern 75% Color Bars Sync Level Burst Level Line Frequency Description Sync Rise Time Sync Fall Time Sync Width Sync Level Burst Level Sync to Burst Start Burst Width Line Frequency Field Frequency Fig.11.1 H-Timing All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 16 V1.10 Dec. 2012 NTSC/PAL Digital Image SOC Chroma Level WHITE Chroma Phase 75% Color Bars Unit IRE IRE IRE IRE IRE IRE IRE IRE IRE IRE IRE IRE IRE IRE IRE IRE Deg Deg Deg Deg Deg Deg L-Limit 69.2 62.1 50.5 43.4 32.6 25.4 13.9 6.8 0.0 55.9 78.9 73.7 73.7 78.9 55.9 0.0 162.1 278.5 235.7 55.7 98.5 342.1 H-Limit 84.6 75.9 61.7 53.0 39.8 31.0 16.9 8.3 1.4 68.3 96.5 90.1 90.1 96.5 68.3 1.4 172.1 288.5 245.7 65.7 108.5 352.1 Nominal 76.9 69.0 56.1 48.2 36.2 28.2 15.4 7.5 0.0 62.1 87.7 81.9 81.9 87.7 62.1 0.0 167.1 283.5 240.7 60.7 103.5 347.1 Measurement 77.9 70.2 56.9 48.8 36.8 28.6 15.8 7.6 0.1 58.4 82.7 77.1 77.1 82.8 58.6 0.1 165.0 282.0 240.1 59.2 103.1 346.0 BLACK Composite Color Bar_1 YELLOW Luma Level Pattern Gray Yellow Cyan Green Magenta Red Blue Black Gray Yellow Cyan Green Magenta Red Blue Black Yellow Cyan Green Magenta Red Blue RED Description MAGENTA Test Item GREEN NTSC : Composite Color Bar CYAN z BLUE PAC7366 Fig.11.2 NTSC mode Color Bar All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 17 V1.10 Dec. 2012 PAC7366 z NTSC/PAL Digital Image SOC PAL : Composite Color Bar Test Item Description Luma Level Composite Color Bar_1 Chroma Level Chroma Phase Pattern Gray Yellow Cyan Green Magenta Red Blue Black Gray Yellow Cyan Green Magenta Red Blue Black Yellow Cyan Green Magenta Red Blue 75% Color Bars Unit mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV Deg Deg Deg Deg Deg Deg L-Limit 472.5 419 331 277 195 141 54 -10 0.0 423 598 558 558 598 423 0.0 162 278 235 55 98 342 H-Limit 577.5 512 405 339 234 173 66 10 10.0 517 730 682 682 730 517 10.0 172 288 245 65 108 352 Nominal 525.0 465.5 368.0 308.0 217.0 157.0 60.0 0.0 0.0 470.0 664.0 620.0 620.0 664.0 470.0 0.0 167.0 283.0 240.0 60.0 103.0 347.0 Measurement 529.8 470.5 370.1 308.2 219.2 158.3 61.4 -0.9 0.5 437.1 618.8 577.2 577.4 619.8 438.9 0.4 167.0 283.4 240.4 60.6 103.4 347.7 White Level 100 IRE 4.43 Mhz Color Burst (9~11 Cycles) 21.43 IRE Black / Blank Level 21.43 IRE 43 IRE Sync Level Fig.11.3 PAL mode Color Bar All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 18 V1.10 Dec. 2012 PAC7366 NTSC/PAL Digital Image SOC 12. Flash and On-Screen-Dispay z Flash Devices Registers can be loaded by Serial Flash or I2C interface. Fig.12.1 I2C and Flash Block Diagram Table below lists Flash devices, which can support both read and write functions. Flash Type SPI SPI z Density 1 Mbit 8 Mbit Mfg NUMONYX ATMEL Device M25P10-A AT26DF081A Speed 50 Mhz 70 Mhz Temp. Range (℃) Supply Voltage (V) -40~85 2.3~3.6 -40~85 2.7~3.6 On-Screen-Display Up to four overlays may be mixed on each layer simultaneously, and a fifth layer can exist for a number character overlay. The host can modify image’s size, position, color, transparency and flicker time by programming register setting. PAC7366 compressed Images overlay buffers: 2KB each layer layer1 decompress layer2 layer3 flash layer4 double Buffers overlay layer1 layer2 layer3 layer4 Fig.12.2 Overlay Channels All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 19 V1.10 Dec. 2012 PAC7366 NTSC/PAL Digital Image SOC 13. Package Information z Package Outline Dimension Fig.13.1 Package Mechanical Diagram Note: 1. Dimensions in mm. dimensions in () are for reference only. Do not measure printed drawing. 2. Wall material: alumina ceramic. 3. Substrate material: alumina ceramic 0.2 thinkness. 4. Lid material: borosilica glass 0.55 thickness 5. Lead finish: gold plating 0.5 microns minimum thickness. 6. Image sensor die 0.3 thickness. 7. Maximum rotation of optical area relative to package edged: 1° Maximum tilt of optical are relative to seating plane A: 50 microns Maximum tilt of optical are relative to top of cover glass:75 microns 8. Optical center = package center All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 20 V1.10 Dec. 2012 PAC7366 z NTSC/PAL Digital Image SOC Recommended PCB Layout Fig.13.2 Recommended PCB Layout Note: 1. All dimensions are millimeter 2. Top view 3. Optical center = package center All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 21 V1.10 Dec. 2012 PAC7366 z I. NTSC/PAL Digital Image SOC Recommended Guideline for PCB Assembly ecommended vender and type for Pb-free solder paste 1 Almit LFM-48W TM-HP 2 Senju M705-GRN360-K II. IR Reflow Soldering Profile Temperature profile is the most important control in reflow soldering. It must be fine tuned to establish a robust process. The typical recommended IR reflow profile is showed in figure 8 below. Fig.13.3 IR Reflow Profile z Reflow Profile 1. Average Ramp-up Rate (30°C to preheat zone): 1.5~ 2.5 Degree C/ Sec 2. Preheat zone: 2.1 Temp ramp from 170~ 200 degree C 2.2 Exposure time: 90 +/- 30 sec 3. Melting zone: 3.1 Melting area temp > 220 degree C for at least 30 ~ 50 sec 3.2 Peak temperature : 245 degree C. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 22 V1.10 Dec. 2012 PAC7366 NTSC/PAL Digital Image SOC 14. Revision History Revision V0.90 V0.92 V1.00 V1.10 Comments Preliminary version Update “Output Format”, “Active Array Size”, “Optical format” Update “Power Consumption”, “Operating Current” Add SPI or I2C selection at CONFIG_4 Update I/O Table Replace Pin#4 CONFIG_4 with FLASH_IF_SEL Update current consumption Update “Lens Chief Ray Angle” Update notes in “Register Table” Update “Recommended PCB Layout” Update “DC supply voltage – Digital core” Update “Features” Issue Date Aug. 16, 2012 Nov. 14, 2012 Dec. 4, 2012 Dec. 20, 2012 All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: [email protected] 23 V1.10 Dec. 2012