PIXART PAS6167

PAS6167 Specification
PAS6167 CMOS QCIF+ DIGITAL IMAGE SENSOR
General Description
The PAS6167 is a highly integrated CMOS active-pixel image sensor that has output of 176 x 220 pixels. It
embedded the new FinePixel™ sensor technology to perform the excellent image quality. PAS6167 outputs
YUV/YCrCb 4:2:2 or RGB 565/555/444 data through the parallel/serial data bus. It is available in CSP-20pin
package.
The PAS6167 can be programmed to set the exposure time for different luminance condition via I2CTM serial
control bus. By programming the internal register set, it performs on-chip frame rate adjustment, offset correction
DAC and programmable gain control.
Key Specification
Features
ƒ
Active Pixels: 188 x 236 pixels
ƒ
Resolution: 176 x 220 pixels, 1/13” Lens
ƒ
Bayer-RGB color filter array
ƒ
Output format (parallel/serial):
z
z
YUV/YCrCb 4:2:2 (QCIF+, and other
sizes …)
RGB 565/555/444 (QCIF+, and other
sizes …)
ƒ
On-chip 11-bit pipelined A/D converter
ƒ
On-chip 2-stage background compensation DAC
ƒ
On-chip manual analog gain control
ƒ
Continuous variable frame time & exposure time
ƒ
I2CTM Interface
ƒ
Support 1.8V~3.3V I/O power
ƒ
low power-down dissipation
ƒ
Automatic Background Compensation
ƒ
DSP function:
188(H) x 236(V)
Resolution
176 (H) x 220 (V)
Analog
2.5V ~ 2.8V
I/O
1.8V ~ 3.3V
Core
1.8V
Power
Pixel Size
z
z
z
z
z
z
z
z
z
ƒ
Active Pixel
AEC & AGC
AWB
Gamma
Color matrix
Sharpness
De-noise
Color saturation
Defect compensation
Lens shading compensation
Lens Chief Ray Angle
Max. Frame rate
Max. System clock rate
Max. SPI clock rate
4.5µm x 4.5µm, 1/13” Lens
< 22degree
30 fps, QCIF+ YUV mode
52 MHz
26 MHz, QCIF+ YUV mode
Sensitivity
3.9V/Lux-sec
Color filter
RGB Bayer Pattern
Exposure Time
~ Frame time to Line time
WOI & Sub-sampling
ƒ
PLL
ƒ
Module size : 5.0 * 5.0 * 3.0 mm
Scan Mode
Progressive
S/N Ratio
39dB
Dynamic range
60dB
Package
CSP-20pin (PAS6167LT)
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PixArt Imaging Inc.
E-mail: [email protected]
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PixArt Imaging Inc.
PAS6167
CMOS Image Sensor IC
1. Pin Assignment
Parallel mode
Pin No.
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
C1
C2
C3
C4
C5
D1
D2
D3
D4
D5
Name
PXD7
SYSCLK
PXD5
PXD4
PXCLK
VDDA
VSSA
VSSD
PXD0
PXD1
CSB
PXD6
HSYNC
PXD3
PXD2
SCL
SDA
VSYNC
VDDD
VDDMD
Type
OUT
IN
OUT
OUT
OUT
PWR
GND
GND
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
I/O
OUT
PWR
PWR
Description
Digital pixel data [7], MSB
External clock input
Digital pixel data [5]
Digital pixel data [4]
Pixel clock output
Analog power, 2.5V ~ 2.8V
Analog ground
Digital ground
Digital pixel data [0], LSB
Digital pixel data [1]
Power down enable, active high
Digital pixel data [6]
Horizontal synchronization signal output
Digital pixel data [3]
Digital pixel data [2]
I2C clock input
I2C data
Vertical synchronization signal output
Digital core power, 1.8V
I/O power, 1.8V ~ 3.3V
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PixArt Imaging Inc.
PAS6167
CMOS Image Sensor IC
Serial mode
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PAS6167
CMOS Image Sensor IC
Pin No.
A1
A2
A3
A4
Name
NC
SYSCLK
NC
NC
A5
SCK
B1
B2
B3
B4
C1
C2
VDDA
VSSA
VSSD
SDO
OVERFLOW
READY
CSB
NC
C3
SSn
C4
NC
NC
OVERFLOW
SCL
SDA
CTS
NC
VDDD
VDDMD
B5
C5
D1
D2
D3
D4
D5
Type
-IN
--OUT
IN
PWR
GND
GND
OUT
OUT
OUT
IN
-OUT
IN
--OUT
IN
I/O
IN
-PWR
PWR
Description
-External clock input
--SPI clock output (SPI master mode)
SPI clock input (SPI slave mode)
Analog power, 2.5V ~ 2.8V
Analog ground
Digital ground
SPI data output
FIFO overflow (SPI master mode)
Data ready (SPI slave mode)
Power down enable, active high
-SPI frame sync (SPI master mode)
SPI select (SPI slave mode)
--FIFO overflow (SPI slave mode)
I2C clock input
I2C data
Pause output data (SPI master mode)
-Digital core power, 1.8V
I/O power, 1.8V ~ 3.3V
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PAS6167
CMOS Image Sensor IC
2. Specifications
Absolute Maximum Ratings
Ambient Storage Temperature
-40℃~60℃
Supply Voltage ( with respect to ground )
VDDD
3.0V
VDDA
4.5V
VDDMD
4.5V
All Input / Output Voltage ( with respect to ground )
-0.3V to VDDMD+0.5V
Lead-free temperature, Surface-mount process
245℃
ESD rating, Human Body model
2000V
DC Electrical Characteristics ( Ta = 0℃ ~ 70℃ )
Symbol
Parameter
Min.
Typ.
Max.
Unit
2.8
V
1.98
V
3.3
V
Type : POWER
VDDA
DC supply voltage – Analog
2.45
VDDD
DC supply voltage – Digital core
1.62
VDDMD
DC supply voltage – I/O
1.62
a
1.8
IDD
Operating Current (see Note )
15.8
mA
IPWDN
Power Down Current (see Noteb)
10
µA
Type : IN & I/O Reset and System Clock(input clock)
VIH
Input Voltage HIGH
VIL
Input Voltage LOW
VDDMD
* 0.7
V
VDDMD
* 0.3
V
Type : OUT & I/O for PX0 : 9, SDA, H/VSYNC and PXCLK(output clock)
VOH
Output Voltage HIGH
VOL
Output Voltage LOW
VDDMD
* 0.9
V
VDDMD
* 0.1
V
Notea: VDDA=2.8V, VDDD=1.8V, VDDMD=3.3V, 30fps / QCIF+ / YUV output, without I/O loading
Noteb: VDDA=2.8V, VDDMD=2.8V
AC Operating Condition
Symbol
Parameter
fsysclk
System clock frequency
tsysclk_dc
System clock duty cycle
Min.
Typ.
Max.
13
45
MHz
55
%
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Unit
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PixArt Imaging Inc.
PAS6167
CMOS Image Sensor IC
Sensor Characteristics
Parameter
Typ.
Unit
Sensitivity
3.9
V/Lux-sec
Signal to Noise Ratio
39
dB
Dynamic Range
60
dB
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PixArt Imaging Inc.
PAS6167
CMOS Image Sensor IC
3. I2CTM Bus
PAS6167 supports I2C bus transfer protocol and acts as slave device. The 7-bits unique slave address is
“1000000” and supports receiving / transmitting speed as maximum 400KHz.
I2C Bus Overview
z
Only two wires SDA ( serial data ) and SCL ( serial clock ) carry information between the
devices connected to the I2C bus. Normally both SDA and SCL lines are open collector
structure and pulled high by external pull-up resistors.
z
Only the master can initiates a transfer ( start ), generates clock signals, and terminates a
transfer ( stop ).
z
Start and stop condition : A high to low transition of the SDA line while SCL is high defines a
start condition. A low to high transition of the SDA line while SCL is high defines a stop
condition. Please refer to Figure 2.1.
z
Valid data : The data on the SDA line must be stable during the high period of the SCL clock.
Within each byte, MSB is always transferred first. Read / Write control bit is the LSB of the
first byte. Please refer to Figure 2.2.
z
Both the master and slave can transmit and receive data from the bus.
z
Acknowledge : The receiving device should pull down the SDA line during high period of the
SCL clock line when a complete byte was transferred by transmitter. In the case of a master
received data from a slave, the master does not generate an acknowledgment on the last byte
to indicate the end of a master read cycle.
Figure 2.1 Start and Stop conditions
Figure 2.2 Valid Data
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PAS6167
CMOS Image Sensor IC
Data Transfer Format
Master transmits data to salve ( write cycle )
z
S : Start.
z
A : Acknowledge by salve.
z
P : Stop.
z
RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW = 1 –
Read cycle, RW = 0 – Write cycle.
z
SUBADDRESS : The address values of PAS6167 internal control registers. ( Please refer to
PAS6167 register description )
During write cycle, the master generates start condition and then places the 1st byte data that are
combined slave address ( 7 bits ) with a read / write control bit to SDA line. After slave ( PAS6167 )
issues acknowledgment, the master places 2nd byte ( Sub Address ) data on SDA line. Again follow the
PAS6167 acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS6167
control register ( address was assigned by 2nd byte ). After PAS6167 issues acknowledgment, the master
can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the PAS6167
sub-address is automatically increment after each DATA byte transferred. The data and A cycles is repeat
until last byte write. Every control registers value inside PAS6167 can be programming via this way.
Slave transmits data to master ( read cycle )
z
The sub-address was taken from previous write cycle.
z
The sub-address is automatically increment after each byte read.
z
Am : Acknowledge by master.
z
Note there is no acknowledgment from master after last byte read.
During read cycle, the master generates start condition and then place the 1st byte data that are combined
slave address ( 7 bits ) with a read / write control bit to SDA line. After issue acknowledgment, 8 bits
DATA was also placed on SDA line by PAS6167. The 8 bits data was read from PAS6167 internal control
register that address was assigned by previous write cycle. Follow the master acknowledgment, the
PAS6167 place the next 8 bits data ( address is increment automatically ) on SDA line and then transmit
to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read, Am is
no longer generated by master but instead by keep SDA line high. The slave ( PAS6167 ) must releases
SDA line to master to generate STOP condition.
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PixArt Imaging Inc.
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V1.0, 2009/08/12
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PAS6167
CMOS Image Sensor IC
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PAS6167
CMOS Image Sensor IC
I2CTM Bus Timing
I2CTM Bus Timing Specification
Parameter
Symbol
Standard Mode
Unit
Min.
Max
fscl
10
400
KHz
tHD:STA
4.0
-
µs
Low period of the SCL clock.
tLOW
4.7
-
µs
High period of the SCL clock.
tHIGH
0.75
-
µs
Set-up time for a repeated START condition.
tSU;STA
4.7
-
µs
Data hold time. For I2C-bus device.
tHD;DAT
0
3.45
µs
Data set-up time.
tSU;DAT
250
-
ns
Rise time of both SDA and SCL signals.
tr
30
N.D.
ns
( notel )
Fall time of both SDA and SCL signals.
tf
30
N.D.
ns
( notel )
tSU;STO
4.0
-
µs
Bus free time between a STOP and START.
tBUF
4.7
-
µs
Capacitive load for each bus line.
Cb
1
15
pF
Noise margin at LOW level for each connected device.
( Including hysteresis )
VnL
0.1
VDD
-
V
Noise margin at HIGH level for each connected device.
( including hysteresis )
VnH
0.2
VDD
-
V
SCL clock frequency.
Hold time ( repeated ) Start condition.
After this period, the first clock pulse is generated.
Set-up time for STOP condition.
Note : It depends on the “high” period time of SCL.
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PAS6167
CMOS Image Sensor IC
4. Registers
Register Table
Bank0 (set address_0xEF=0)
Address (Hex)
4 [4:0]
6 [0]
F [7:0]
11 [7:0]
13 [7:0]
[2:0]
14
[7:4]
15 [7:0]
17 [7:0]
35 [0]
56 [7:0]
58 [7:0]
59 [7:0]
5A [7:0]
5B [7:0]
5C [7:0]
5D [7:0]
5E [7:0]
5F [7:0]
60 [7:0]
61 [7:0]
Register name
AE_stage_indoor[4:0]
in_door
AWB_Window_X[7:0]
AWB_Window_Y[7:0]
lpf_min[7:0]
lpf_min[10:8]
ny_min[3:0]
AE_Window_X[7:0]
AE_Window_Y[7:0]
AC_freq
AG_stage_UB
ISP_Y0
ISP_Y1
ISP_Y2
ISP_Y3
ISP_Y4
ISP_Y5
ISP_Y6
ISP_Y7
ISP_Y8
ISP_Y9
Default
0x0b
0x00
0xa0
0xc0
0xf6
0x00
0x09
0xa0
0xc0
0x01
0x3f
0x04
0x08
0x10
0x20
0x32
0x44
0x71
0x90
0xae
0xca
[0]
ISP_Gamma_EnH
0x01
[0]
freq_60
0x01
[4]
AE_EnH
0x00
[7:0]
SysClk_freq[7:0]
0x97
[6:0]
SysClk_freq[13:8]
0x31
73
74
[7]
[4:0]
[4:0]
[7:0]
[0]
[4]
[7:0]
[7:0]
SysClk_freq_Div8
AE_minStage[4:0]
AE_maxStage[4:0]
Ytar8bit
AWB_EnH
AWB_Gain_rst
Ylow
Yhigh
0x01
0x05
0x1a
0x64
0x00
0x00
0x70
0xf0
8F
[7:0]
ImgEffect_c0
0x40
90
[7:0]
ImgEffect_c1
0x40
91
[7:0]
ImgEffect_c2
0x10
62
66
67
68
6B
6C
6F
72
Description
Min. AE stage clamp in door
AE In door enable
AWB window width
AWB window height
Lpf minimum value for AE
Lpf minimum value for AE
Ny minimum value for AE
AE window width
AE window height
AC frequency (1: 60Hz, 0: 50Hz)
AG_stage upper bound at max. AE_stage
ISP Gamma Y0, (ISP_UpdateFlag=1, update )
ISP Gamma Y1, (ISP_UpdateFlag=1, update )
ISP Gamma Y2, (ISP_UpdateFlag=1, update )
ISP Gamma Y3, (ISP_UpdateFlag=1, update )
ISP Gamma Y4, (ISP_UpdateFlag=1, update )
ISP Gamma Y5, (ISP_UpdateFlag=1, update )
ISP Gamma Y6, (ISP_UpdateFlag=1, update )
ISP Gamma Y7, (ISP_UpdateFlag=1, update )
ISP Gamma Y8, (ISP_UpdateFlag=1, update )
ISP Gamma Y9, (ISP_UpdateFlag=1, update )
ISP gamma correction enable,
(ISP_UpdateFlag=1, update )
Set de-flicker frequency
0/1: 50/60Hz
AE enable
R_SysClk_freq_Div8 = 0 : Input_frequency/2048
R_SysClk_freq_Div8 = 1 : Input_frequency/256
R_SysClk_freq_Div8 = 0 : Input_frequency/2048
R_SysClk_freq_Div8 = 1 : Input_frequency/256
R_SysClk_freq_Div8
Minimum AE stage
Maximum AE stage (AE_maxStage<=28)
0~255, Target luminance of AE
Auto-white balance enable
AWB gain gain reset
Low bond of “light-pixel” in AWB
High bond of “light-pixel” in AWB
Image Effect parameter 0,
(ISP_UpdateFlag=1, update )
Image Effect parameter 1,
(ISP_UpdateFlag=1, update )
Image Effect parameter 2,
(ISP_UpdateFlag=1, update )
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PAS6167
92
[7:0]
CMOS Image Sensor IC
ImgEffect_c3
0x80
Image Effect parameter 3,
(ISP_UpdateFlag=1, update )
Image Effect mode
1: monochrome; 2: negative
3: Sepia; 4: Emboss; 5: Sketch
6: Black Board; 7: White Board
8: Solarize; 9: Color range R
10: Color range G;
11: Color range B; 12: Contrast
(ISP_UpdateFlag=1, update )
[3:0]
ImgEffectMode
0x00
[5:4]
ImgEffectFilter
0x00
[0]
[4]
[5]
[6:0]
[6:0]
[6:0]
[6:0]
[6:0]
[6:0]
[6:0]
[6:0]
[6:0]
[6:0]
[6:0]
[6:0]
[6:0]
[6:0]
[6:0]
[6:0]
[7:0]
[1:0]
[7:0]
[1:0]
[2:0]
ISP_ImgEffect_En
Shading_EnH
Shading_On
BYcoef_D
BXcoef_R
BYcoef_U
BXcoef_L
GbYcoef_D
GbXcoef_R
GbYcoef_U
GbXcoef_L
GrYcoef_D
GrXcoef_R
GrYcoef_U
GrXcoef_L
RYcoef_D
RXcoef_R
RYcoef_U
RXcoef_L
brightestX[7:0]
brightestX[9:8]
brightestY[7:0]
brightestY[9:8]
LensShfBit[2:0]
0x00
0x00
0x00
0x1f
0x1f
0x1f
0x1f
0x1f
0x1f
0x1f
0x1f
0x1f
0x1f
0x1f
0x1f
0x1f
0x1f
0x1f
0x1f
0x40
0x01
0xf0
0x00
0x00
[6:4]
DigFilter_mode_NL[2:0]
0x00
[2:0]
DigFilter_mode_LL[2:0]
0x00
[4:0]
[4:0]
[0]
[4]
DigFilterAE_stageLL[4:0]
DigFilterAE_stageNL[4:0]
ISP_Update
ISP_FrameSkip
0x00
0x00
93
94
97
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
E2
E3
E4
ED
Image Effect emboss filter type,
(ISP_UpdateFlag=1, update )
(ISP_UpdateFlag=1, update )
Lens shading enable
Shading on/off status (read only)
Lens Shading Y coefficient of color B (down)
Lens Shading X coefficient of color B (right)
Lens Shading Y coefficient of color B (up)
Lens Shading X coefficient of color B (left)
Lens Shading Y coefficient of color Gb (down)
Lens Shading X coefficient of color Gb (right)
Lens Shading Y coefficient of color Gb (up)
Lens Shading X coefficient of color Gb (left)
Lens Shading Y coefficient of color Gr (down)
Lens Shading X coefficient of color Gr (right)
Lens Shading Y coefficient of color Gr (up)
Lens Shading X coefficient of color Gr (left)
Lens Shading Y coefficient of color R (down)
Lens Shading X coefficient of color R (right)
Lens Shading Y coefficient of color R (up)
Lens Shading X coefficient of color R (left)
Lens Shading brightest X
Lens Shading brightest X
Lens Shading brightest Y
Lens Shading brightest Y
Lens shading coefficient right shift bit
0 : DigFilter off @ NL,
1 : DigFilter level-1 @ NL,
2 : DigFilter level-2 @ NL,
0 : DigFilter off @ LL,
1 : DigFilter level-1 @ LL,
2 : DigFilter level-2 @ LL,
Digital Filter @Low Light
Digital Filter @Normal Light
ISP_UpdateFlag
(ISP_UpdateFlag=1, update )
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PAS6167
CMOS Image Sensor IC
Bank2 (set address_0xEF=2)
Address (Hex)
0 [0]
4 [7:0]
5 [7:0]
6 [7:0]
7 [7:0]
Register name
ISP2_Update
R_ImgEffect_R_Gain[7:0]
R_ImgEffect_G_Gain[7:0]
R_ImgEffect_B_Gain[7:0]
R_ImgEffect_R_offset[7:0]
Default
0x00
0x00
0x00
0x00
0x00
8
[7:0]
R_ImgEffect_G_offset[7:0]
0x00
9
[7:0]
R_ImgEffect_B_offset[7:0]
0x00
A
[0]
R_ISP_ImgEffect_1_En
0x00
R_Curve_EnH
R_Curve_Y0[7:0]
R_Curve_Y1[7:0]
R_Curve_Y2[7:0]
R_Curve_Y3[7:0]
R_Curve_Y4[7:0]
R_Curve_Y5[7:0]
R_Curve_Y6[7:0]
R_Curve_Y7[7:0]
R_Curve_Y8[7:0]
R_Curve_Y9[7:0]
R_Defect_EnH
R_Defect_NL_th[5:0]
R_Defect_LL_th[5:0]
R_FlatRatio[3:0]
R_Flat_En
R_ISP_Edge_En0
R_Edge_UB[7:0]
R_Edge_LB[7:0]
R_AE_stage_LL[4:0]
R_AE_stage_NL[4:0]
0x01
0x1a
0x34
0x49
0x5b
0x6d
0x7d
0x9a
0xb6
0xcf
0xe8
0x00
0x0a
0x05
0x08
0x00
0x01
0x32
0x14
0x1b
0x14
[4:0]
R_AE_Middle_Stage[4:0]
0x0e
[7]
[4:0]
[0]
[2:0]
[7:0]
[2:0]
[7:0]
[2:0]
[7:0]
[2:0]
[7:0]
[2:0]
[7:0]
[2:0]
R_AE_Middle_Gain_En
R_AE_Middle_Gain[4:0]
R_CCMb_En
R_CCMb0_0[10:8]
R_CCMb0_0[7:0]
R_CCMb0_1[10:8]
R_CCMb0_1[7:0]
R_CCMb0_2[10:8]
R_CCMb0_2[7:0]
R_CCMb1_0[10:8]
R_CCMb1_0[7:0]
R_CCMb1_1[10:8]
R_CCMb1_1[7:0]
R_CCMb1_2[10:8]
0x01
0x09
0x01
0x80
0xb5
0x07
0xcb
0x00
0x00
0x07
0xc8
0x00
0xea
0x07
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
28
29
[0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[3]
[5:0]
[5:0]
[3:0]
2A [6]
[7]
2C [7:0]
2D [7:0]
2F [4:0]
30 [4:0]
38
39
3D
3E
3F
40
41
42
43
44
45
46
47
48
Description
ISP2_UpdateFlag
ImageEffect R Gain (ISP2_UpdateFlag=1, update )
ImageEffect G Gain (ISP2_UpdateFlag=1, update )
ImageEffect B Gain (ISP2_UpdateFlag=1, update )
ImageEffect R Offset (ISP2_UpdateFlag=1, update )
ImageEffect G Offset (ISP2_UpdateFlag=1,
update )
ImageEffect B Offset (ISP2_UpdateFlag=1, update )
Enable ImageEffect Gain, Offset
(ISP2_UpdateFlag=1, update )
ISP tone curve Enable
ISP tone curve Y0
ISP tone curve Y1
ISP tone curve Y2
ISP tone curve Y3
ISP tone curve Y4
ISP tone curve Y5
ISP tone curve Y6
ISP tone curve Y7
ISP tone curve Y8
ISP tone curve Y9
Defect Enable
Defect test threshold @ Normal Light
Defect test threshold @ Low Light
ISP flat ratio
ISP flat enable
ISP edge enhancement enable
ISP edge enhancement value upper bound
ISP edge enhancement value lower bound
AE_stage > R_AE_stage_LL =>Low Light
AE_stage < R_AE_stage_NL =>Normal Light
Apply Middle Gain when AE_stage >=
R_AE_Middle_Stage
AE Middle Gain Enable
AE Middle Gain value
CCM Enable
CCM matrix coefficient
CCM matrix coefficient
CCM matrix coefficient
CCM matrix coefficient
CCM matrix coefficient
CCM matrix coefficient
CCM matrix coefficient
CCM matrix coefficient
CCM matrix coefficient
CCM matrix coefficient
CCM matrix coefficient
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: [email protected]
13
V1.0, 2009/08/12
PixArt Imaging Inc.
PAS6167
49
4A
4B
4C
4D
4E
4F
58
C0
C3
C4
[7:0]
[2:0]
[7:0]
[2:0]
[7:0]
[2:0]
[7:0]
[4:0]
[0]
[1]
[3:2]
[4]
[5]
[6]
[5:0]
[0]
[1]
[2]
[3]
CMOS Image Sensor IC
R_CCMb1_2[7:0]
R_CCMb2_0[10:8]
R_CCMb2_0[7:0]
R_CCMb2_1[10:8]
R_CCMb2_1[7:0]
R_CCMb2_2[10:8]
R_CCMb2_2[7:0]
R_EdgeRatio_NL[4:0]
R_UV_Swap
R_YC_Swap
R_RGB565_mode[1:0]
R_RGB565_En
R_RGB555_En
R_RGB444_En
R_SPI_SysClk_Div[5:0]
R_SPI_En
R_SPI_SSn_VsyncTim
R_SPI_Slave_En
R_SPI_CTS_En
0xcf
0x07
0xf7
0x07
0x7e
0x01
0x0b
0x05
0x00
0x01
0x00
0x00
0x00
0x00
0x01
0x00
0x00
0x00
0x00
CCM matrix coefficient
CCM matrix coefficient
CCM matrix coefficient
CCM matrix coefficient
CCM matrix coefficient
CCM matrix coefficient
CCM matrix coefficient
Edge ratio @Normal Light
U V Swap
Y C Swap
RGB565_mode
RGB565 Enable (ISP2_UpdateFlag=1, update )
RGB555 Enable (ISP2_UpdateFlag=1, update )
RGB444 Enable (ISP2_UpdateFlag=1, update )
SPI SCK freq div
SPI Master Mode Enable
SPI SSn vsync timing (Master mode)
SPI Slave Mode Enable
SPI CTS Enable (Master mode)
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: [email protected]
14
V1.0, 2009/08/12
PixArt Imaging Inc.
PAS6167
CMOS Image Sensor IC
5. Reference Circuit Schematic
Parallel mode
PXCLK
A5
PXCLK
PXD4
A4
PXD4
PXD5
A3
PXD5
VSSD
B3
SYSCLK
SYSCLK
PXD7
A2
PXD7
U1
A1
DGND
VDDA
B1
B2
AGND
CSB
C1
SCL
D1
PXD0
VDDA
VSSA
PXD1
CSB
PXD3
SCL
PXD2
VDDMD
B4
PXD0
B5
PXD1
C4
PXD3
C5
PXD2
VDDMD
D5
VDDD
D4
VSYNC
PXD6
HSYNC
C3
D3
C2
D2
SDA
PAS6167LT
HSYNC
VSYNC
PXD6
SDA
VDDA
VDDD
VDDD
VDDMD
C1
C2
C3
0.1uF
0.1uF
0.1uF
AGND
DGND
DGND
Note:
Sensor pwdn pin, "CSB", high active
(connect to DGND if un-used)
VDDA, analog power, 2.5V ~ 2.8V
VDDMD, I/O power, 1.8V ~ 3.3V
VDDD, digital core power, 1.8V
DGND, digital ground
AGND, analog ground
All capacitors must be close to the sensor as possible
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: [email protected]
15
V1.0, 2009/08/12
PixArt Imaging Inc.
PAS6167
CMOS Image Sensor IC
Serial mode
SCK
A5
SCK
A4
NC
A3
NC
VSSD
B3
A2
SYSCLK
NC
U1
A1
SYSCLK
DGND
VDDA
B1
B2
AGND
CSB
C1
SCL
D1
SDO
VDDA
VSSA
OVERFLOW / READY
CSB
NC
SCL
NC / OVERFLOW
VDDMD
B4
SDO
B5
OVERFLOW / READY (MASTER / SLAVE)
C4
C5
NC / OVERFLOW (MASTER / SLAVE)
D5
VDDMD
VDDD
D4
CTS / NC
NC
SSn
C3
D3
C2
D2
SDA
PAS6167LT
SSn
SDA
VDDA
VDDD
VDDMD
C1
C2
C3
0.1uF
0.1uF
0.1uF
VDDD
AGND
DGND
DGND
CTS / NC (MASTER / SLAVE)
Note:
Sensor pwdn pin, "CSB", high active
(connect to DGND if un-used)
VDDA, analog power, 2.5V ~ 2.8V
VDDMD, I/O power, 1.8V ~ 3.3V
VDDD, digital core power, 1.8V
DGND, digital ground
AGND, analog ground
All capacitors must be close to the sensor as possible
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: [email protected]
16
V1.0, 2009/08/12
PixArt Imaging Inc.
PAS6167
CMOS Image Sensor IC
6. Package Information
*Note:
The formation of image is the result formed by package Top view(A1 : left-up) and general Lens(invert and mirror the image).
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: [email protected]
17
V1.0, 2009/08/12
PixArt Imaging Inc.
PAS6167
CMOS Image Sensor IC
Recommended Layout PCB
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: [email protected]
18
V1.0, 2009/08/12
PixArt Imaging Inc.
PAS6167
CMOS Image Sensor IC
Recommended Condition For Infrared Reflow
Carefully observe the mounting conditions, recommended temperature profile when
Mounting infrared reflows is show in the figure below.
After mounting on the mother board, it must be dispense epoxy in side of the CSP package.
☉ Reflow Profile
Recommend Reflow Profile
Melting area
250
Temp.
200
150
Pre-heat
100
50
0
0
20
40
60
80
100
120
140
160
180
200
220
Time ( Sec )
Recommend Pb-free solder paste vender & type :
Programming
rate
1.5~2.5 oC/sec
Pre-heat
170~200oC
90 +/- 30 sec
☉ Dispense Epoxy
1. Almit LFM-48W TM-HP
2. Senju M705-GRN360-K
Melting area
>220oC 30~50sec
with peak temperature 230~245oC
Epoxy
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: [email protected]
19
V1.0, 2009/08/12