2015
DP8051 IP Core
Pipelined High Performance 8-bit Microcontroller v. 4.01
COMPANY OVERVIEW
Digital Core Design is a leading IP Core provider and a System-on-Chip design house.
The company was founded in 1999 and since
the very beginning has been focused on IP
Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers and with more
than 500 hundred licenses sold to companies
like Intel, Siemens, Philips, General Electric,
Sony and Toyota. Based on more than 70 different architectures, starting from serial interfaces to advanced microcontrollers and SoCs,
we’re designing solutions tailored to your
needs.
IP CORE OVERVIEW
The DP8051 is an ultra-high performance,
speed optimized soft core of a single-chip 8bit embedded controller, dedicated to operate
with fast (typically on-chip) and slow (off-chip)
memories. The core has been designed with a
special concern for performance to power
consumption ratio. This ratio is extended by
an advanced power management unit - the
PMU. The DP8051 soft core is 100% binarycompatible with the industry standard 8051 8bit microcontroller. There are two configurations of the DP8051: Harvard, where an internal data and program buses are separated and
von Neumann, with common program and
external data bus. The DP8051 has a Pipelined
RISC architecture and executes 120-300 million instructions per second. Dhrystone 2.1
benchmark program runs from 11.46 to 15.55
times faster than the original 80C51 at the
same frequency. This performance can be also
exploited to a great advantage in low power
applications, where the core can be clocked
over ten times slower than the original implementation, with no performance penalty.
The DP8051 is delivered with fully automated
test bench and complete set of tests, allowing
easy package validation at each stage of SoC
design flow.
CPU FEATURES
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100% software compatible with 8051 industry
standard
Pipelined RISC architecture enables to execute 15.55 times faster than the original
80C51 at the same frequency
Up to 14.632 VAX MIPS at 100 MHz
24 times faster multiplication
12 times faster addition
Up to 256 bytes of internal (on-chip) Data
Memory
Up to 64K bytes of internal (on-chip) or external (off-chip) Program Memory
Up to 16M bytes of external (off-chip) Data
Memory
User programmable Program Memory Wait
States solution, for wide range of memories
speed
User programmable External Data Memory
Wait States solution, for wide range of memories speed
De-multiplexed Address/Data bus to allow
easy connection to memory
Dedicated signal for Program Memory writes.
Interface for additional Special Function Registers
Fully synthesizable, static synchronous design,
with positive edge clocking and no internal
tri-states
Scan test ready
LICENSING
Comprehensible and clearly defined licensing
methods without royalty-per-chip fees make
use of our IP Cores easy and simple.
Single-Site license option – dedicated to small
and middle sized companies, which run their
business in one place.
Multi-Site license option – dedicated to corporate customers, who operate at several locations. The licensed product can be used in
selected company branches.
In all cases the number of IP Core instantiations within a project and the number of
manufactured chips are unlimited. The license
is royalty-per-chip free. There are no restrictions regarding the time of use.
There are two formats of the delivered Core:
VHDL or Verilog RTL synthesizable source code
called HDL Source code
FPGA EDIF/NGO/NGD/QXP/VQM called Netlist
1
Copyright © 1999-2015 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
♦
● Installation notes
● HDL core specification
● Datasheet
PERIPHERALS
●
DoCD™ debug unit
○ Processor execution control
○ Run, Halt
○ Step into instruction
○ Skip instruction
○ Read-write all processor contents
○ Program Counter (PC)
○ Program Memory
○ Internal (direct) Data Memory
○ Special Function Registers (SFRs)
○ External Data Memory
○ Code execution breakpoints
○ up to eight real-time PC breakpoints
○ unlimited number of real-time OPCODE breakpoints
○ Hardware execution watch-points at
○ Internal (direct) Data Memory
○ Special Function Registers (SFRs)
○ External Data Memory
○ Hardware watch-points activated at a certain
○ address by any write into memory
○ address by any read from memory
○ address by write required data into memory
○ address by read required data from memory
○ Instructions Smart Trace Buffer – configurable
up to 8192 levels (optional)
○ Automatic adjustment of debug data transfer
speed rate between HAD and Silicon
○ TTAG or JTAG Communication interface
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Delivery of the IP Core and documentation up
dates, minor and major versions changes
Phone & email support
CONFIGURATION
The following parameters of the DP8051 core
can be easily adjusted to requirements of a
dedicated application and technology. The
configuration of the core can be effortlessly
done, by changing appropriate constants in
the package file. There is no need to change
any parts of the code.
Internal Program RAM Memory size
-
Internal Program Memory fixed size
- true
- false
Interrupts
-
Interrupt Controller
Power Management Mode
- used
- unused
○ 2 priority levels
○ 2 external interrupt sources
○ 3 interrupt sources from peripherals
Stop mode
- used
- unused
DoCD debug unit
- used
- unused
Power Management Unit
Four 8-bit I/O Ports
Two 16-bit timer/counters
Synchronous mode, fixed baud rate
8-bit asynchronous mode, fixed baud rate
9-bit asynchronous mode, fixed baud rate
9-bit asynchronous mode, variable baud rate
Source code:
● VHDL Source Code or/and
● VERILOG Source Code or/and
● Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
● Active-HDL automatic simulation macros
● ModelSim automatic simulation macros
● Tests with reference responses
-
0 - 64kB
0 - 64kB
subroutines
location
Except parameters mentioned above, all
available peripherals and external interrupts
can be excluded from the core, by changing
appropriate constants in the package file.
Full-duplex serial port
DELIVERABLES
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● IP Core implementation support
● 3 months maintenance
Internal Program ROM Memory size
○ Timers clocked by internal source
○ Auto reload 8-bit timers
○ Externally gated event counters
●
Synthesis scripts
Example application
Technical support
- synchronous
- asynchronous
○ Bit addressable data direction for each line
○ Read/write of single line and 8-bit group
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Internal Program Memory type
○ Power management mode
○ Switchback feature
○ Stop mode
●
Technical documentation
DESIGN FEATURES
♦
PROGRAM MEMORY:
The DP8051 soft core is dedicated to operate with
Internal and External Program Memory. Internal
Program Memory can be implemented as:
○ ROM located in address range between 0x0000
(ROMsize-1)
○ RAM located in address range between
(RAMsize-1) 0xFFFF
External Program Memory can be implemented as
ROM or RAM located in address range between
ROMsize RAMsize.
2
Copyright © 1999-2015 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
♦
INTERNAL DATA MEMORY:
The DP8051 can address Internal Data Memory of
up to 256 bytes The Internal Data Memory can be
implemented as Single-Port synchronous RAM.
♦
EXTERNAL DATA MEMORY:
The DP8051 soft core can address up to 16 MB of
External Data Memory. Extra DPX (Data Pointer
eXtended) register is used for segments swapping.
♦
USER SPECIAL FUNCTION REGISTERS:
Up to 104 External (user) Special Function Registers (ESFRs) may be added to the DP8051 design.
ESFRs are memory mapped into Direct Memory
between addresses 0x80 and 0xFF in the same
manner, as core SFRs and may occupy any address,
that is not occupied by a SFR core.
♦
WAIT STATES SUPPORT:
The DP8051 soft core is dedicated for operation
with wide range of Program and Data memories.
Slow Program and External Data memory may
assert a memory WAIT signal to hold up CPU activity, for required period of time.
PINS DESCRIPTION
PIN
clk
reset
port0i
port1i
port2i
port3i
iprgramsize
iprgromsize
prgramdata
prgromdata
TYPE
input
input
input
input
input
input
input
input
input
input
sxdmdatai
input
xdatai
ready
ramdatai
sfrdatai
int0
int1
t0
t1
gate0
gate1
rxdi0
tdi
tck
tms
rsto
port0o
port1o
port2o
port3o
prgaddr
input
input
input
input
input
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output
DESCRIPTION
Global clock
Global reset input
Port 0 input
Port 1 input
Port 2 input
Port 3 input
Size of on-chip RAM CODE
Size of on-chip ROM CODE
Data bus from int. RAM prog. memory
Data bus from int. ROM prog. memory
Data bus from sync external data memory
(SXDM)
Data bus from external memories
External memory data ready
Data bus from internal data memory
Data bus from user SFR’s
External interrupt 0
External interrupt 1
Timer 0 input
Timer 1 input
Timer 0 gate input
Timer 1 gate input
Serial receiver input 0
DoCD™ TAP data input
DoCD™ TAP clock input
DoCD™ TAP mode select input
Reset output
Port 0 output
Port 1 output
Port 2 output
Port 3 output
Internal program memory address bus
prgdatao
prgramwr
sxdmaddr
sxdmdatao
sxdmoe
sxdmwe
xaddr
xdatao
xdataz
xprgrd
xprgwr
xdatard
xdatawr
ramaddr
ramdatao
ramoe
ramwe
sfraddr
sfrdatao
sfroe
sfrwe
tdo
rtck
debugacs
coderun
pmm
stop
rxdo0
txd0
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
Data bus for internal program memory
Internal program memory write
Sync XDATA memory address bus (SXDM)
Data bus for Sync XDATA memory (SXDM)
Sync XDATA memory read (SXDM)
Sync XDATA memory write (SXDM)
Address bus for external memories
Data bus for external memories
Turn xdata bus into ‘Z’ state
External program memory read
External program memory write
External data memory read
External data memory write
Internal Data Memory address bus
Data bus for internal data memory
Internal data memory output enable
Internal data memory write enable
Address bus for user SFR’s
Data bus for user SFR’s
User SFR’s read enable
User SFR’s write enable
DoCD™ TAP data output
DoCD™ return clock line
DoCD™ accessing data
CPU is executing an instruction
Power management mode indicator
Stop mode indicator
Serial receiver output 0
Serial transmitter output 0
UNITS SUMMARY
ALU – Arithmetic Logic Unit - performs the
arithmetic and logic operations, during execution of an instruction. It contains accumulator
(ACC), Program Status Word (PSW), (B) registers and related logic, like arithmetic unit,
logic unit, multiplier and divider.
Opcode Decoder – Performs an opcode decoding instruction and control functions for all
other blocks.
Control Unit – It performs the core synchronization and data flow control. This module is
directly connected to Opcode Decoder and it
manages execution of all microcontroller
tasks.
Program Memory Interface – Program
Memory Interface contains Program Counter
(PC) and related logic. It performs the instructions code fetching. Program Memory can be
also written. This feature allows usage of a
small boot loader, to load new program into
ROM, RAM, EPROM or FLASH EEPROM storage
via UART, SPI, I2C or DoCD™ module.
External Memory Interface - Contains
memory access related registers, such as Data
Page High (DPH), Data Page Low (DPL) and
3
Copyright © 1999-2015 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
Data Page Pointer (DPP) registers. It performs
the external Program and Data Memory addressing and data transfers. Program fetch
cycle length can be programmed by the user.
This feature is called Program Memory Wait
States and it allows core, to work with different speed program memories.
Synchronous eXternal Data Memory (SXDM)
Interface – contains XDATA memory access
related logic, allowing fast access to synchronous memory devices. It performs the external Data Memory addressing and data transfers. This memory can be used to store large
variables, frequently accessed by CPU, improving overall performance of application.
Internal Data Memory Interface – Interface
controls access into the internal memory of
size up to 256 bytes. It contains 8-bit Stack
Pointer (SP) register and related logic.
User SFRs Interface – Special Function Registers interface controls access to the special
registers. It contains standard and used defined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified), by using all direct
addressing mode instructions.
Interrupt Controller – Interrupt Controller
module is responsible for the interrupt manage system of the external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt
Priority (IP) and (TCON) registers.
Timers – System timers module. Contains two
16 bits configurable timers: Timer 0 (TH0,
TL0), Timer 1 (TH1, TL1) and Timers Mode
(TMOD) registers. In the timer mode, timer
registers are incremented every 12 (or 4) CLK
periods, when appropriate timer is enabled. In
the counter mode, the timer registers are
incremented every falling transition on their
corresponding input pins (T0, T1), if gates are
opened (GATE0, GATE1). T0, T1 input pins are
sampled every CLK period. It can be used as
clock source for UARTs.
UART0 – Universal Asynchronous Receiver
and Transmitter module is full duplex, which
means, it can transmit and receive concurrently. Includes Serial Configuration register
(SCON), serial receiver and transmitter buffer
(SBUF) registers. Its receiver is double-
buffered, meaning, it can commence reception of a second byte, before the previously
received byte has been read from the receive
register. Writing to SBUF0 loads the transmit
register and reading SBUF0, reads a physically
separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0
can be synchronized by Timer 1 or Timer 2 (if
present in the system).
Ports - Block contains 8051’s general purpose
I/O ports. Each of port’s pin can be read/write
as a single bit or as a 8-bit bus P0, P1, P2, P3.
Power Management Unit – Power Management Unit contains advanced power saving
mechanisms with switchback feature, allowing
external clock control logic to stop clocking
(Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to
be processed in full speed mode, if enabled. It
is highly desirable, when microcontroller is
planned to be used in portable and power
critical applications.
DoCD™ Debug Unit – it’s a real-time hardware debugger, which provides debugging
capability of a whole SoC system. Unlike other
on-chip debuggers, DoCDTM ensures nonintrusive debugging of running application. It
can halt, run, step into or skip an instruction,
read/write any contents of microcontroller,
including all registers, internal and external
program memories and all SFRs, including user
defined peripherals. Hardware breakpoints
can be set and controlled on program
memory, internal and external data memories,
as well as on SFRs. Hardware watchpoints can
be set and controlled on internal and external
data memories and also on SFRs. Hardware
watchpoints are executed, if any write/read
occurs at particular address, with certain data
pattern or without pattern. Two additional
pins: CODERUN and DEBUGACS, indicate the
state of the debugger and CPU. CODERUN is
active, when CPU is executing an instruction.
DEBUGACS pin is active, when any access is
performed by DoCDTM debugger. The DoCDTM
system includes TTAG or JTAG interface
and complete set of tools, to communicate
and work with core in real time debugging. It
is built, as a scalable unit and some features
4
Copyright © 1999-2015 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
can be turned off by the user, to save silicon
and reduce power consumption. When debugger is not used, it is automatically switched
to power save mode. Finally, when debug
option is no longer used, whole debugger is
turned off.
0xFFFF
0xF000
Off chip Memory
PROGRAM CODE SPACE
IMPLEMENTATION
The following figure shows an example Program Memory space implementation in systems with the DP8051 Microcontroller core.
The on-chip Program Memory located in address space between 0kB and 1kB, is typically
used for BOOT code, with system initialization
functions. This part of the code is typically
implemented as ROM. The on-chip Program
Memory located in address space between
60kB and 64kB, is typically used for timing
critical part of the code e.g. interrupt subroutines, arithmetic functions etc. This part of the
code is typically implemented as RAM and can
be loaded by the BOOT code, during initialization phase from an off-chip memory or
through a RS232 interface from an external
device. From the two spaces mentioned
above, the program code is executed without
wait-states and can achieve top performance,
up to 200 million instructions per second
(many instructions executed in one clock cycle). The off-chip Program Memory located in
address space between 1kB and 60kB, is typically used for a main code and constants. This
part of the code is usually implemented as
ROM, SRAM or FLASH device. Due to relatively
long access time, the program code executed
from devices mentioned above, must be
fetched with additional Wait-States. The number of required Wait-States depends on a
memory access time and the DP8051 clock
frequency. In most cases, the proper number
of Wait-States cycles is in range 2 to 5. The
READY pin can be also dynamically modulated
e.g. by SDRAM controller. The figure across
shows typical Program Memories connection
in system with the DP8051 Microcontroller
core.
On chip Memory
(implemented as RAM)
(implemented as ROM, SRAM
or FLASH)
0x0400
0x0000
On-chip Memory
(implemented as ROM)
8
prgramdatai
8
prgdatao
prgramwr
On-chip Memory
12
(implemented as RAM)
0 Wait-State access
prgaddr
10
8
prgromdatai
On-chip Memory
(implemented as ROM)
0 Wait-State access
ASIC or FPGA chip
DP8051
xdatai
8
xdatao
xaddr
Off-chip Memory
16
xprgrd
(implemented as FLASH,
or SRAM)
e.g. 2-5 Wait-State access
xprgwr
ready
rsto
Wait-State
Manager
The implementation described above should
be treated only as an example. All Program
Memory spaces are fully configurable. For
timing-critical applications the whole program
code can be implemented as on-chip ROM and
(or) RAM and executed without Wait-States,
but for some other applications, the whole
program code can be implemented as off-chip
ROM or FLASH and executed with required
number Wait-State cycles.
5
Copyright © 1999-2015 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
SYMBOL
port0i
port1i
port2i
port3i
ramdatai
sfrdatai
prgramdatai
prgromdatai
xdatai
ready
sxdmdatai
int0
int1
t0
gate0
t1
gate1
BLOCK DIAGRAM
port0o
port1o
port2o
port3o
prgaddr
prgdatao
prgramwr
xaddr
xdatao
xdataz
xdatard
xdatawr
xprgrd
xprgwr
sxdmaddr
sxdmdatao
sxdmwe
sxdmoe
prgaddr
prgdatao
prgdatai
prgramwr
xaddress
xdatao
xdatai
xdataz
ready
xdatard
xdatawr
xprgrd
xprgwr
iprgromsize
iprgramsize
ramaddr
ramdatao
ramwe
ramoe
ramaddr
ramdatao
ramdatai
ramwe
ramoe
sfraddr
sfrdatao
sfroe
sfrwe
sfraddr
sfrdatao
sfrdatai
sfrwe
sfroe
Opcode
Decoder
I/O Port
Registers
port0
port1
port2
port3
Program
Memory
Interface
Timers
t0
t1
gate0
gate1
External
Memory
Interface
Interrupt
Controller
Control
Unit
Internal Data
Memory
Interface
PMM
Unit
iprgromsize
iprgramsize
rxd0o
txd0
DoCD™
Debug Unit
tdi
tck
tms
tdo
rtck
coderun
debugacs
SXDM
Interface
sxdmaddr
sxdmdatao
sxdmdatai
sxdmoe
sxdmwe
User
SFR’s
Interface
clk
reset
rsto
pmm
stop
stop
pmm
rxd0i
int0
int1
ALU
coderun
debugacs
rsto
reset
clk
6
Copyright © 1999-2015 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
DP8051 FAMILY OVERVIEW
-
Floating Point Coprocessor
-
Fixed Point Coprocessor
-
SPI
4
4
-
-
-
-
2
1
2
Slave I C Bus Controller
I\O Ports
2
3
2
UART
1
1
2
Master I C Bus Controller
Timer/Counters
2
2
2
Watchdog
Data Pointers
2
5
15
Compare/Capture
Interrupt levels
DP8051CPU 15.6 64k 64k 64k 256 256 16M
DP8051
15.6 64k 64k 64k 256 256 16M
DP8051XP 15.6 64k 64k 64k 256 256 16M
Interrupt sources
Interface for additional SFRs
External Data Memory space
External Data / Program
Memory Wait States
Power Management Unit
Internal Data Memory space
Stack space size
off-chip
on-chip ROM
Program
Memory
space
on-chip RAM
Design
Architecture speed grade
The main features of each DP8051 family member have been summarized in the table below. It gives
a brief member characteristic, helping you to select the most suitable IP Core for your application.
You can specify your own peripheral set (including listed below and others) and requests the core
modifications.
DP8051 family of Pipelined High Performance Microcontroller Cores
DP80390 FAMILY OVERVIEW
-
Floating Point Coprocessor
-
Fixed Point Coprocessor
-
SPI
4
4
-
-
-
-
2
I\O Ports
1
2
Slave I C Bus Controller
UART
2
3
2
Timer/Counters
1
1
2
Master I C Bus Controller
Data Pointers
2
2
2
Watchdog
Interrupt levels
2
5
15
Compare/Capture
Interrupt sources
DP80390CPU 15.6 64k 64k 8M 256 256 16M
DP80390
15.6 64k 64k 8M 256 256 16M
DP80390XP 15.6 64k 64k 8M 256 256 16M
Interface for additional SFRs
External Data Memory space
External Data / Program
Memory Wait States
Power Management Unit
Internal Data Memory space
Stack space size
off-chip
on-chip ROM
Program
Memory
space
on-chip RAM
Design
Architecture speed grade
The main features of each DP80390 family member have been summarized in the table below. It
gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed below and others) and requests the
core modifications.
DP80390 family of Pipelined High Performance Microcontroller Cores
7
Copyright © 1999-2015 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
PERFORMANCE
The following table gives a survey about the
Core area and performance in Programmable
Logic Devices after Place & Route (CPU features and peripherals have been included):
Device
Speed grade
Area
Fmax
FLEX10KE
-1
2250 LC
57 MHz
ACEX1K
-1
2250 LC
57 MHz
APEX20K
-1
2250 LC
50 MHz
APEX20KE
-1
2250 LC
66 MHz
APEX20KC
-7
2250 LC
78 MHz
APEX-II
-7
2250 LC
76 MHz
CYCLONE
-6
2250 LC
91 MHz
CYCLONE-II
-6
2250 LC
93 MHz
CYCLONE-III
-6
2400 LC
111 MHz
Arria GX
-6
1595 ALUT
112 MHz
STRATIX
-5
2250 LC
90 MHz
STRATIX-II
-3
1580 ALUT
160 MHz
STRATIX-III
-2
1580 ALUT
191 MHz
STRATIX-IV
-2
1580 ALUT
196 MHz
Core performance in ALTERA® devices – results given for working system with connected IDATA, CODE and XDATA memories
For the user, the most important aspect is an
application speed improvement. The most
commonly used arithmetic functions and their
improvement are shown in the table below.
The improvement was computed as {80C51
clock periods} divided by {DP8051 clock periods} required to execute an identical function.
More details are available in the core documentation.
Function
8-bit addition (immediate data)
8-bit addition (direct addressing)
8-bit addition (indirect addressing)
8-bit addition (register addressing)
8-bit subtraction (immediate data)
8-bit subtraction (direct addressing)
8-bit subtraction (indirect addressing)
8-bit subtraction (register addressing)
8-bit multiplication
8-bit division
16-bit addition
16-bit subtraction
16-bit multiplication
32-bit addition
32-bit subtraction
32-bit multiplication
Average speed improvement:
Improvement
9,00
9,00
9,00
12,00
9,00
9,00
9,00
12,00
16,00
9,60
12,00
12,00
13,60
12,00
12,00
12,60
11,12
Dhrystone Benchmark Version 2.1 was used to
measure the core performance. The following
table shows the DP8051 performance in terms
of VAX MIPS per 1 MHz rating.
Device
DMIPS/MHz
80C51
0,00941
DP8051
0,10787
DP8051+DPTRs
0,13722
DP8051+DPTRs+SXDM
0,14457
DP8051+DPTRs+SXDM+MDU32
0,14632
Core performance in terms of DMIPS per MHz
Ratio
1,00
11,46
14,58
15,36
15,55
VAX MIPS ratio
14,58
15
15,36 15,55
11,46
10
5
1
0
80C51
DP8051
DP8051+DPTRs
DP8051+DPTRs+SXDM
DP8051+DPTRs+SXDM+MDU32
CONTACT
For any modifications or special requests,
please contact Digital Core Design or local
distributors.
DCD’s headquarters:
Wroclawska 94
41-902 Bytom, POLAND
e-mail: : [email protected]
tel. : +48 32 282 82 66
fax : +48 32 282 74 37
Distributors:
Please check: http://dcd.pl/sales
8
Copyright © 1999-2015 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.