High Speed Translator Buffer to PECL FEATURES Input clock frequency ≤266 MHz JEDEC standard Differential LVPECL output 70mA typical power supply current 300ps Max. Rise/Fall time 740ps input propagation delay LVCMOS and LVTTL Input compatible Single 2.5V ±5% or 3.3V ±10% power supply with V EE =0V Available in 8 pin SOP Green/RoHS compliant Package PIN CONFIGURATION (TOP VIEW) DNC 1 8 VCC REF-IN 2 7 Q OE 3 6 QB DNC 4 5 VEE SOP-8L DESCRIPTION The PL130-58 is a low cost, high performance, high speed, translator buffer that produces a pair of differential LVPECL outputs from CMOS input. Outputs are JEDEC standard LVPECL signals. The device is targeted for Backplane buffering, data distribution, Fibre Channel and many other applications. BLOCK DIAGRAM 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 08/25/11 Page 1 High Speed Translator Buffer to PECL PIN DESCRIPTIONS Name SOP-8L Type DNC 1, 4 - REF-IN 2 Input OE VEE QB Q VCC 3 5 6 7 8 Input Power Output Output Power Description Do Not Connect Reference input signal. The frequency of this signal will be reproduced at the output (after translation to PECL level). Output enable (‘1’ for enable). Internal pull-up (default is ‘1’). Power Ground. PECL Complementary output. PECL True output. Positive Power Supply. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage MIN. V DD MAX. UNITS 4.6 V Input Voltage, dc VI -0.5 V DD +0.5 V Output Voltage, dc VO -0.5 V DD +0.5 V Storage Temperature TS -65 150 C Ambient Operating Temperature* TA -40 85 C Junction Temperature TJ 110 C 260 C Lead Temperature (soldering, 10s) Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. AC Specifications PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS Input Frequency 266 MHz Output Frequency 266 MHz 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 08/25/11 Page 2 High Speed Translator Buffer to PECL 3. DC CHARACTERISTICS, VCC = 3.3V ±10%; VEE = 0V; T A = -40ºC TO +85ºC Parameter Output High Voltage* Output Low Voltage* Input High Voltage† Input Low Voltage† Input High Current Input Low Current Symbol VOH VOL VIH VIL IIH IIL Min -40°C Typ 2.215 2.320 1.470 1.610 0.7VCC -0.3 -150 Max Min 2.420 2.275 1.745 1.490 VCC+0.3 0.7VCC 0.3VCC -0.3 200 -150 25°C Typ 2.350 1.585 Max Min 80°C Typ Max 2.420 2.275 2.35 2.420 1.680 1.490 1.585 1.680 VCC+0.3 0.7VCC VCC+0.3 0.3VCC -0.3 0.3VCC 200 200 -150 Units V V V V µA µA 4. DC CHARACTERISTICS, VCC = 2.5V ±5%; VEE = 0V; T A = -40ºC TO +85ºC Parameter Symbol Min -40°C Typ Max Min 25°C Typ Max Min 80°C Typ Max Output High Voltage* Output Low Voltage* Input High Voltage† Input Low Voltage† Input High Current Input Low Current VOH 1.415 1.520 1.620 1.475 1.550 1.620 1.475 1.55 1.620 VOL 0.670 0.810 0.945 0.690 0.785 0.880 0.690 0.785 0.880 VIH 0.7VCC VCC+0.3 0.7VCC VCC+0.3 0.7VCC VCC+0.3 0.3VCC VIL -0.3 0.3VCC -0.3 -0.3 0.3VCC IIH 150 150 150 IIL -120 -120 -120 . Input and output parameters vary 1:1 with VCC VEE can vary +0.925V to -0.5V. Input parameters vary with the ratio of VI : (VCC - VEE) * Outputs terminated with 50 Ω to V CCO – 2V. † VIH/VIL apply to REF_IN. 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 08/25/11 Page 3 Units V V V V µA µA High Speed Translator Buffer to PECL 6. PECL Switching Characteristics PARAMETERS SYMBOL CONDITIONS Clock Rise Time tr Clock Fall Time tf MIN. MAX. UNITS @20/80% of output waveform 300 ns @80/20% of output waveform 300 ns PECL Levels Test Circuit OUT PECL Output Skew VDD 50 TYP. OUT 2.0V 50% 50 OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 08/25/11 Page 4 High Speed Translator Buffer to PECL PACKAGE INFORMATION (GREEN PACKAGE COMPLIANT) 8 PIN (dimensions in mm) SOP–8L Symbol Min. Max. A 1.47 1.73 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 4.95 E 3.80 4.00 H 5.80 6.20 L 0.38 1.27 e E H D A A 1 1.27 BSC C L B e ORDERING INFORMATION For part ordering, please contact our Sales Department: 2880 Zanker Road, San Jose, CA 95134 USA Tel (408) 571-1668 Fax (408) 571-1688 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range Order Number PL130-58SC-R PL130-58SC Marking P130-58 SC LLLLL Package Option SOP-8L - Tape and Reel SOP-8L - Tube *Note: LLLLL designates lot number PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 08/25/11 Page 5