BL5372 Low Power Real-Time Clock (RTC) SHANGHAI BELLING GENERAL DESCRIPTION FEATURES The BL5372 is a CMOS type real-time clock, which is connected to the CPU via two wires and capable of serial transmission of clock to the CPU. The BL5372 can generate various periodic interrupt clock pulses lasting for long period (one month), and alarm interrupt can be made by two incorporated systems. Since an oscillation circuit is driven at a constant voltage, it undergoes fluctuations of few voltage and consequently offers low current consumption (TYP. 400nA @ 5V) It also provides an oscillator halt sensing function applicable for data validation at power-on and other occasions. The product also incorporates a time trimming circuit that adjusts the clock with higher precision by adjusting any errors in crystal oscillator frequencies based on signals from the CPU. The crystal oscillator may be selected from 32KHz or 32.768KHz types. It adopts 8-pin SOP or TSSOP package. Lowest supply current: 400nA TYP. @ 5V Connected to the CPU via only 2-wires (MAX. 100KHz) A clock counter (counting hours, minutes, and seconds) and a calendar counter (counting leap years, years, months, days, and days of the week) in BCD codes Two systems output providing interrupt to the CPU output (period of one month to one second, interrupt halt function) Two systems output of alarm functions Oscillation halt sensing to judge internal data validity Clock output of 32.768KHz (32KHz) (output controllable via a register) Second digit adjustment by ±30 seconds Automatic leap year recognition up to the year 2099 12-hour or 24-hour time display selectable High precision time trimming circuit Oscillator of 32.768KHz or 32KHz may be used CMOS logic Package: 8pin SOP or TSSOP BL5372 Data Sheet 1 Shanghai Belling ORDERING INFORMATION Type number BL5372 BL5372T Package Description plastic small outline package;8 pins; body width 3.9mm plastic thin shrink small outline package; 8 pins; body width 4.3mm Name SOP8 TSSOP8 BLOCK DIAGRAM 1 2 3 4 PIN DEFINITION Pin No. Symbol 1 INTRB 2 SCL 3 SDA 4 GND 5 INTRA 6 OSCOUT 7 OSCIN 8 VDD 8 7 6 5 8pin TSSOP INTRB 1 SCL 2 SDA 3 GND 4 VDD OSCIN OSCOU T INTRA Definition Interrupt Output B Serial Clock Line Serial Data Line Ground Power Interrupt Output A Oscillator Circuit Output Oscillator Circuit Input Supply Voltage Value 0~12V 0~5.5V 0~5.5V 0V 0~12V 0~1.5V 0~1.5V 1.8V~5.5V 2 BL5372 Data Sheet BL5372T INTRB SCL SDA GND BL5372 PIN CONFIGURATION 8pin SOP 8 7 6 5 VDD IN OSCOUT OSCRA INT IN/OUT OUT IN IN/OUT POWER OUT OUT IN POWER Shanghai Belling VDD and GND BL5372 VDD GND C1 0.1u + C2 VDD GND Bypass Capacitance The VDD pin is connected to the positive power supply and GND to the ground. To prevent the possibility of noise, when rapidly changing signal took place on BL5372 pin, we have to place a capacitance beside the BL5372. One possibility is to place a bypass capacitance as close as to the BL5372. The capacitance capacity of C2 could be determined per user’s demand, which provides large current passing ability between the pin and the ground. OSCIN and OSCOUT These pins configure an oscillator circuit by connecting a crystal oscillator between the OSCIN-OSCOUT pins. The diagram beside shows the connection method of such crystal oscillator circuit. It’s recommended to choose the right crystal oscillator parameter referring to the supplier’s suggestion, since it does determine the start-up reliability and oscillation stability provided by external devices. The influence of the distributing capacitance should be considered when choosing capacitance capacity in an oscillator circuit. To minimize output distortion, both crystal oscillator and capacitance should be installed as close to BL5372 pin as possible. Crystal Oscillator Connection with External Capacitance SCL and SDA SCL and SDA are Serial Clock Line and Serial Data Line, relatively. SCL is used to input shift clock pulses to synchronize data input/output to and from the SDA pin with this clock. SDA inputs and outputs written or read data in synchronization with shift clock pulses from the SCL pin. Depend on different level of current, separate pull-up resistance can be added to SCL and SDA on exterior circuit board. INTRA and INTRB INTRA and INTRB are two interrupt output ports and are both open drain outputs. When using BL5372 a pull-up resistance must be connected with pins of INTRA and INTRB. INTRA could output periodic interrupt pulses and alarm interrupt (ALARM-A, ALARM-B); INTRB could output 32.768KHz clock pulses (when 32.768KHz crystal is used), periodic interrupt pulses, alarm interrupt (ALARM-B). When power is activated from 0V, it could output 32.768kHz clock pulses (when 32.768KHz crystal is used). BL5372 Data Sheet 3 Shanghai Belling FUNCTIONAL DESCRIPTIONS Allocation of Internal Addresses Internal Contents Address 0H Second Counter 1H Minute Counter 2H Hour Counter 3H Day of the Week Counter 4H Day Counter 5H Month Counter 6H Year Counter 7H Time Trimming Register 8H EH Alarm_A (Minute Register) Alarm_A (Hour Register) Alarm_A (Day of the Week Register) Alarm_B (Minute Register) Alarm_B (Hour Register) Alarm_B (Day of the Week Register) Control Register 1 FH Control Register 2 9H AH BH CH DH Function Counting and storing seconds in BCD codes Counting and storing minutes in BCD codes Counting and storing hours in BCD codes Counting and storing days of the week in BCD codes Counting and storing days in BCD codes Counting and storing months in BCD codes Counting and storing years in BCD codes Storing adjusting parameter and external select control of crystal oscillator Storing minutes in Timer A Storing hours in Timer A Storing days of the week in Timer A Storing minutes in Timer B Storing hours in Timer B Storing days of the week in Timer B Storing ring enable, interrupt output port select, and periodic interrupt cycle select information Storing time display select, interrupt and alarm signal, oscillator halt sensing information Calendar Counter The BL5372 can exchange from year to second (lower two bits) with CPU. When the lower two bits of the year could be divided by 4, that year is leap year. It could automatically recognize the year between 2000 and 2099 and these data are stored separately in registers from 0H to 6H. Control Unit The control unit is a substantial part of the BL5372, under which all functionalities of the whole circuit is realized. The time display select, interrupt / alarm select and signal, output port select, as well as oscillation halt sensing information are all sent out by the control circuit. High Precision time Trimming function The BL5372 has an internal oscillation circuit capacitance CGND and CVDD so that an oscillation circuit may be configured simply by externally connecting a crystal. The BL5372 incorporates a time trimming circuit (at internal address 7H) that adjusts gain or loss of the clock from the CPU up to approx. ± 189ppm( ± 194ppm when 32.000KHz crystal is used) by approximately 3ppm steps to correct discrepancy in oscillation frequency. Clock display is possible at much higher precision than conventional real-time clock while using a crystal with broader fluctuation in precision. Even seasonal frequency fluctuation may be corrected by adjusting seasonal clock error. For those systems that have temperature detection precision of clock, function may be increased by correcting clock error according to temperature fluctuations. Alarm function and Periodic Interrupt Alarm Function: The BL5372 has an alarm function that outputs an interrupt signal from⎯ INTRA or ⎯INTRB output pins to the CPU when the day of the week, hour or minute corresponds to the setting. These two systems of alarms (ALARM-A, ALARM-B), each may output interrupt signal separately at a specific time. The 4 BL5372 Data Sheet Shanghai Belling alarm may be selectable between on and off for each day of the week, thus allowing outputting alarm everyday or on a specific day of the week. The ALARM-A is output from the⎯INTRA pin while the ALARM-B is output from either the ⎯INTRA or the⎯INTRB pins. Polling is possible separately for each alarm function. Periodic Interrupt: The BL5372 can output periodic interrupt pulses in addition to alarm function from the ⎯INTRA and ⎯INTRB pins. This frequency may be selected from 2Hz, 1Hz, 1/60Hz, 1/3600Hz and monthly by controlling register (at lower 3 bits of internal address EH) output selectively. Output waveform for periodic interrupt may be selected from regular pulse waveform (2Hz and 1Hz) and waveforms (every second, every minute, every hour and every month) that are appropriate for CPU level interrupt. Oscillation Halt Sensing The oscillation halt sending function uses a register (XSTP bit at internal address FH) to store oscillation halt information. This function may be used to determine if the BL 5372 supply power has been booted from 0V and if it has been backed up. This function is useful for determining if clock data is valid or invalid. Clock Output The BL5372 may output oscillation frequency from INTRB pin. This clock output is set for output by default, which is set to on or off by setting the register (internal address FH bit CLEN). It can also choose different crystal oscillator (32.768KHz or 32.000KHz) by setting the register (internal address 7H at bit XSL), and output clock pulses with two different frequencies. BL5372 Data Sheet 5 Shanghai Belling REGISTERS 1. Clock Counter（at internal address 0-2H） Time digit display (in BCD code) Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00. Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00. Hour digits: See descriptions on the⎯12/24 bit (Section 7). Carried to day and day-of-the week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. Any registered imaginary time should be replaced with correct time as carrying to such registered imaginary time digits from lower-order ones cause the clock counter malfunction. Second digit register (at internal address 0H) D7 0 0 D6 S40 S40 Undefined D5 S20 S20 Undefined D4 S10 S10 Undefined D3 S8 S8 Undefined D2 S4 S4 Undefined D1 S2 S2 Undefined D0 S1 S1 Undefined Operation Write Read Default D2 M4 M4 Undefined D1 M2 M2 Undefined D0 M1 M1 Undefined Operation Write Read Default Minute digit register (at internal address 1H) D7 0 0 D6 M40 M40 Undefined D5 M20 M20 Undefined D4 M10 M10 Undefined D3 M8 M8 Undefined Hour digit register (at internal address 2H) D7 D6 D5 D4 D3 D2 D1 D0 Operation H10 H8 H4 H2 H1 Write H20 or P/⎯A 0 0 H10 H8 H4 H2 H1 Read H20 or P/⎯A 0 0 Undefined Undefined Undefined Undefined Undefined Undefined Default *Default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc. 2. Day-of-the-week Counter (at internal address 3H) Day-of-the-week digits are incremented by 1 when carried to 1-day digits. Day-of-the-week digits display (incremented in septimal notation): (W4,W2,W1) = (0,0,0)→(0,0,1)→……→(1,1,0)→(0,0,0) The relation between days of the week and day-of-the-week digits is defined as: Sunday=(0,0,0); Monday=(0,0,1); …… ; Saturday=(1,1,0). (W4, W2, W1) should not be set to (1,1,1). Operation D7 D6 D5 D4 D3 D2 D1 D0 Write W4 W2 W1 Read 0 0 0 0 0 W4 W2 W1 Undefined Undefined Undefined Default 0 0 0 0 0 *The default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc. 3. Calendar Counter (at internal address 4-6H) The automatic calendar function provides the following calendar digit displays in BCD code and could recognize the leap year. Day digits: Range from 1 to 31 (for January, March, May, July, August, October, and December). 6 BL5372 Data Sheet Shanghai Belling Range from 1 to 30 (for April, June, September, and November). Range from 1 to 29 (for February in leap years). Range from 1 to 28 (for February in ordinary years). Month digits: Range from 1 to 12 and carried to year digits when cycled to 1. Carried to year digits when cycled from 12 to 1. Year digits: Range from 00 to 99 and 00,04,08, ……, 92, and 96 are counted as leap years. Any registered imaginary time should be replaced with correct time as carrying to such registered imaginary time digits from lower-order ones cause the clock counter malfunction. Day digit register (at internal address 4H) Operation D7 D6 D5 D4 D3 D2 D1 D0 Write D20 D10 D8 D4 D2 D1 Read 0 0 D20 D10 D8 D4 D2 D1 Undefined Undefined Undefined Undefined Undefined Undefined Default 0 0 *Default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc. Month digit register (at internal address 5H) Operation D7 D6 D5 D4 D3 D2 D1 D0 Write MO10 MO8 MO4 MO2 MO1 Read 0 0 0 MO10 MO8 MO4 MO4 MO1 Undefined Undefined Undefined Undefined Undefined Default 0 0 0 *Default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc. Year digit register (at internal address 6H) Operation D7 D6 D5 D4 D3 D2 D1 D0 Write Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 Read Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Default *Default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc. 4. Time Trimming Register (at internal address 7H) Operation D7 D6 D5 D4 D3 D2 D1 D0 Write XSL_ F6 F5 F4 F3 F2 F1 F0 Read XSL_ F6 F5 F4 F3 F2 F1 F0 Default 0 0 0 0 0 0 0 0 *Default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc. XSL bit The ⎯XSL bit is used to select a crystal oscillator. Set the ⎯XSL to“0”(default) to use 32.768KHz；Set ⎯XSL to“1”to use 32KHz. counting up to seconds is made once per 32,768 of clock pulse (or 32,000 when 32.000KHz crystal is used) generated by the oscillator. Setting data to this register activates the time trimming circuit. F6 to F0 The time trimming circuit adjust one second count based on this register readings when second digit is 00，20，or 40 seconds. Normally, Register counts will be incremented as ((F5, F4, F3, F2, F1, F0)-1) x2 when F6 is set to “0”. Register counts will be decremented as ((⎯F5, BL5372 Data Sheet 7 Shanghai Belling ⎯F4, ⎯F3, ⎯F2, ⎯F1, ⎯F0)+1) x2 when F6 is set to “1”. Counts will not change when (F6, F5, F4, F3, F2, F1, F0) are set to (*, 0, 0, 0, 0, 0, *). set to (1,1,0,1,0,0,1), counts will change as: 32768+（-17+1）*2=32736 (clock will be advanced) when second digit is 00, 20, or 40. For example, when 32.768KHz crystal is used. When (F6, F5, F4, F3, F2, F1, F0) are set to (0,1, 0, 1, 0, 0,1), counts will change as: 32768+（29-1）*2=32824 (clock will be delayed) when second digit is 00, 20, or 40. When (F6, F5, F4, F3, F2, F1, F0) are set to (0, 0, 0, 0, 0, 0, 1), counts will remain 32,768 without changing when second digit is 00, 20, or 40. When (F6, F5, F4, F3, F2, F1, F0) are Adding 2 clock pulses every 20 seconds: 2/ （32768*20）=3.051ppm (or 3.125ppm when 32.000KHZcrystal is used), delays the clock by approx. 3ppm. Likewise, decrementing 2 clock pulses advances the clock by 3ppm. Thus the clock may be adjusted to the precision of ± 1.5ppm. Note that the time trimming function only adjusts clock timing and oscillation frequency but 32.768KHz clock output is not adjusted. 5. Alarm Register (Alarm-A: internal address 8-AH; Alarm-B: internal address B-DH) Alarm-A minute register (at internal address 8H) D7 0 0 D6 AM40 AM40 Undefined D5 AM20 AM20 Undefined D4 AM10 AM10 Undefined D3 AM8 AM8 Undefined D2 AM4 AM4 Undefined D1 AM2 AM2 Undefined D0 AM1 AM1 Undefined Operation Write Read Default D2 BM4 BM4 Undefined D1 BM2 BM2 Undefined D0 BM1 BM1 Undefined Operation Write Read Default Alarm-B minute register (at internal address BH) D7 0 0 D6 BM40 BM40 Undefined D5 BM20 BM10 Undefined D4 BM10 BM10 Undefined D3 BM8 BM8 Undefined Alarm-A hour register (at internal address 9H) D7 0 0 D6 0 D5 AH20,AP/⎯A AH20,AP/⎯A Undefined D4 AH10 AH10 Undefined D3 AH8 AH8 Undefined D2 AH4 AH4 Undefined D1 AH2 AH2 Undefined D0 AH1 AH1 Undefined Operation Write Read Default Alarm-B hour register (at internal address CH) D7 0 0 D6 0 0 D5 BH20,BP/⎯A BH20,BP/⎯A Undefined D4 BH10 BH10 Undefined D3 BH8 BH8 Undefined D2 BH4 BH4 Undefined D1 BH2 BH2 Undefined D0 BH1 BH1 Undefined Operation Write Read Default D1 AW1 AW1 Undefined D0 AW0 AW0 Undefined Operation Write Read Default Alarm-A day-of-the-week register (at internal address AH) D7 0 0 D6 AW6 AW6 Undefined D5 AW5 AW5 Undefined D4 AW4 AW4 Undefined D3 AW3 AW3 Undefined D2 AW2 AW2 Undefined 8 BL5372 Data Sheet Shanghai Belling Alarm-B day-of-the-week register (at internal address DH) D7 0 0 D6 D5 D4 D3 D2 D1 D0 Operation BW6 BW5 BW4 BW3 BW2 BW1 BW0 Write BW6 BW5 BW4 BW3 BW2 BW1 BW0 Read Undefined Undefined Undefined Undefined Undefined Undefined Undefined Default *Default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc. ALARM-A, ALARM-B hour register D5 is set to “0” for AM and “1” for PM in the 12-hour display system. The register D5 indicates 10 digit of hour digit in 24-hour display system. To activate alarm operation, any imaginary alarm time setting should not be left to avoid un-matching. In hour digit display midnight is et to “12”, noon is set to “32” in 12-hour display system. AW0 to AW6 (BW0 to BW6) correspond to the day-of-the-week counter being set at (0, 0, 0) to (1, 1, 0). No alarm pulses are output when all of AW0 to AW6 (BW0 to BW6) are set to “0”. Example of Alarm Time Settings Alarm Time Settings 00:00AM every day 05:27AM every day 11:59AM every day 00:00PM on Mon thru Fri 05:56PM on Wed 11:59PM on Tue, Thu, and Sat Sun 1 Day-of-the-week Mon Tue Wed Thu 1 1 1 1 Fri 1 Sat 1 12-hour system 10H 1H 10M 1M 1 2 0 0 24-hour system 10H 1H 10M 1M 0 0 0 0 1 1 1 1 1 1 1 0 5 2 7 0 5 2 7 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9 0 1 1 1 1 1 0 3 2 0 0 1 2 0 0 0 0 0 1 0 0 0 2 5 5 6 1 7 5 6 0 0 1 0 1 0 1 3 1 5 9 2 3 5 9 6. Control Register 1 (at internal address EH) D7 D6 D5 D4 D3 D2 D1 D0 Operation AALE BALE SL2 SL1 TEST CT2 CT1 CT0 Write AALE BALE SL2 SL1 TEST CT2 CT1 CT0 Read 0 0 0 0 0 0 0 0 Default *The default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc. BL5372 Data Sheet 9 Shanghai Belling AALE，BALE ALARM-A，ALARM-B enable bits Description ALARM-A，ALARM-B correspondence action invalid ALARM-A，ALARM-B correspondence action valid AALE，BALE 0 1 Operation Default SL2，SL1 Interrupt output select bits SL2 0 SL1 0 0 1 1 0 1 1 Description Outputs ALARM-A, ALARM-B, INT to the INTRA. Outputs 32K clock pulses to the INTRB. Outputs ALARM-A, INT to the INTRA. Outputs 32K clock pulses, ALARM-B to the INTRB. Outputs ALARM-A, ALARM-B to the INTRA. Outputs 32K clock pulses, INT to the INTRB. Outputs ALARM-A to the INTRA. Outputs 32K clock pulses, ALARM-B, INT to the INTRB. Operation Default By setting SL1 and SL2 bits, two alarm pulses (ALARM-A, ALARM-B), periodic interrupt output (INT), 32K clock pulses may be output to the INTRA or INTRB pins selectively. TEST BL5372 Test bit Description Operation TEST Default 0 Ordinary operation mode 1 Test mode The test bit is used for BL5372 test. Set the TEST bit to 0 in ordinary operation. CT2，CT1，CT0 Periodic interrupt cycle select bit CT2 0 0 0 0 1 1 1 1 CT1 0 0 1 1 0 0 1 1 CT0 0 1 0 1 0 1 0 1 Wave Form Mode Pulse Mode Pulse Mode Level Mode Level Mode Level Mode Level Mode Description Cycle and INTRA（INTRB）Falling Timing INTRA（INTRB）at high level INTRA（INTRB）at low level 2Hz（Duty 50%） 1Hz（Duty 50%） Every second（synchronized with second count up） Every minute（00 second of every minute） Every hour（00 minute 00 second of every hour） Every month（the 1st day 00 A.M. 00 minute 00 second of every month） 1） Pulse mode: Outputs 2Hz, 1Hz clock pulses. For relationships with counting up of seconds see the diagram below. In the 2Hz clock pulse mode, 0.496s clock pulses and 0.504s clock pulses are output alternatively. Duty cycle for 1Hz clock pulses becomes 50.4%. 2） Level mode: One second, one minute or one month may be selected for an interrupt cycle. Counting up of seconds is matched with falling edge of interrupt output. 10 BL5372 Data Sheet Shanghai Belling 3） When the time trimming circuit is used, periodic interrupt cycle changes every 20 seconds. Pulse mode: “L” duration of output pulses may change in the maximum range of ±3.784ms (±3.875ms when 32KHz crystal is used). For example, Duty will be 50±0.3784% (or 50±0.3875% when 32KHz crystal is used) at 1Hz. Level Mode: Frequency is one second may change in the maximum range of ±3.784ms (± 3.875ms when 32KHz crystal is used). Relation Between Mode Waveforms and CRFG Bit Pulse mode Level mode CTFG INTRA(INTRB) CTFG=0 CTFG=0 Second count-up Second count-up Second count-up 7. Control Register 2 (at internal address FH) D7 D6 D5 D4 D3 D2 D1 D0 Operation 12_/24 ADJ CLEN_ CTFG AAFG BAFG Write 0 0 12_/24 XSTP CLEN_ CTFG AAFG BAFG Read 0 0 Undefined 1 0 0 0 0 Default *The default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc. ⎯12/24 ⎯12/24-hour Time Display System Selection bit ⎯12/24 0 1 Description 12-hour time display system 24-hour time display system Being set this bit at “0” indicates 12-hour display system while “1” indicates 24-hour system. BL5372 Data Sheet 11 Shanghai Belling Time Display Digit Table 24-hour time display 12-hour time display 24-hour time display 12-hour time display system system system system 00 12(AM12) 12 32(PM12) 01 01(AM1) 13 21(PM1) 02 02(AM2) 14 22(PM2) 03 03(AM3) 15 23(PM3) 04 04(AM4) 16 24(PM4) 05 05(AM5) 17 25(PM5) 06 06(AM6) 18 26(PM6) 07 07(AM7) 19 27(PM7) 08 08(AM8) 20 28(PM8) 09 09(AM9) 21 29(PM9) 10 10(AM10) 22 30(PM10) 11 11(AM11) 23 31(PM11) Either the 12-hour or 24-hour time display system should be selected before writing time data. ADJ ±30 Second Adjust Bit ADJ 0 1 Description Ordinary operation Second digit adjustment The following operations are performed by setting the second ADJ bit to 1 1） For second digits ranging from “00” to “29” seconds：Time counters smaller than seconds are reset and second digits are set to “00”. 2） For second digits ranging from “30” to “59” seconds: Time counters smaller than seconds are reset and second digits are set to “00”. Minute digits are incremented by 1. Second digits are adjusted within 122us(within 125us: when 32KHz crystal is used) from writing operation to ADJ. The ADJ bit is for write only and allows no read operation. XSTP Oscillator Halt Sending Bit XSTP 0 1 Description Ordinary oscillation Oscillator halt sensing Operation default The XSTP bit senses the oscillator halt. When oscillation is halted after initial power on from 0V or drop in supply voltage the bit is set to “1” and which remains to be “1” after it is restarted. This bit may be used to judge validity of clock and calendar count data after power on or supply voltage drop. When this bit is set to “1”, ⎯XSL，F6 to F0，CT2，CT1，CT0，AALE，BALE，SL2， SL1，⎯CLEN and TEST bits are reset to “0”. ⎯INTRA will stop output and the ⎯INTRB will output 32KHz clock pulses. The XSTP bit is set to “0” by setting the control register 2 (address FH) during ordinary oscillation. 12 BL5372 Data Sheet Shanghai Belling CLEN 32KHz Clock Output Bit ⎯CLEN 0 1 Description 32KHz clock output enabled 32KHz clock output disabled Operation Default By setting this bit to “0”, output of clock pulses of the same frequency as the crystal oscillator is enabled. CTFG Periodic Interrupt Flag Bit CTFG 0 1 Description Periodic interrupt output=OFF Periodic interrupt output=ON Operation Default This bit is set to “1” when periodic interrupt pulses are output (⎯INTRA or ⎯INTRB= “L”). The CTFG bit may be set only to “0” in the interrupt level mode. Setting this bit to “0” sets either the⎯INTRA or the⎯INTRB to OFF (“H”). When this bit is set to “1” nothing happens. AAFG，BAFG ALARM-A, ALARM-B Flag Bit Description Unmatched alarm register with clock counter Matched alarm register with clock counter ALARM-A，ALARM-B 0 1 Operation Default The alarm interruption is enabled only when the AALE, BALE bits are set to “1”. This bit turns to “1” when matched time is sensed for each alarm. The AAFG, BAFG bit may be set only to “0”. Setting this bit to “0” sets either the ⎯INTRA or the⎯ INTRB to the OFF “H”. When this bit is set to “1” nothing happens. When the AALE, BALE bit is set to “0”, alarm operation is disabled and “0” is read from the AAFG, BAFG bit. Output Relationships Between AAFG（BAFG）Bit and ⎯INTRA（⎯INTRB） AAFG(BAFG) INTRA(INTRB) AAFG(BAFG)=0 Time matche AAFG(BAFG)=0 Time matched BL5372 Data Sheet Time matched 13 Shanghai Belling Transmission System of Interface Communication protocol determines: circuits in the equipment which sends data through SDA bus are regarded as emitters, contrarily, circuits in the equipment which receives data through SDA bus are regarded as receivers. Master equipment and master circuit control data transmission; Slave circuit is controlled. Typical System Bus Structure VDD SDA SCL Master Emitter/ Receiver Slave Receiver Slave Emitter / Receiver Slave Receiver Master Emitter/ Receiver Data Validity Protocol Data transmission protocol determines: Transmit one bit data in every clock cycle. SDA must be kept at a certain state while SCL is at the “H” state as shown below during data transmission. Start and stop conditions The SCL and SDA pins are at the “H” level when no data transmission is made. Changing the SDA from “H” to “L” when the SCL and the SDA are “H” activates the start condition and access is started. Changing the SDA from “L” to “H” when the SCL is “H” activates stop condition and accessing stopped. Start and stop conditions As the arrival of the start condition, master emitter must send out an address command bit, which includes slave address and R/W model; When a certain receiver in bus is chosen, it will send ACK signal and SDA changes into low voltage. ACK signal indicates the success of data transmission. When SCL clock drops, emitter sends continuously 8 bits and releases the data bus (SDA changes into high voltage). 14 BL5372 Data Sheet Shanghai Belling The slave address The high effective 7 bits (bit7---bit1) in the address byte are defined as device type id. In BL5372, these 7 bits are 0110010. The lowest bit0 is defined as R/W model. When this bit is “1”, it is read model, while “0” is write model. The slave address BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 0 1 1 0 0 1 0 R/W BIT7—BIT1：The slave address of the BL5372 is defined as 0110010 BIT0： R/W definition “1” is read model “0” is write model Data transmission format in the Interface Communication Interface generates no Chip Enable signals. In place of it each device has a 7bit slave address allocated. The first 1byte is allocated to this 7bit of slave address and to the command (R/⎯W) for which data transmission direction is designated b the data transmission thereafter. The slave address of the BL5372 is specified at (0110010). At the end of data transmission/receiving stop condition is generated to complete transmission. However, if start condition is generated without generating stop condition, repeated start condition is met and transmission/receiving data may be continued by setting the slave address again. Use this procedures when the transmission direction needs t be changed during one transmission. Data is written into the slave from the master When data is read from the slave immediately after 7bit addressing from the master BL5372 Data Sheet 15 Shanghai Belling When the transmission direction is to be changed during transmission Data Transmission Write Format in the BL5372 A）First send 7 address bit(0110010), the eighth bit is write command “0”. B）When the ninth bit is ACK signal, BL5372 is under writing condition. C） In the following byte, the high 4 bits are determined as internal address in BL5372(0H-FH), the low 4 bits are transmission model. D） After another bit’s ACK signal, it starts writing data normally. E） After writing 1 byte data, there will be 1 bit ACK signal and then writing data in next 1 byte starts. Only when there is a stop signal in the bit after ACK signal, can the writing operation be stopped. Example of data writing (When writing to internal address 4H to 5H) Data Transmission Read Format in the BL5372 The BL5372 allows the following three readout methods of data from an internal register. Ⅰ）The first method to reading data from the named internal address A)The first three steps are the same as write model B) After one bit ACK signal, a new start signal will be produced to change the direction of data transmission in INTERFACE connection. C)Then send 7 address bit(0110010), the eighth bit command is “1”, BL5372 is under data reading condition. 16 BL5372 Data Sheet Shanghai Belling D) After another bit’s ACK signal, it starts reading data normally. E) When a byte data is read and CPU sends 1 bit ACK signal, a next byte data can be read. Only when the 1 bit ACK signal which is sent by CPU is high voltage, can the reading operation be stopped and then CPU sends stop signals. Example 1 of data read (when data is read from 7H to 9H) Ⅱ) The second method to reading data from the internal register is to start immediately after writing to the internal address pointer and the transmission format register. Set 4h to the transmission format register when this method is used. Example 2 of data read (when data is read from internal address Dh to 0h). BL5372 Data Sheet 17 Shanghai Belling Ⅲ) The third method to reading data from the internal register is to start reading immediately after writing to the slave address(0110010) and the (R/⎯W) bit. Since the internal address pointer is set to Fh by default , this method is only effective when reading is started from the internal address Fh. Example 3 of data read (when data is read from internal address Fh to 3h). Data Transmission Under Special Condition The BL5372 hold the clock tentatively for duration from start condition to stop condition to avoid invalid read or write clock on carrying clock. To prevent invalid read or write clock shall be made during one transmission operation. When 0.5 to 1.0 seconds elapses after start condition any access to the BL5372 is automatically released to release tentative hold of the clock and access from the CPU is forced to be terminated (automatic resume function from the interface). Also a second start condition after the first condition and before the stop condition is regarded as the “repeated start condition”. Therefore, when 0.5 to 1.0 seconds passed after the first start condition, access to the BL5372 is automatically released. The user shall always be able to access the real-time clock as long as the following two conditions are met. 1） No stop condition shall be generated until clock read/write is started and completed. 2） One cycle read/write operation shall be completed within 0.5 seconds. Bad example of reading from seconds to hours (invalid read) (Start condition) → (Read of seconds) → (Read of minutes) → (Stop condition) → (Start condition) → (Read of hour) → (Stop condition) Assuming read was started at 09:59:59PM, and while reading seconds and minutes the time advanced to 10:00:00 PM. At this time second digit is hold so the read as 59:59. BL5372 confirms (Stop condition) and carry second digit being hold and the time changes to 10:00:00 PM. Then, when the hour digit is read, it changes to 10. The wrong results of 10:59:59 will be read. 18 BL5372 Data Sheet Shanghai Belling Configuration of Oscillating Circuit and Time Trimming Circuit a) In general crystal oscillators are classified by their central frequency of CL (load capacitance) and available further grouped in several ranks as ±10， ±20 and ±50ppm of fluctuations in precision. b) c) The fluctuation of IC circuit frequency is ±5~10ppm at room temperature. Here, the clock accuracy at room temperature varies along with the variation of the characteristic of crystal oscillator. Configuration of Oscillating Circuit Because the adjustment of crystal oscillator frequency is also the adjustment of clock frequency, so the former adjustment can be done through CIN & COUT on the both sides of crystal. BL5372 clock cooperates with CIN & COUT, so oscillator frequency can be referred to crystal CL. General, relation between CL and CIN or COUT is as follows： Cl = Cin * Cout + Cs CS：Board floating capacitance Cin + Cout If crystal oscillator frequency is on the higher side, the CL should be decreased, contrarily, the CL should be increased. According to this standard, the best CL is chosen to adjust frequency and clock frequency. For example: if the frequency is on the higher side, it can be lowed by attaching a CGOUT capacitor. Capacitor should be connected with OSCOUT pin to adjust frequency . Oscillation halt will happen when capacitor is connected with OSCIN pin because OSCIN pin has no driving ability.(as shown below) BL5372 Data Sheet 19 Shanghai Belling Time Trimming Circuit Using the time trimming circuit gain or lose of clock may be adjusted with high precision by changing clock pulses for one second every 20 seconds. When oscillation frequency *1 > target frequency*2（clock gain） 1. Adjustment amount*3 = (OscilationFrequency − T arg etFrequency + 0.1) OscillationFrequency * 2 (T arg etFrequency * 20) = (Oscillation frequency – Target frequency) x 10 +1 *1) Oscillation frequency: Clock frequency output from the ⎯INTRB pin *2) Target frequency: TYP. 32.768KHz to 32.000KHz *3) Adjustment amount: A value to be set finally to F6 to F0 bits. This value is expressed in 7 bit binary digits with sign bit (two’s compliment). 2. When oscillation frequency = target frequency (no clock gain or loss) Set the adjustment value to 0 or +1, or –64, or –63 to disable adjustment. 3. When oscillation frequency < target frequency (clock losses) Adjustment amount = (OscilationFrequency − T arg etFrequency) OscillationFrequency * 2 (T arg etFrequency * 20) = (Oscillation frequency – Target frequency) x 10 Example of Calculations 1) When oscillation frequency = 32770kHz; target frequency = 32768kHz Adjustment value = （32770-32768+0.1）/(32770*2/(32768*20)) =(32770-32768)*10+1=21 Set （F6，F5，F4，F3，F2，F1，F0）=（0，0，1，0，1，0，1） 2) When oscillation frequency =32762kHz; target frequency = 32768kHz Adjustment value =（32762-32768）/(32762*2/(32768*20)) = (32762-32768)*10=-60 To express –60 in 7bi binary digits with sign bit ( two’s compliment) Subtract 60(3Ch) from 128(80h) in the above case, 80h-3Ch=44h Thus set （F6，F5，F4，F3，F2，F1，F0）=（1，0，0，0，1，0，0） After adjustment, adjustment error against the target frequency will the approx. ±1.5ppm at a room temperature. Notice: 1) Clock frequency output from the⎯INTRB pin will change after adjustment by the clock adjustment circuit. 20 BL5372 Data Sheet Shanghai Belling 2) Adjustment range: A)When oscillation frequency is higher than target frequency, the range of adjustment values is （F6，F5，F4，F3，F2，F1，F0）=（0，0，0，0，0，0，1）to (0，1，1，1，1，1，1) and actual adjustable amount shall be -3.05ppm to –189.2ppm (-3.125ppm to 193.7ppm for 32000Hz crystal). B) When oscillation frequency is lower than target frequency, the range of adjustment values is （F6，F5，F4，F3，F2，F1，F0）=（1，1，1，1，1，1，1）to（1，0，0，0，0，1，0） and actual adjustable amount shall be 3.05ppm to 189.2ppm (3.125ppm to 193.7ppm for 32000Hz crystal) Output Waveforms The following three output waveforms can be output from the ⎯INTRA (⎯INTRB) pin. 1）Alarm interrupt When a registered time for alarm (such as day-of-the-week, hour or minute) coincide with calendar counter (such as day-of-the-week, hour or minute) interrupt to the CPU are requested with the output pin being on “L”. Alarm interrupt consists of Alarm_A and Alarm_B, both have equivalent functions. 2）Periodic interrupt Outputs an output waveform selected by setting the periodic interrupt frequency select bit. Waveforms include pulse mode and level mode. 3）32KHz clock output Clock pulses generated in the oscillation circuit are output as they are. Control of the⎯INTRA (⎯INTRB) Output (flag bit, enable bit, interrupt output select bit) Of the three output wave forms listed above, interrupt output conditions may be set by setting the flag bit that monitors output state on the register, the enable bit that enables an output wave form and the output select bit that selects either ⎯INTRA or ⎯INTRB to be output. Flag bit Alarm_A Alarm_B Periodic interrupt 32KHz clock output AAFG (D1 at FH) BAFG (D0 at FH) CTFG (D2 at FH) NO Interrupt output select bit （SL2，SL1） (D5，D4 at EH) Enable bit AALE (D7 at EH) BALE (D6 at EH) Disabled at CT2=CT1=CT0=0 (D2 to D0 at EH) ⎯CLEN (D3 at FH) （0，0） （0，1） （1，0） （1，1） ⎯INTRA ⎯INTRA ⎯INTRA ⎯INTRA ⎯INTRA ⎯INTRA ⎯INTRB ⎯INTRB ⎯INTRB ⎯INTRB ⎯INTRB ⎯INTRB ⎯INTRA ⎯INTRB ⎯INTRA ⎯INTRB When power ON (XSTP=1) since AALE=BALE=CT2=CT1=CT0=⎯CLEN=SL2=SL1=0, ⎯INTRA=OFF (“H”) and 32KHz clock pulses are output from the ⎯INTRB pin. BL5372 Data Sheet 21 Shanghai Belling When more than one output waveforms are output from a single output pin, the output will have OR wave form of negative logic of both. ALARM-A ALARM-B INTRA Alarm Interrupt For setting an alarm time, designated time such as day-of-the-week, hour or minute should be set to the alarm registers being AALE（BALE）bit to 0. After that set the AALE（BALE） bit to 1, from this moment onward when such registered alarm time coincide the value of calendar counter the⎯INTRA (⎯INTRB) comes down to “L” (ON). The ⎯INTRA (⎯INTRB) output can be controlled by operating to the AALE (BALE) and AAFG (BAFG) bits. Periodic (Clock) Interrupt The ⎯INTRA (⎯INTRB) pin output, the periodic interrupt cycle select bits (CT2, CT1, CT0) and the interrupt output select bits (SL2, SL1) can be used to interrupt the CPU in a certain cycle. The periodic interrupt cycle select bits can be used to select either one of two interrupt output modes: the pulse mode and the level mode. 22 BL5372 Data Sheet Shanghai Belling CT2 0 0 0 0 1 1 1 1 CT1 0 0 1 1 0 0 1 1 CT0 0 1 0 1 0 1 0 1 Wave Form Mode Pulse Mode Pulse Mode Level Mode Level Mode Level Mode Level Mode Description Cycle and INTRA(INTRB) Falling Timing INTRA（INTRB）OFF (Default) INTRA（INTRB）fixed at “L” 2Hz (Duty 50%) 1Hz (Duty 50%) Every second (coincident with second count-up) Every minute (00 second of every minute) Every hour (00minute 00second of every hour) Every month (1st day, 00:00:00 a.m.of every month) 1） Pulse mode: Output 2Hz, 1Hz clock pulses. For relationships with counting up of seconds see the diagram below. In the 2Hz clock pulse mode, 0.496s clock pulses and 0.504s clock pulse are output alternatively. Duty cycle for 1Hz clock pulses becomes 50.4%. 2） Level mode: One second, one minute one month may be selected for an interrupt cycle. Counting up of seconds is matched with falling edge of interrupt output. 3） When the time trimming circuit is used, periodic interrupt cycle changes every 20 seconds. Pulse mode: “L” duration of output pulses may change in the maximum range of ±3.784ms (±3.875ms when 32KHz crystal is used) For example, Duty will be 50±0.3784% (or 50±0.3875% when 32KHz crystal is used) at 1Hz. Level mode: Frequency in one second may change in the maximum range of ±3.784ms (±3.875ms when 32KHz crystal is used). Relation Between Mode Waveforms and CRFG Bit Pulse mode Level mode BL5372 Data Sheet 23 Shanghai Belling 32Khz Clock Output The crystal oscillator can generate clock pulses of 32KHz from the ⎯INTRB pin. The pin is changed to “H” by setting the ⎯CLEN bit to “1”. 32KHz clock pulse output will not be affected from settings in the clock adjustment register. When power ON (XSTP=1), 32KHz clock pulses are output from the ⎯INTRB pin. Oscillator Halt Sensing Oscillation halt can be sensed through monitoring the XSTP bit with preceding setting of the XSTP bit to “0” by writing data to the control register 2.Upon oscillator halt sending, the XSTP bit is switched from 0 to 1. This function can be applied to judge clock data validity. When the XSTP bit is “1”, ⎯XSL, F6 to F0, CT2, CT1, CT0, AALE, BALE, SL2, SL1, ⎯CLEN and TEST bits are reset to “0”. *1）The XSTP bit is set to “1” upon power-on from 0V. Note that any instantaneous power disconnection may cause operation failure. *2）Once oscillation halt has been sensed, the XSTP bit is held at “1” even if oscillation is restarted. Ensure error-free oscillation half sensing by preventing the following events: 1） Instantaneous disconnection of VDD 2） Condensation on the crystal oscillator 3） Generation of noise on the PCB in the crystal oscillator 4） Application of voltage exceeding prescribed maximum ratings to the individual pins of the IC 24 BL5372 Data Sheet Shanghai Belling DC Characteristics TOPT=-40℃ to +85℃, GND=0V, VDD=3.6V, fOSC=32,768Hz or 32,000Hz Symbol Item Pin name Conditions MIN. VIH “H” Input SCL, SDA 0.8VDD Voltage VIL “L” Input SCL, SDA -0.3 Voltage IOL1 “L” Output INTRA, INTRB VOL1=0.4V 1 Current IOL2 SDA VOL2=0.6V 7 IILK Input Leakage SCL VI=6VorGND -1 Current VDD=6V VDD Operating VDD 1.8 Voltage GND Counting 1.8 Voltage IOZ Output Off SDA, INTRA, VO=6VorGND -1 State Leakage INTRB VDD=6V Current VDD=5V, IDD Standby VDD TOPT=25℃ Current SCL,SDA=5V AC Characteristics Characteristics Parameter TA= -40℃ to +85℃，VDD =4.5V to 5.5V Symbol Item SCL Clock Frequency fSCL SCL Clock “L” Time tLOW SCL Clock “H” Time tHIGH Bus release Time tBUF tSU:STA tSU:STO tHD:STA tHD:STO tSU:DAT tHD:DAT THD Start Condition Setup Time Stop Condition Setup Time Start Condition Hold Time Stop Condition Hold Time Data Setup Time Data input Hold Time Data output Hold Time tAA clock output tR tF tI Rising Time of SCL and SDA (Input) Falling Time of SCL and SDA (Input) Spike width that can be removed with input filter Conditions before next data is transmitted SCL negedge to SDA data changes SCL negedge to SDA data availed BL5372 Data Sheet TYP. MAX. 6.0 Unit V 0.3VDD V 1 mA mA uA 5.5 V 5.5 V 1 uA 0.4 MIN. 0 4.7 5 4.7 uA MAX. 100 4.7 4.7 4 4 250 0 0 0.3 Unit KHz us us us us us us us ns ns ns 3.5 us 1 300 100 us ns ns 25 Shanghai Belling Absolute Maximum Ratings Item Symbol VDD VI VO1 VO2 TOPT TSTG Supply Voltage Input Voltage Output Voltage 1 Output Voltage 2 Operating Temperature Storage Temperature Conditions Ratings Unit SCL，SDA SDA INTRA, INTRB -0.3 to +7.0 -0.3 to +7.0 -0.3 to +7.0 -0.3 to +12.0 -40 to +85 V V V V ℃ -55 to +125 ℃ 26 BL5372 Data Sheet Shanghai Belling TYPICAL APPLICATIONS Example of Circuit (B) VCC BATT D1 10u D0 0.1u C1 C0 INTRB SCL SDA GND 1. Mount the high-and low-frequency by-pass capacitors C0 and C1 (TYP. C1=10uF, C2=0.1uF) 10K R3 10K 10K 10K R2 R1 R0 1 2 3 4 8 7 6 5 VDD OSCIN OSCOUT INTRA 32768 CRYSTAL BL5372 (A) 10u C0 D0 10K 10K R2 R1 10K R0 0.1u C1 INTRB SCL SDA GND 10K R3 1 2 3 4 3.BATT and VCC’s Voltage: VBATT≤ VVCC 4. Connect the pull-up resistor of the INTRA pin or the INTRB pin to two different positions depending battery back-up: VCC BATT D1 2. The typical volume of pull-up resistance R0~R3 is 10KΩ 8 7 6 5 A、 when the spare battery supplies power, INTRA (B) is not used. VDD OSCIN OSCOUT INTRA 32768 CRYSTAL BL5372 B、 when the spare battery supplies power, INTRA (B) is used. Example of Interface Circuit to the CPU D1 10u C3 0.1u C4 D0 VCC BATT 10K R3 10u C0 VDD MCU 0.1u C1 10K 10K 10K R2 R1 R0 INTRB SCL SDA GND 1 2 3 4 8 7 6 5 VDD OSCIN OSCOUT INTRA 32768 CRYSTAL BL5372 BL5372 Data Sheet 27 Shanghai Belling PACKAGE DIMMENSIONS SOP8 Symbol A A1 B C D ddd E e H h L α Min 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 0o mm TYP. 1.27 - Max 1.75 0.25 0.51 0.25 5.00 0.10 4.00 6.20 0.50 0.90 8o 28 BL5372 Data Sheet Min 0.053 0.004 0.013 0.007 0.189 0.150 0.228 0.010 0.016 0o Inches TYP. 0.050 - Max 0.069 0.010 0.020 0.010 0.197 0.004 0.157 0.244 0.020 0.035 8o Shanghai Belling TSSOP8 DIMENSIONS(mm are the original dimensions) UNIT A A1 A2 A3 max. mm 1.10 0.15 0.95 0.25 0.05 0.80 UNIT mm HE 6.70 6.10 L 0.94 Lp 0.80 0.20 v 0.1 Bp C D(1) E(2) e 0.32 0.12 0.25 0.10 3.10 2.90 4.60 4.20 0.65 Z(1) 0.70 0.35 θ 100 00 w 0.1 y 0.1 Notes 1.Plastic or metal protrusions of 0.15mm maximum per side are not included 2.Plastic or metal protrusions of 0.25mm maximum per side are not included BL5372 Data Sheet 29 Shanghai Belling REVISION SUMMARY The contents of this document are provided in connection with Shanghai Belling, Inc. products. Shanghai Belling makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in Shanghai Belling's Standard Terms and Conditions of Sale, Shanghai Belling assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. Shanghai Belling's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of Shanghai Belling 's product could create a situation where personal injury, death, or severe property or environmental damage may occur. Shanghai Belling reserves the right to discontinue or make changes to its products at any time without notice. © 2003 Shanghai Belling, Inc. All rights reserved. 30 BL5372 Data Sheet