–20V, –3.1A, 155m: Features General Description Max rDS(on) = 155m: at VGS = –4.5V, ID = –3.1A This device is designed specifically as a single package solution for the battery charge switch in cellular handset and other ultra portable applications. It features two independent P-Channel MOSFETs with low on-state resistance for minimum conduction losses. When connected in the typical common source configuration, bi-directional current flow is possible. Max rDS(on) = 220m: at VGS = –2.5V, ID = –2.3A Low profile - 0.8mm maximum - in the new package MicroFET 2X2 mm RoHS Compliant The MicroFET 2X2 package offers exceptional thermal performance for its physical size and well suited to linear mode applications. Free from halogenated compounds and antimony oxides Application DC - DC Conversion PIN 1 D2 S1 1 1 6 G1 2 2 5 G2 D2 3 3 G1 4 S2 6 S1 D1 D2 G2 4 D1 5 D1 S2 MicroFET 2X2 MOSFET Maximum Ratings TA = 25°C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current -Continuous ID (Note 1a) TJ, TSTG Units V ±12 V –3.1 –6 -Pulsed PD Ratings –20 Power Dissipation for Single Operation (Note 1a) 1.4 Power Dissipation (Note 1b) 0.7 –55 to +150 Operating and Storage Junction Temperature Range A W °C Thermal Characteristics RTJA Thermal Resistance Single Operation, Junction to Ambient (Note 1a) 86 RTJA Thermal Resistance Single Operation, Junction to Ambient (Note 1b) 173 RTJA Thermal Resistance Dual Operation, Junction to Ambient (Note 1c) 69 RTJA Thermal Resistance Dual Operation, Junction to Ambient (Note 1d) 151 °C/W Package Marking and Ordering Information Device Marking 025 Device FDMA1025P ©2010 Fairchild Semiconductor Corporation FDMA1025P Rev.B5 Package MicroFET 2X2 1 Reel Size 7’’ Tape Width 8mm Quantity 3000 units www.fairchildsemi.com FDMA1025P Dual P-Channel PowerTrench® MOSFET July 2014 FDMA1025P Dual P-Channel PowerTrench® MOSFET Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = –250PA, VGS = 0V 'BVDSS 'TJ Breakdown Voltage Temperature Coefficient –20 ID = –250PA, referenced to 25°C IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current V 14 VDS = –16V, VGS = 0V mV/°C –1 –100 TJ = 125°C VGS = ±12V, VDS = 0V PA ±100 nA –1.5 V On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = –250PA 'VGS(th) 'TJ Gate to Source Threshold Voltage Temperature Coefficient ID = –250PA, referenced to 25°C rDS(on) Drain to Source On Resistance gFS Forward Transconductance –0.4 –0.9 –3.8 mV/°C VGS = –4.5V, ID = –3.1A 88 155 VGS = –2.5V, ID = –2.3A 144 220 VGS = –4.5V, ID = –3.1A,TJ = 125°C 121 220 VDS = –5V, ID = –3.1A 6.2 m: S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance VDS = –10V, VGS = 0V, f = 1MHz 340 450 pF 80 105 pF 45 70 pF FDMA1025P Dual P-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25°C unless otherwise noted Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg(TOT) Total Gate Charge at 4.5V Qgs Gate to Source Gate Charge Qgd Gate to Drain “Miller” Charge VDD = –10V, ID = –3.1A VGS = –4.5V, RGEN = 6: VGS = 0V to –4.5V V = –10V DD ID = –3.1A 5 10 ns 14 26 ns 13 24 ns 8 16 ns 3.4 4.8 nC 0.8 nC 1.0 nC Drain-Source Diode Characteristics IS Maximum Continuous Source-Drain Diode Forward VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge FDMA1025P Rev.B5 VGS = 0V, IS = –1.1A (Note 2) IF = –3.1A, di/dt = 100A/Ps 2 –0.8 –1.1 –1.2 A V 17 26 ns 10 15 nC www.fairchildsemi.com 1. RTJA is determined with the device mounted on a 1 in2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. RTJC is guaranteed by design while RTJA is determined by the user's board design. (a) RTJA = 86 °C/W when mounted on a 1 in2 pad of 2 oz copper, 1.5 " x 1.5 " x 0.062 " thick PCB. For single operation. (b) RTJA = 173 °C/W when mounted on a minimum pad of 2 oz copper. For single operation. (c) RTJA = 69 oC/W when mounted on a 1 in2 pad of 2 oz copper, 1.5 ” x 1.5 ” x 0.062 ” thick PCB. For dual operation. (d) RTJA = 151 oC/W when mounted on a minimum pad of 2 oz copper. For dual operation. a)86 oC/W when mounted on a 1 in2 pad of 2 oz copper. b)173 oC/W when mounted on a minimum pad of 2 oz copper. c)69 oC/W when mounted on a 1 in2 pad of 2 oz copper. d)151 oC/W when mounted on a minimum pad of 2 oz copper. 2. Pulse Test : Pulse Width < 300 us, Duty Cycle < 2.0 FDMA1025P Rev.B5 4 www.fairchildsemi.com FDMA1025P Dual P-Channel PowerTrench® MOSFET Notes: 5 6 VGS = -4.5V VGS = -3.5V 4 VGS = -2.5V 3 VGS = -1.8V 2 1 PULSE DURATION = 80Ps DUTY CYCLE = 0.5%MAX 0 0 1 2 -VDS, DRAIN TO SOURCE VOLTAGE (V) PULSE DURATION = 80Ps DUTY CYCLE = 0.5%MAX NORMALIZED DRAIN TO SOURCE ON-RESISTANCE -ID, DRAIN CURRENT (A) 5 4 VGS = -1.8V 3 VGS = -3.5V 1 VGS = -4.5V 0 3 0 ID =-3.1A VGS = -4.5V rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (oC) ID = -3.1A 300 TJ = 125oC 200 100 TJ = 25oC 3 TJ = 25oC 1 TJ = -55oC 1.5 2.0 2.5 4 5 6 Figure 4. On-Resistance vs Gate to Source Voltage 4 TJ = 150oC 3 -VGS, GATE TO SOURCE VOLTAGE (V) -IS, REVERSE DRAIN CURRENT (A) -ID, DRAIN CURRENT (A) PULSE DURATION = 80Ps DUTY CYCLE = 0.5%MAX 2 PULSE DURATION = 80Ps DUTY CYCLE = 0.5%MAX 3.0 -VGS, GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics FDMA1025P Rev.B5 6 400 150 6 0 1.0 5 0 -25 Figure 3. Normalized On Resistance vs Junction Temperature 2 2 3 4 -ID, DRAIN CURRENT(A) 500 1.6 5 1 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage SOURCE ON-RESISTANCE (m:) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE Figure 1. On Region Characteristics 0.6 -50 VGS = -2.5V 2 10 VGS = 0V 1 0.1 0.01 0.001 0.0001 0.0 TJ = 150oC TJ = 25oC TJ = -55oC 0.2 0.4 0.6 0.8 1.0 -VSD, BODY DIODE FORWARD VOLTAGE (V) 1.2 Figure 6. Source to Drain Diode Forward Voltage vs Source Current 4 www.fairchildsemi.com FDMA1025P Dual P-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25°C unless otherwise noted -VGS, GATE TO SOURCE VOLTAGE(V) 10 1000 ID = -3.1A Ciss VDD = -8V CAPACITANCE (pF) 8 VDD = -10V 6 VDD = -12V 4 2 0 0 2 4 6 Qg, GATE CHARGE(nC) Coss 100 Crss f = 1MHz VGS = 0V 10 0.1 8 Figure 7. Gate Charge Characteristics P(PK), PEAK TRANSIENT POWER (W) 20 -ID, DRAIN CURRENT (A) 100us 1ms SINGLE PULSE TJ = MAX RATED R 0.1 10ms 100ms o =173 C/W TJA 1s 10s DC TA = 25OC THIS AREA IS LIMITED BY rDS(on) 0.01 0.1 1 50 10 30 Figure 8. Capacitance vs Drain to Source Voltage 10 1 1 10 -VDS, DRAIN TO SOURCE VOLTAGE (V) 100 VGS = -4.5V FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 150 – T A -----------------------125 I = I25 10 TA = 25oC 1 SINGLE PULSE 0.6 -4 10 -3 -2 10 -1 0 1 2 10 10 10 10 t, PULSE WIDTH (s) -VDS, DRAIN to SOURCE VOLTAGE (V) 10 3 10 Figure 10. Single Pulse Maximum Power Dissipation Figure 9. Forward Bias Safe Operating Area 1 NORMALIZED THERMAL IMPEDANCE, ZTJA DUTY CYCLE-DESCENDING ORDER 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZTJA x RTJA + TA SINGLE PULSE 0.001 -4 10 -3 10 -2 -1 10 10 0 10 1 10 2 10 t, RECTANGULAR PULSE DURATION (s) Figure 11. Transient Thermal Response Curve FDMA1025P Rev.B5 5 www.fairchildsemi.com FDMA1025P Dual P-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25°C unless otherwise noted FDMA1025P Dual P-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/package/packageDetails.html?id=PN_MLDEB-X06 FDMA1025P Rev.B5 6 www.fairchildsemi.com tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. 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