POSEICO SPA Via Pillea 42-44, 16153 Genova - ITALY Tel. + 39 010 8599400 - Fax + 39 010 8682006 Sales Office: Tel. + 39 010 8599400 - Fax + 39 010 8681180 POSEICO POSEICO SPA POwer SEmiconductors Italian COrporation HIGH CURRENT PHASE CONTROL THYRISTOR INSULATED MODULE - Full hermetic packaging - Base plate insulation uisng AlN substrate - Industrial compatible packaging - Contract screws available on request AZT800 Repetitive voltage up to Mean on-state current Surge current 1800 V 800 A 30 kA FINAL SPECIFICATION lug 07 - ISSUE : 2 Symbol Characteristic Tj [°C] Conditions Value Unit BLOCKING V RRM / DRM Repetitive peak reverse/off-state voltage 125 1800 V RSM Non-repetitive peak reverse voltage 125 1900 RRM / DRM Repetitive peak reverse/off-state current 125 70 I V V mA CONDUCTING I T (AV) Mean on-state current 180° sin, 50Hz, Tc=85°C 800 A I T (AV) Mean on-state current 180° sin. 50Hz, Tc=55°C 1220 A I TSM Surge on-state current sine wave, 10 ms 30 kA I² t I² t without reverse voltage V T On-state voltage On-state current = V T(TO) T r 125 4500 x1E3 1800 A A²s 25 1,34 V Threshold voltage 125 0,82 V On-state slope resistance 125 0,180 mohm SWITCHING di/dt Critical rate of rise of on-state current, min. From 75% VDRM up to 1050 A, gate 10V 5 ohm 125 200 A/µs dv/dt Critical rate of rise of off-state voltage, min. Linear ramp up to 70% of VDRM 125 500 V/µs 25 td Gate controlled delay time, typical VD = 100V, gate source 25 V, 10 ohm , tr = 0.5 µs tq Circuit commutated turn-off time, typical dV/dt = 20 V/µs linear up to 75% VDRM Q rr Reverse recovery charge di/dt = -20 A/µs, I = 700 A 3 250 125 µs µs µC I rr Peak reverse recovery current VR = 50 V I H Holding current, typical VD = 5V, gate open circuit 25 300 mA A I L Latching current, typical VD = 5 V, tp = 30 µs 25 700 mA VD = 5 V 25 3,5 V mA GATE V GT Gate trigger voltage I GT Gate trigger current VD = 5 V 25 300 V GD Non-trigger gate voltage, min. VD = VDRM 125 0,25 V V FGM Peak gate voltage (forward) 30 V I FGM Peak gate current 10 A V RGM Peak gate voltage (reverse) P GM Peak gate power dissipation P G Average gate power dissipation Pulse width 100 µs 5 V 150 W 2 W MOUNTING R th(j-c) Thermal impedance, DC Junction to case R th(c-h) Thermal impedance Case to heatsink T j Operating junction temperature V ins RMS insulation voltage 50Hz, circuit to base,all terminal shorted Mounting tourque Case to heatsink T Busbars to terminals Mass ORDERING INFORMATION : AZT800 S 18 standard specification VDRM&VRRM/100 25 42 °C/kW 10 °C/kW -30 / 125 °C 4500 V 4 to 6 Nm 12 to 18 2800 Nm g HIGH CURRENT PHASE CONTROL THYRISTOR INSULATED MODULE AZT800 FINAL SPECIFICATION POSEICO POSEICO SPA POwer SEmiconductors Italian COrporation lug 07 - ISSUE : 2 SURGE CHARACTERISTIC Tj = 125 °C 3000 35 2500 30 25 2000 ITSM [kA] On-state Current [A] ON-STATE CHARACTERISTIC Tj = 125 °C 1500 20 15 1000 10 500 5 0 0 0 0,5 1 1,5 1 10 On-state Voltage [V] 100 n°cycles TRANSIENT THERMAL IMPEDANCE 177 90 K G G-K Terminali A 2.8x0.8 40,0 35,0 104 70 Ø6 .5 1 2 20,0 70 46 58 3 Ø1 25,0 30 Zth j-c [°C/kW] 30,0 V5 80 92 15,0 10,0 5,0 K 0,0 0,001 0,01 0,1 1 10 2 G t[s] Distributed by All the characteristics given in this data sheet are guaranteed only with uniform clamping force, cleaned and lubricated heatsink, surfaces with flatness < .03 mm and roughness < 2 µm. In the interest of product improvement POSEICO SPA reserves the right to change any data given in this data sheet at any time without previous notice. If not stated otherwise the maximum value of ratings (simbols over shaded background) and characteristics is reported. 1 79.5 4 45,0