200320A.pdf

APPLICATION NOTE
APN1010: A VCO Design for WLAN Applications in the
2.4–2.5 GHz ISM Band
Introduction
The increased demand for mobile network connections has led
to the establishment of RF interface standards for Wireless Local
Area Networks (WLANs). The unlicensed ISM frequency band,
2.4–2.5 GHz, has been designated for WLAN usage. Table 11
displays frequency allocations in different parts of the world for
WLAN. In the US, IEEE 802.11 specifies two RF physical layer
interfaces for WLAN, Direct Sequence Spread Spectrum (DSSS),
and Frequency Hopped Spread Spectrum (FHSS).
DSSS uses an 11-bit Barker code where each bit of information
is spread within a single channel. The IEEE standard allocates 11
channels, each 22 MHz wide, with 5 MHz spacing between
center frequencies in the 83.5 MHz band. This creates channels
whose frequencies overlap.
Region
Allocated Spectrum (GHz)
US, Europe
2.4–2.4835
Japan
2.471–2.497
France
2.4465–2.4835
Spain
2.445–2.475
SMP1322-017
In the typical DSSS interface architecture, shown in Figure 1, the
RF signal passes through an antenna diversity switch (this switch
may be designed using the common cathode SMP1320-074 PIN
diode). The signal passes through a bandpass filter and a T/R
switch (this switch may be designed using the PIN diodes
SMP1320-079 and SMP1322-0173). In the down/up converter IC,
Intersil HFA3683, the RF signal is converted to an IF of 374 MHz.
The IF signal enters a second down/up converter, Intersil
HFA3783, and is further converted to/from the baseband IC
input/output interface range. This architecture uses external VCOs
for the RF and IF local oscillators. In the selected frequency plan,
the RF VCO operational range is 2.06–2.1095 MHz and the IF
VCO operates at 748 MHz fixed frequency.
This application note describes the design of RF and IF VCOs for
a 2.4–2.4835 GHz WLAN application. It is based on the frequency
plan described above. Although this design addresses a particular
RF system outline, this example may be applied to most
WLAN systems.
Table 1. Global Spectrum Allocation at 2.4 GHz1
2.4–2.4835 GHz
With FHSS, there are 75 channels, each 1 MHz wide. The transmitter and receiver follow a predetermined frequency-hopping
sequence at least once every 400 ms. The frequency-hopping
sequences have been arranged to spread the power evenly
across the ISM band.
2.4–2.4835 GHz
HFA3783
374 ± 11 MHz
HFA3683
SMP1320-079
SMP1320-074
Ant. Select
PLL
PLL
Base
Band
Processor
0/90°
MAC
T/R
RF VCO
2.026–2.1095 GHz
IF VCO
748 MHz
TM
Figure 1. Typical WLAN RF Interface Architecture Based on Intersil Prism Chip Set2
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APPLICATION NOTE • APN1010
VCO Specifications
In the frequency plan shown in Figure 1, the RF VCO frequency
range is 2.026–2.1095 GHz. In reality, the tuning range of the
specific VCO design should be stretched to accommodate conditions that would affect frequency. These factors include
temperature variations, component value variations, aging, and
humidity. Table 2 shows how the tuning range needs to be
expanded to meet these conditions. We assume that the VCO has
a +0.1%/10°C temperature sensitivity, which is typical for
uncompensated RF VCO designs.
Tuning Range (GHz)
Range Description
Margin %
Operational
Temperature
(+15°C to + 85°C)
+0.7
Min.
Max.
2.026
2.1095
2.026
2.1243
Components Variations
±2.3
1.979
2.1732
Aging and Other
±0.5
1.969
2.1841
Table 2. RF VCO Tuning Range Margins
In this design, there is no frequency trimming allowed after
mounting. Therefore, the tuning range will be extended to cover
deviations resulting from component value variations. For inductors and capacitors with a ±5% tolerance the worst case of
±2.3% frequency variation may result. Including aging and other
factors, a ±0.5% final tuning range will be from 1.969–2.184
GHz, or 215 MHz.
Parameter
Frequency Range (GHz)
Test
Conditions
RF VCO
IF VCO
VCTL
0.5 V
2.5 V
1.969 GHz
2.184 GHz
0.726 GHz
0.770 GHz
108
22
3
3
Tuning Sensitivity (MHz/V)
Supply Voltage (V)
Supply Current (mA)
15
10
Control Voltage (V)
VCTL
0.5–2.5
0.5–2.5
Output Power (dBm)
POUT
-3
-8
2
2
Pushing Figure (MHz/V)
Pulling Figure (MHz)
VSWR = 2
For All Phases
1
1
Phase Noise (dBc/Hz)
@ 10 kHz
-90
-90
Similar considerations lead to an extension of the IF VCO range
of 748 MHz, ±3.2%, (724–772 MHz) resulting in a 48 MHz
tuning range.
The RF and IF VCO performance also depends on the characteristics of the specific RF IC chip-set used. Table 3 lists typical
performance objectives for the RF and IF VCO.
VCO Design Considerations
An important consideration for the VCO and other RF components
integrated on the same PCB is the ability to cover the frequency
range with no trimming. Non-trimmed VCOs are particularly
sensitive to variations of the component values and PCB material
characteristics. In addition, VCOs operating at oscillation
frequencies greater than 1 GHz are even more sensitive to
these variations.
For this reason, this design employs a frequency-doubling
scheme to achieve an RF VCO between 1.969–2.1841 GHz. The
fundamental frequency of the RF VCO architecture, in Figure 2,
operates at 0.9845–1.092 GHz, half the output frequency. This
signal is fed to a multiplier/buffer transistor, whose output circuit
is tuned to the second harmonic, 1.969–2.184 GHz.
An important benefit of frequency doubling is its inherent high
level of load isolation, reducing the VCO buffer amplifier’s complexity. However, the presence of the fundamental component in
the output spectrum may require some filter circuitry at the multiplier output to prevent PLL counter errors.
The fundamental RF VCO was designed using traditional Colpitts
circuit procedures. Similarly, the IF VCO is also a traditional
design using a separate Colpitts VCO and buffer transistor, both
operating in the same frequency range of 0.726–0.770 GHz.
Table 3. Typical RF/IF VCO Performance
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APPLICATION NOTE • APN1010
VCO Transistor
Buffer Transistor
Frequency Doubler Transistor
X2
VCTL
0.9845–1.092 GHz
0.9845–1.092 GHz
1.969–2.184 GHz
0.9845–1.092 GHz
Figure 2. RF VCO Block Diagram
Colpitts VCO Fundamentals
The fundamental Colpitts VCO operation is illustrated in Figures
3a and 3b.
Figure 3a shows a Colpitts VCO circuit the way it is usually implemented on a PCB. Figure 3b reconfigures the same circuit as a
common emitter amplifier with parallel feedback. The transistor
junction and package capacitors, CEB, CCB and CCE, are shown
separated from the transistor parasitic components to demonstrate their direct effect on the VCO tank circuit.
VCC
CCB
CSER
CCE
CVCC
CDIV1
LRES
POUT
CEB
CVAR
CDIV2
RL
Figure 3a. Basic Colpitts VCO Configuration
In an actual low-noise VCO circuit, the capacitor we noted as
CVAR may have a more complicated structure. It would include
series and parallel connected discrete capacitors used to set the
oscillation frequency and tuning sensitivity. The parallel resonator
(or simply resonator) consists of the parallel connection of the
resonator inductance, LRES, and the varactor capacitive branch,
CVAR. A fundamental property of the parallel resonator in a
Colpitts VCO is its inductive impedance at the oscillation
frequency. This means that its parallel resonant frequency is
always higher than the oscillation frequency.
At parallel resonance in the resonator branch, its impedance in
the feedback loop is high, acting like a stop band filter. Thus, the
closer the oscillation frequency to the parallel resonant frequency,
the higher the loss introduced into the feedback path. However,
since more reactive energy is stored in the parallel resonator
closer to the resonant frequency, a higher Q-loaded (QL) will be
achieved. Obviously, low-loss resonators, such as crystal or
dielectric resonators, allow closer and lower loss oscillation
buildup at parallel resonance in comparison to microstrip or
discrete inductor-based resonators.
The proximity of the parallel resonance to the oscillation
frequency may be effectively established by the CSER capacitance
value. Indeed, if the capacitance of the CSER is reduced, the
parallel resonator will have higher inductance to compensate
for the increased capacitive reactance. This means that the
oscillation frequency will move closer to parallel resonance
resulting in higher QL and higher feedback loss.
The Leeson equation establishing connection between tank
circuit QL and its losses states:
CCB
CSER
CEB
CVCC
LRES
CVAR
CDIV1
CDIV2
ξ? ( f m ) =
FkT
2P
1+
f
2
4Q L2 f m2
CCE
RL
Figure 3b. Common Emitter View of the Colpitts VCO
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APPLICATION NOTE • APN1010
Where F is the large-signal noise figure of the amplifier, P is loop or
feedback power (measured at the input of the transistor), and QL is
loaded Q. These three parameters have significant consequence for
phase noise in an actual low-noise RF VCO. In designing a low noise
VCO, we need to define the condition for minimum F and maximum
P and QL.
This discussion shows that loop power and QL are contradictory
parameters. That is, an increase in QL leads to more loss in the
feedback path resulting in lower loop power. The condition for
optimum noise figure is also contrary to maximum loop power
and largely depends on the specific transistor used. The best
noise performance is usually achieved with a high gain transistor
whose maximum gain coincides with minimum noise at large
signals. Since there are no such specifications currently available
for standard industry transistors, we can base the transistor
choice only on experience.
The RF VCO Model
The RF VCO model is shown in Figures 4a and 4b. Some component values, defined as variables, are listed in the “Var_Eqn”
column in Figure 4b. In the VCO resonator model, in Figure 4a,
the SMV1763-079 varactor model is described as a resistor and
inductor, SRL4, connected in series, and capacitor C9 and diode
SMV1763 are connected in parallel. The varactor choice was
based on the VCO frequency coverage and the requirement for
low phase noise. The resonator inductor, LRES, is described as a
series RL network SRL1 with parallel capacitor C4. Parallel
capacitor C4 is modeled with its parasitic series inductance and
resistance in the SRLC1 series network. Two series capacitors,
CSER and CSER2, are also modeled as SRLC series networks, X4
and XRLC4, respectively. Transmission line TL2 models the physical connection of the resonator with the base of the VCO
transistor X2 (Figure 4b).
Figure 4a. The RF VCO Resonator Model
In the RF VCO circuit model, shown in Figure 4b, transistors, X2
and X4, are connected in DC cascode sharing the base bias network consisting of R4 (RDIV1), R1 (RDIV2) and R2. The bias resistor
values were designed to evenly distribute the DC voltages
between X2 and X4. The emitter bias resistor, RL1, was chosen at
the low value of 100 Ω to minimize the DC voltage drop. The 60
nH inductance in series with RL1 in the network SRL1 enhances
the RF-to-ground impedance at the emitter terminal. At RF frequencies, X4 operates as a common emitter amplifier with the
emitter grounded through parallel capacitor network
SRLC1–SRLC3. The efficiency of the circuit suppresses the fundamental component and enhances the second harmonic at the
output of X4 and is critical to the design of that network. The
inductors L3, L2 and the parasitic inductances in SRLC1 and
SRLC3 are crucial parts of the design.
Figure 4b. The RF VCO Circuit Model
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APPLICATION NOTE • APN1010
The details of the SRLC1–SRLC3 network layout in the VCO
design are shown in Figure 5. The circuit model values
appearing in the model were optimized to fit the circuit’s
performance. Some inductors in the model look different from
the layout and are attributed to the imperfection of the circuit
component models.
The output circuit of transistor, X4, consists of transmission line
TL2 and coupling capacitor SLC3. This output circuit is tuned
to the second harmonic of the oscillation frequency. The buffer
transistor X3 operates at the second harmonic as an ordinary
common-emitter amplifier with about 10 mA DC current for
high gain.
In the test bench in Figure 6, the loop gain Ku = VOUT/VIN is
defined as the ratio of voltage phasors at the input and output
ports of an OSCTEST component. Defining the oscillation point is
a technique to balance the input (loop) power in order to provide
zero gain for zero loop phase shift. Once the oscillation point is
defined, the frequency and output power may be measured.
We do not recommend the use of the OSCTEST2 component
for closed loop analysis, since it may not converge and does not
allow clear insight to VCO behavior.
Figure 5. SRLC1-SRLC3 Network Layout Details
Figure 6. The RF VCO Test Bench for Open Loop Oscillator Analysis Using OSCTEST Coupler from Libra IV Library
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APPLICATION NOTE • APN1010
The IF VCO Model
The IF VCO model is shown in Figures 7a and 7b. Some component
values, defined as variables, are listed in the “Var_Eqn” column in
Figure 7b. In the resonator model Figure 7a, the SMV1763-079
varactor model is described with resistor and inductor, SRL4, connected in series, and capacitor C9 and diode SMV1763 connected
in parallel. For this narrow-band application, many varactors,
abrupt and hyperabrupt, work well; however the low resistance
and the hyperabrupt characteristic of the SMV1763-079 help
improve tuning linearity and phase noise. The resonator inductor,
LRES, is described as a series RL network, SRL1, with parallel
capacitor C4. The parallel capacitor is modeled with its parasitic
series inductance and resistance in the SRLC1 series network. Two
series capacitors, CSER and CSER2, are also modeled as SRLC series
networks, X4 and XRLC4 respectively. Transmission line, TL2,
models the physical connection of the resonator with the base of
the VCO transistor, X2, in Figure 7b.
In the IF VCO circuit model, in Figure 7b, transistors X2 and X4 are
DC biased separately to independently optimize the performance
of the VCO and buffer transistors. The emitter bias resistor, RL1,
was chosen as low as 130 Ω to achieve current/performance
balance in the VCO transistor. The overall current from the 3 V DC
bias was set at approximately 10 mA, which is adequate to provide sufficient power with good phase noise performance.
The VCO output signal is fed from collector resistor R2, shown in
the base of common-emitter amplifier buffer stage X3. The output
circuit of the buffer stage consists of parallel-connected inductor,
SRL1, capacitor, SLC2, and coupling capacitor, SRLC1. The collector inductance is modeled as a lossy inductance with 0.6 Ω
series resistance in parallel with parasitic capacitor, C5.
Transmission line, TL1, is an essential contributor to VCO performance, as a part of the load/tank circuitry. Referring to Figure
3b, RL (the VCO active load) shown as R2 in Figure 7b, could be
interpreted as series impedance between the collector of the VCO
transistor and capacitor CVCC. Transmission line, TL1, in Figure
7b, may be considered an inductor in series with that load. The
buffer input circuit then becomes parallel to both R2 and TL1 (in
Figure 7b). The effective inductance of TL1 improves the input
match of the buffer stage and increases the output power level;
however this will also increase the load on the VCO feedback
power, which may lead to phase noise degradation.
The test bench was identical to Figure 6 (RF VCO), which was
defined for open loop analysis with the OSCTEST component above.
Figure 7a. IF VCO Resonator Model
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APPLICATION NOTE • APN1010
Figure 7b. IF VCO Circuit Model
SMV1763-079 SPICE Model
The SPICE model for the SMV1763-079 varactor diode, defined
for the Libra IV environment, is shown in Figure 8 with a description of the parameters employed.
SMV1763-079 is a low series resistance, hyperabrupt junction
varactor diode. It is packaged in the small footprint, SC-79 plastic
package with a body size of 47 x 31 x 24 mils (total length with
leads is 62 mils).
PORT
P_anode
port – 1
IND
LS
L = 1.10
RES
Rs
R = 0.60
DIODE
DIOD3
AREA = 1
MODEL = amv1763
MODE = nonlinear
CAP
Cpo
C = 1.60
DIODEM
smv1763
IS = 1.00e-014
RS = 0
N=1
TT = 0
CJO = 7.60e-012
VJ = 120
M = 90
EG = 1.11
XTI= 3
KF =0
AF =1
FC = 0.50
BV= 0
IBV = 1.00e-003
ISR – 0
NR = 2
IKF = 0
NBV = 1
IBVL = 0
NBVL = 1
TBV1 = 0
TNOM = 27
FFE = 1
PORT
P_cathode
port = 2
Figure 8. SMV1763-079 SPICE Model for Libra IV
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APPLICATION NOTE • APN1010
Table 4 describes the model parameters. It shows default values
appropriate for silicon varactor diodes that may be used by the
Libra IV simulator.
Parameter
Unit
Default
IS
Saturation current (with N, determine the DC characteristics of the diode)
Description
A
1e-14
RS
Series resistance
Ω
0
N
Emission coefficient (with IS, determines the DC characteristics of the diode)
-
1
TT
Transit time
S
0
CJO
Zero-bias junction capacitance (with VJ and M define nonlinear junction capacitance of the diode)
F
0
VJ
Junction potential (with VJ and M define nonlinear junction capacitance of the diode)
V
1
M
Grading coefficient (with VJ and M define nonlinear junction capacitance of the diode)
-
0.5
EG
Energy gap (with XTI, helps define the dependence of IS on temperature)
EV
1.11
XTI
Saturation current temperature exponent (with EG, helps define the dependence
of IS on temperature)
-
3
KF
Flicker noise coefficient
-
0
AF
Flicker noise exponent
-
1
FC
Forward-bias depletion capacitance coefficient
-
0.5
BV
Reverse breakdown voltage
V
Infinity
IBV
Current at reverse breakdown voltage
A
1e-3
ISR
Recombination current parameter
A
0
NR
Emission coefficient for ISR
-
2
IKF
High injection knee current
A
Infinity
NBV
Reverse breakdown ideality factor
-
1
IBVL
Low-level reverse breakdown knee current
A
0
NBVL
Low-level reverse breakdown ideality factor
-
1
TNOM
Nominal ambient temperature at which these model parameters were derived
°C
27
FFE
Flicker noise frequency exponent
-
1
Table 4. Silicon Diode Default Values in Libra IV
According to the SPICE model, the varactor capacitor, CV, is a
function of the applied reverse DC voltage, VR, and may be
expressed as follows:
CV =
C JO
1+
VR
VJ
M
+C
This equation is a mathematical expression of the capacitance
characteristic. The model is most accurate for abrupt junction
varactors (like the SMV1408). For hyperabrupt junction varactors,
the model is less accurate because the coefficients are dependent on the applied voltage. To make this equation work better
for hyperabrupt varactors, the coefficients were optimized for the
best capacitance vs. voltage fit as shown in Table 2.
Note that in the Libra model in Figure 8, CP is given in
picoFarads, while CGO is given in farads to comply with the
default unit system used in Libra.
Part Number
CJO (pF)
M
VJ (V)
CP (pF)
Ω)
RS (Ω
LS (nH)
SMV1763-079
7.6
90
120
1.6
0.6
1.1
Table 5. SPICE Parameters for SMV1763-079
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APPLICATION NOTE • APN1010
RF VCO Design, Materials and Layout
The PCB layout is shown in Figure 10. The board is made of standard 10 mil thick FR4 material. The passive components on the
board have 0402 footprints. The bill of materials is shown in
Table 6.
The RF VCO circuit diagram is shown in Figure 9. The circuit is
powered by a 3 V voltage source. The ICC current was established
near 20 mA. The RF output signal is coupled from the VCO
through capacitor C13 (1 pF).
VCTL: 0.5–2.5 V
C1
100 pF
C7
560 pF
R3
270
V2
NE68019
D1
SMV1763-079
C4
1.8 pF
R1
2.4 k
L3
8 x 0.15 mm
VCC: +3 V
20 mA
R7
3k
D1
R2
8.2 k
L2
3.9 nH
C3
1p
POUT
V1
NE68519
C13
1p
C6
3.6 p
R5
5.6 k
C8
2p
C5
6p
C12
560 p
R4
100
L5
68 nH
C14
560 p
V3
NE68019
C11
1.2 p
C2
5 pF
L4
8 x 0.15 mm
C9
100 p
C10
7p
R6
100
Figure 9. RF VCO Schematic
Figure 10. RF VCO PCB
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200320 Rev. A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • July 21, 2005
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APPLICATION NOTE • APN1010
Designator
Value
Part Number
Footprint
C1
100 pF
0402AU101KAT
0402
AVX
Manufacturer
C2
5 pF
0402AU5R0JAT
0402
AVX
C3
1 pF
0402AU1R0JAT
0402
AVX
C4
1.8 pF
0402AU1R8JAT
0402
AVX
C5
6 pF
0402AU6R0JAT
0402
AVX
AVX
C6
3.6 pF
0402AU3R6JAT
0402
C7
560 pF
0402AU561KAT
0402
AVX
C8
2 pF
0402AU2R0JAT
0402
AVX
C9
100 pF
0402AU101KAT
0402
AVX
C10
7 pF
0402AU7R0KAT
0402
AVX
C11
1.2 pF
0402AU1R2KAT
0402
AVX
C12
560 pF
0402AU561KAT
0402
AVX
C13
1 pF
0402AU1R0KAT
0402
AVX
C14
560 pF
0402AU561KAT
0402
AVX
D1
SMV1763-079
SMV1763-079
SC-79
Skyworks Solutions
R1
2.4 k
CR10-242J-T
0402
AVX/KYOCERA
R2
8.2 k
CR10-822J-T
0402
AVX/KYOCERA
R3
270
CR10-271J-T
0402
AVX/KYOCERA
R4
100
CR10-101J-T
0402
AVX/KYOCERA
R5
5.6 k
CR10-562J-T
0402
AVX/KYOCERA
R6
100
CR10-101J-T
0402
AVX/KYOCERA
R7
3k
CR10-302J-T
0402
AVX/KYOCERA
L1
22 nH
LL1005-FH22NK
0402
TOKO
COILCRAFT
L2
3.9 nH
0402CS-3N9XJB
0402
L3
8 x 0.11 mm
MSL(Meander Line)
8 x 0.11mm
L4
8 x 0.11 mm
MSL(Meander Line)
8 x 0.11mm
L5
68 nH
HI1608-1B68N_N_K
0603
V1
NE68119
NE68119
SOT-416
NEC/CEL
V2
NE68619
NE68619
SOT-416
NEC/CEL
V2
NE68619
NE68619
SOT-416
NEC/CEL
ACX (Taiwan)
Table 6. Bill of Materials for RF VCO
IF VCO Design, Materials and Layout
The IF VCO circuit diagram is shown in Figure 11. This circuit is
also powered by a 3 V voltage source. The ICC current was established near 9 mA. The RF output signal is coupled from the VCO
through capacitor C11 (3 pF).
The PCB layout is shown in Figure 12. The board is made using
standard 10 mil thick FR4 material. Passive components on the
board have 0402 footprints. The bill of materials is shown in
Table 7.
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APPLICATION NOTE • APN1010
VCTL: 0.5–2.5 V
VCC: +3 V
9 mA
TL1
8 x 0.1 mm
C1
100 pF
R1
3k
D1
SMV1763-079
R3
20
R5
3k
C7
100 pF
L3
10 nH
V2
NE68019
V1
NE68119
C4
2.7 pF
L1
49 nH
C2
4 pF
C8
3p
C3
2.7 p
D1
R2
3k
L2
6.8 nH
C5
4p
C6
3p
C11
3p
C10
2p
R6
3k
R4
120
C9
100 p
R7
200
Figure 11. IF VCO Schematic
Figure 12. IF VCO PCB
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200320 Rev. A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • July 21, 2005
11
APPLICATION NOTE • APN1010
Designator
Value
Part Number
Footprint
Manufacturer
C1
100 pF
0402AU101KAT
0402
AVX
C2
4 pF
0402AU4R0JAT
0402
AVX
C3
2.7 pF
0402AU2R7JAT
0402
AVX
C4
2.7 pF
0402AU2R7JAT
0402
AVX
C5
4 pF
0402AU4R0JAT
0402
AVX
AVX
C6
3 pF
0402AU3R0JAT
0402
C7
560 pF
0402AU561KAT
0402
AVX
C8
3 pF
0402AU3R0JAT
0402
AVX
C9
100 pF
0402AU101KAT
0402
AVX
C10
2 pF
0402AU2R0KAT
0402
AVX
C11
3 pF
0402AU3R0JAT
0402
AVX
D1
SMV1763-079
SMV1763-079
SC-79
Skyworks Solutions
R1
3k
CR10-302J-T
0402
AVX/KYOCERA
R2
3k
CR10-302J-T
0402
AVX/KYOCERA
R3
20
CR10-200J-T
0402
AVX/KYOCERA
R4
130
CR10-131J-T
0402
AVX/KYOCERA
R5
3k
CR10-302J-T
0402
AVX/KYOCERA
R6
3k
CR10-302J-T
0402
AVX/KYOCERA
R7
200
CR10-201J-T
0402
AVX/KYOCERA
L1
56 nH
0402CS-56NXJB
0402
COILCRAFT
L2
6.8 nH
0402CS-6N8XJB
0402
COILCRAFT
L3
10 nH
0402CS-10NXJB
0402
V1
NE68119
NE68119
SOT-416
NEC/CEL
COILCRAFT
V2
NE68019
NE68019
SOT-416
NEC/CEL
Table 7. IF VCO Bill of Materials
RF VCO: Measurement and Simulation Results
P2 out simu.
0
Frequency (GHz)
2.25
-10
2.15
Fosc simu.
P1 out simu.
2.05
-20
-30
1.95
-40
1.85
0
0.5
1.0
1.5
2.0
2.5
3.0
Control Voltage (V)
Fosc meas.
P2 out meas.
P1 out meas.
Figure 13. RF VCO Tuning Response
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July 21, 2005 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • 200320 Rev. A
Output Power (dBm)
The measured performance of this circuit and the simulated results
obtained from the model are shown in Figures 13 and 14. Phase
noise measurements are shown in Figure 15, showing better than
-91 dBc/Hz at 10 kHz offset and better than -111 dBc/Hz at 100 kHz
offset. This 20 dB/decade slope is constant to below 10 MHz.
10
2.35
APPLICATION NOTE • APN1010
Because of frequency doubling, phase noise at the fundamental
frequency should be 6 dB better at the far offset. The doubled
frequency phase response, shown in Figure 15, gradually
diverges from the fundamental frequency as the offset frequency
increases with the phase noise difference close to the ideal value
of 6 dB. The measurements were performed using an Aeroflex
PN9000 Phase Noise Test Set with a 100 ns delay-line.
The measured frequency tuning response, in Figure 13, shows
near linear, 145 MHz/V, tuning sensitivity in the 0.5–2.5 V range
typical for battery applications. The simulated frequency tuning
response is similar to the measured response. The VCO output
2.10
The DC supply pushing response is shown in Figure 14. It shows
a distinct change of frequency vs. supply voltage, which is probably a result of the dominant VCO emitter-base capacitance.
Table 8 summarizes the data measured for RF and IF VCOs.
0
Parameter
P2 out meas.
-3
2.09
Fosc meas.
2.08
-6
-9
2.07
1.5
Output Power (dBm)
Frequency (GHz)
power vs. tuning voltage shows a 2–4 dB divergence between
measurement and simulation. This may be attributed to an inaccuracy in the VCO model parameters, especially to the transistor
model parameters. These models are derived for small-signal
amplifier applications and may not accurately reflect the higher
degree of nonlinearity of a VCO.
Frequency Range (GHz)
Test
Conditions
RF VCO
IF VCO
VCTL
0.5 V
2.5 V
1.93 GHz
2.22 GHz
0.720 GHz
0.765 GHz
145
22
Tuning Sensitivity (MHz/V)
Supply Voltage (V)
3
3
Supply Current (mA)
20
10
Control Voltage (V)
VCTL
0.5–2.5
0.5–2.5
Output Power (dBm)
POUT
0 ±2
-8
10
5
VCC Voltage (V)
Pulling Figure (MHz)
VSWR = 2
For All Phases
-
-
Figure 14. RF VCO Pushing Response
Phase Noise (dBc/Hz)
@ 10 kHz
-91
-94
2.0
2.5
3.0
3.5
4.0
Pushing Figure (MHz/V)
Table 8. Measured RF/IF VCO Performances
Figure 15. RF VCO Phase Noise at VCTL = 1.5 V and VCC = 3 V
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200320 Rev. A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • July 21, 2005
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APPLICATION NOTE • APN1010
IF VCO: Measurement and Simulation Results
The measured performance and simulated results of the IF VCO
are shown in Figures 16 and 17. Phase noise measurements,
shown in Figure 18, demonstrate better than -94 dBc/Hz at 10
kHz offset and better than -114 dBc/Hz at 100 kHz offset. This 20
dB/decade slope is constant to below 10 MHz. As with the RF
VCO, these measurements were performed with the Aeroflex
PN9000 Phase Noise Test Set.
The measured frequency tuning response, in Figure 16, shows 22
MHz/V tuning sensitivity in the 0.5–2.5 V range, typical for battery
applications. The simulated frequency tuning response shows a
The model used, however, was quite successful in achieving the
design goals at the first attempt (directly from simulation to physical design) and in understanding phenomena such as the
influence of TL1.
4
745
Fosc meas.
770
5
4
750
3
P1 out simu.
740
2
730
1
720
0
710
-1
Output Power (dBm)
760
743
2
741
0
739
-2
POUT (dBm)
-4
737
-6
735
2.4
-2
700
0
0.5
1.0
1.5
2.0
2.5
Control Voltage (V)
Fosc meas.
3.0
2.6
2.8
3.0
3.2
3.4
VCC Voltage (V)
Figure 17. IF VCO Pushing Response
P1 out meas.
Figure 16. IF VCO Tuning Response
Figure 18. IF VCO Phase Noise at VCTL = 1.5 V and VCC = 3 V
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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July 21, 2005 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • 200320 Rev. A
3.6
Output Power (dBm)
Fosc simu.
Frequency (MHz)
6
780
Frequency (MHz)
higher tuning range because the transmission line (TL1 in Figure
7b) significantly affects VCO performance. Another reason for the
divergence of the simulation and measurement data is the effect
of higher harmonics. A far more complicated circuit model than
the one described in Figure 7b is required to account for higher
harmonics.
APPLICATION NOTE • APN1010
Summary
References
In this application note, two VCO designs applicable for 2.4–2.5
GHz WLAN transceiver functions were demonstrated. It was
shown that an RF VCO with a large tuning sensitivity (about 150
MHz/V) could be achieved with low phase noise (< -91 dBc/Hz at
10 kHz offset) using Skyworks low resistance hyperabrupt varactor SMV1763-079. This varactor was also shown to suit a
lower frequency IF VCO, providing good tuning range and low
phase noise. VCO models were developed that were able to accurately predict performance, and were confirmed by a comparison
of simulated and measured performance.
1. AN9829, Brief Tutorial on IEEE 802.11 Wireless LANs, Intersil
Co., Feb. 1999.
List of Available Documents
1. The WLAN VCO Simulation Project Files for Libra IV.
2. The WLAN VCO Circuit Schematic and PCB Layout for Protel,
EDA Client, 1998 Version.
3. The WLAN VCO PCB Gerber Photo-plot Files.
TM
2. AN9837, PRISM II Chip Set Overview, 11 MBPS SiGe, Intersil
Co., Feb. 1999.
3. APN1016, T/R Switch for WCDMA and IMT-2000 Handset
Applications, Skyworks Solutions Inc., 1999.
4. APN1004, Varactor SPICE Models for RF VCO Applications,
Skyworks Solutions Inc., 1998.
5. APN1006, A Colpitts VCO for Wide Band
(0.95 GHz– 2.15 GHz) Set Top TV Tuner Applications, Skyworks
Solutions Inc., 1999.
6. APN1005, A Balanced Wide Band VCO for Set Top TV Tuner
Applications, Skyworks Solutions Inc., 1999.
7. APN1007, Switchable Dual-Band 170/420 MHz
VCO For Handset Cellular Applications, Skyworks Solutions Inc.,
1999.
8. APN1012, VCO Designs for Wireless Handset and CATV Set-Top
Applications, Skyworks Solutions Inc., 1999.
9. APN1013, A Differential VCO for GSM Handset Applications,
Skyworks Solutions Inc., 1999.
10. APN1015, GSM/PCS Dual-Band Switchable Colpitts IF VCO for
Handset Applications.
11. APN1016, A Low Phase Noise VCO Design for PCS Handset
Applications, Skyworks Solutions Inc., 1999.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200320 Rev. A • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • July 21, 2005
15
APPLICATION NOTE • APN1010
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information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to
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