IRFP440 Data Sheet July 1999 8.8A, 500V, 0.850 Ohm, N-Channel Power MOSFET This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17425. Ordering Information PART NUMBER IRFP440 PACKAGE TO-247 File Number 2089.3 Features • 8.8A, 500V • rDS(ON) = 0.850Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol BRAND D IRFP440 NOTE: When ordering, include the entire part number. G S Packaging JEDEC STYLE TO-247 SOURCE DRAIN GATE DRAIN (FLANGE) 4-347 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRFP440 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRFP440 500 500 8.8 5.6 35 ±20 150 1.2 480 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS VGS = 0V, ID = 250µA (Figure 10) 500 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V - - 25 µA - - 250 µA 8.8 - - A Zero-Gate Voltage Drain Current IDSS TEST CONDITIONS VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC On-State Drain Current (Note 2) Gate to Source Leakage ID(ON) IGSS Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time rDS(ON) gfs td(ON) Rise Time tr Turn-Off Delay Time VDS > ID(ON) x rDS(ON)MAX, VGS = 10V VGS = ±20V - - ±100 nA VGS = 10V, ID = 4.9A (Figures 8, 9) - 0.800 0.850 Ω 5.3 8.2 - S - 17 21 ns - 23 35 ns - 42 74 ns VDS ≥ 50V, ID = 4.9A (Figure 12) VDD = 250V, ID ≈ 8A, RGS = 9.1Ω, RL = 30.1Ω MOSFET Switching Times are Essentially Independent of Operating Temperature td(OFF) Fall Time tf Total Gate Charge (Gate to Source + Gate to Drain) Qg Gate to Source Charge Qgs VGS = 10V, ID = 8A, VDS = 0.8 x Rated BVDSS Ig(REF) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature - 18 30 ns - 42 63 nC - 7 - nC - 22 - nC - 1225 - pF Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance COSS - 200 - pF Reverse-Transfer Capacitance CRSS - 85 - pF - 5.0 - nH - 12.5 - nH - - 0.83 oC/W - - 30 oC/W VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) Internal Drain Inductance LD Measured from the drain Lead, 6mm (0.25in) from the Package to the Center of the Die Internal Source Inductance LS Measured from the Source Lead, 6mm (0.25in) from Header to the Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S Junction to Case RθJC Junction to Ambient RθJA 4-348 Free Air Operation IRFP440 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current ISD Pulse Source to Drain Current (Note 3) ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode MIN TYP MAX UNITS - - 8.8 A - - 35 A - - 1.8 V 210 460 970 ns 2 4.2 8.9 µC D G S Source to Drain Diode Voltage (Note 2) VSD Reverse Recovery Time trr Reverse Recovered Charge QRR TJ = 25oC, ISD = 8.8A, VGS = 0V (Figure 13) TJ = 25oC, ISD = 8.0A, dISD/dt = 100A/µs TJ = 25oC, ISD = 8.0A, dISD/dt = 100A/µs NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 11mH, RG = 50Ω, peak IAS = 8.8A. Typical Performance Curves Unless Otherwise Specified 10 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 8 6 4 2 0.2 0 0 0 50 100 25 150 50 TC , CASE TEMPERATURE (oC) 75 100 150 125 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 ZθJC, THERMAL IMPEDANCE POWER DISSIPATION MULTIPLIER 1.2 0.5 0.2 0.1 0.1 PDM 0.05 0.02 0.01 10-2 10-3 10-5 t1 t2 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC 10-4 10-3 10-2 0.1 t1 , RECTANGULAR PULSE DURATION (s) FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE 4-349 1 10 IRFP440 Typical Performance Curves Unless Otherwise Specified (Continued) 15 102 100µs 1ms 1 10ms TC = 25oC TJ = MAX RATED SINGLE PULSE 0.1 12 VGS = 6.0V 9 VGS = 5.5V 6 VGS = 5.0V 3 DC 0 103 0 50 100 150 200 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 102 VGS = 10V ID, DRAIN CURRENT (A) 12 VGS = 6.0V 9 VGS = 5.5V 6 VGS = 5.0V 3 VGS = 4.0V 0 0 VGS = 4.5V 3 6 9 12 VDS , DRAIN TO SOURCE VOLTAGE (V) 15 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS ≥ 50V 10 1 0.1 10-2 0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VOLTAGE 8 ON RESISTANCE rDS(ON), DRAIN TO SOURCE 3.0 5 VGS = 10V 2 VGS = 20V 0 0 8 16 24 ID , DRAIN CURRENT (A) 32 FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4-350 2 4 6 8 VGS , GATE TO SOURCE VOLTAGE (V) 10 FIGURE 7. TRANSFER CHARACTERISTICS PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 4 TJ = 25oC TJ = 150oC FIGURE 6. SATURATION CHARACTERISTICS 10 250 FIGURE 5. OUTPUT CHARACTERISTICS ID(ON), ON STATE DRAIN CURRENT (A) 15 VGS = 4.5V VGS = 4.0V 102 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 1 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 10µs 10 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V OPERATION IN THIS REGION IS LIMITED BY rDS(ON) 40 2.4 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX ID = 4.9A, VGS = 10V 1.8 1.2 0.6 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE IRFP440 Typical Performance Curves 3000 ID = 250µA 1.15 1.05 0.95 1800 CISS 1200 COSS 0.85 0.75 -60 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGS 2400 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 Unless Otherwise Specified (Continued) 600 -40 -20 0 20 40 60 80 0 100 120 140 160 CRSS 1 ISD, SOURCE TO DRAIN CURRENT (A) TJ = 25oC TJ = 150oC 3 0 50 100 102 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 10 TJ = 150oC 1 TJ = 25oC 0.1 0 3 6 9 ID , DRAIN CURRENT (A) 12 15 0 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 0.3 0.6 0.9 1.2 VSD , SOURCE TO DRAIN VOLTAGE (V) FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 VGS, GATE TO SOURCE VOLTAGE (V) gfs, TRANSCONDUCTANCE (S) 12 6 20 FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS ≥ 50V 9 10 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 15 5 2 TJ , JUNCTION TEMPERATURE (oC) ID = 8A 16 VDS = 100V 12 VDS = 250V VDS = 400V 8 4 0 0 12 24 36 48 60 Qg , GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 4-351 1.5 IRFP440 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN IAS + RG REQUIRED PEAK IAS - VGS VDS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 17. SWITCHING TIME TEST CIRCUIT 0.2µF 50% PULSE WIDTH 10% FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 50% VDD Qg(TOT) SAME TYPE AS DUT 50kΩ Qgd 0.3µF VGS Qgs D VDS DUT G 0 IG(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 4-352 IG(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRFP440 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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