IRF9620 Data Sheet July 1999 3.5A, 200V, 1.500 Ohm, P-Channel Power MOSFET This P-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. File Number 2283.2 Features • 3.5A, 200V • rDS(ON) = 1.500Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance Symbol Formerly developmental type TA17502. D Ordering Information PART NUMBER IRF9620 PACKAGE TO-220AB G BRAND IRF9620 S NOTE: When ordering, use the entire part number. Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) 4-21 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRF9620 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor (Figure 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRF9620 -200 -200 -3.5 -2 -14 ±20 40 0.32 290 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to TJ = 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS ID = -250µA, VGS = 0V, (Figure 10) -200 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = -250µA -2 - -4 V VDS = Rated BVDSS, VGS = 0V - - -25 µA - - -250 µA -3.5 - - A Zero Gate Voltage Drain Current IDSS VDS = 0.8 x Rated BVDSS, VGS = 0V, TC =125oC On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time ID(ON) IGSS rDS(ON) gfs td(ON) Rise Time tr Turn-Off Delay Time td(OFF) Fall Time tf Total Gate Charge (Gate to Source + Gate to Drain) Qg(TOT) Gate to Source Charge Qgs Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Internal Drain Inductance LD VDS > ID(ON) x rDS(ON)MAX, VGS = -10V VGS = ±20V - - ±100 nA ID = -1.5A, VGS = -10V, (Figures 8, 9) - 1.000 1.500 Ω VDS > ID(ON) x rDS(ON)MAX, ID = -1.5A, (Figure 12) 1 1.8 - S VDD = 0.5 x Rated BVDSS, ID ≈ -3.5A, RG = 50Ω, RL = 26Ω, for BVDSS = 200V RL = 20Ω for BVDSS = 150V (Figures 17, 18) MOSFET Switching Times are Essentially Independent of Operating Temperature - 30 50 ns - 50 100 ns - 80 120 ns - 50 75 ns VGS = -10V, ID = -3.5A, VDS = 0.8 x Rated BVDSS, IG(REF) = 1.5mA, (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature - 16 22 nC - 9 - nC - 7 - nC VDS = -25V, VGS = 0V, f = 1MHz, (Figure 11) Measured From the Contact Screw on Tab To Center of Die Measured From the Drain Lead, 6mm (0.25in) from Package to Center of Die Internal Source Inductance LS Measured From the Source Lead, 6mm (0.25in) from Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D - 350 - pF - 100 - pF - 30 - pF - 3.5 - nH - 4.5 - nH - 7.5 - nH - - 3.12 oC/W - - 80 oC/W LD G LS S Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA 4-22 Typical Socket Mount IRF9620 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current ISD Pulse Source to Drain Current (Note 3) ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode MIN TYP MAX UNITS - - -3.5 A - - -14 A D G S Source to Drain Diode Voltage (Note 2) TC = 25oC, ISD = -3.5A, VGS = 0V (Figure 13) - - -1.5 V trr TJ = 150oC, ISD = -3.5A, dISD/dt = 100A/µs - 300 - ns QRR TJ = 150oC, ISD = -3.5A, dISD/dt = 100A/µs - 1.9 - µC VSD Reverse Recovery Time Reverse Recovery Charge NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 35.5mH, RG = 25Ω, peak IAS = 3.5A (Figures 15, 16). Typical Performance Curves Unless Otherwise Specified -5 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 0 -4 -3 -2 -1 0 0 50 100 25 150 50 TC, CASE TEMPERATURE (oC) 75 100 125 150 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 ZθJC, NORMALIZED THERMAL IMPEDANCE POWER DISSIPATION MULTIPLIER 1.2 0.5 0.2 0.1 0.1 PDM 0.05 0.02 0.01 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t1 , RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 4-23 1 10 IRF9620 Typical Performance Curves Unless Otherwise Specified (Continued) -5 OPERATION IN THIS AREA IS LIMITED BY rDS(ON) ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) -100 10µs -10 100µs 1ms -1 10ms 100ms DC TC = 25oC TJ = MAX RATED SINGLE PULSE -10 -100 VDS, DRAIN TO SOURCE VOLTAGE (V) -0.1 -1 VGS = -10V VGS = -8V VGS = -9V -4 VGS = -6V -2 VGS = -5V -1 VGS = -4V 0 -1000 0 -10 ID(ON), ON STATE DRAIN CURRENT (A) ID, DRAIN CURRENT (A) VGS = -7V VGS = -8V VGS = -9V VGS = -10V VGS = -6V -2 VGS = -5V -1 VGS = -4V 0 -50 VDS ≥ I D(ON) x rDS(ON) MAX PULSE DURATION = 80µs -4 DUTY CYCLE = 0.5% MAX TJ = 125oC TJ = 25oC -3 TJ = -55oC -2 -1 -5 0 FIGURE 6. SATURATION CHARACTERISTICS NORMALIZED DRAIN TO SOURCE ON RESISTANCE 4 3 VGS = -10V 2 VGS = - 20V 0 0 4 12 8 ID, DRAIN CURRENT (A) 16 20 VGS = -10V, ID = -1.5A PULSE DURATION = 80µs 2.0 DUTY CYCLE = 0.5% MAX 1.5 1.0 0.5 0 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) NOTE: Heating effect of 2µs pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4-24 -10 2.5 PULSE DURATION = 2µs 1 -2 -4 -6 -8 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 7. TRANSFER CHARACTERISTICS 5 ON RESISTANCE (Ω) -40 0 -4 -2 -3 -1 VDS, DRAIN TO SOURCE VOLTAGE (V) 0 rDS(ON), DRAIN TO SOURCE -30 FIGURE 5. OUTPUT CHARACTERISTICS -5 -3 -20 VDS, DRAIN TO SOURCE VOLTAGE (V) -5 -4 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX -3 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = -7V FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 160 IRF9620 Typical Performance Curves Unless Otherwise Specified (Continued) 1.25 500 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 400 1.15 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250µA 1.05 0.95 CISS 300 200 COSS 100 0.85 CRSS 0 0.75 -40 0 40 80 120 10 0 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE -100 ISD, SOURCE TO DRAIN CURRENT (A) 3.2 TJ = -55oC TJ = 25oC TJ = 125oC 0.8 0 0 -1 -2 -3 -4 -10 -0.1 -0.4 -5 TJ = 150oC TJ = 25oC -1.0 -0.8 -0.6 -1.0 -1.4 -1.6 FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 0 ID = -3.5A -5 VDS = -60V VDS = -40V -10 VDS = -100V 4 8 12 16 20 Qg(TOT) , TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 4-25 -1.2 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 0 50 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX I D , DRAIN CURRENT (A) VGS, GATE TO SOURCE (V) gfs, TRANSCONDUCTANCE (S) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 1.6 40 FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 4.0 2.4 30 20 VDS, DRAIN TO SOURCE VOLTAGE (V) -1.8 IRF9620 Test Circuits and Waveforms VDS tAV L 0 VARY tP TO OBTAIN - RG REQUIRED PEAK IAS + VDD DUT 0V VDD tP VGS IAS IAS VDS tP 0.01Ω BVDSS FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(OFF) td(ON) tr 0 - DUT VGS VDS VDD VGS 0 + 10% 10% RL RG tf 90% 90% 10% 50% 50% PULSE WIDTH 90% FIGURE 18. RESISTIVE SWITCHING WAVEFORMS FIGURE 17. SWITCHING TIME TEST CIRCUIT -VDS (ISOLATED SUPPLY) CURRENT REGULATOR 0 VDS DUT 12V BATTERY 0.2µF 50kΩ 0.3µF Qgs Qg(TOT) DUT G VGS Qgd D VDD 0 S IG(REF) IG CURRENT SAMPLING RESISTOR +VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 4-26 0 IG(REF) FIGURE 20. GATE CHARGE WAVEFORMS IRF9620 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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