IRFBC40 Data Sheet July 1999 6.2A, 600V, 1.200 Ohm, N-Channel Power MOSFET This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. File Number 2157.3 Features • 6.2A, 600V • rDS(ON) = 1.200Ω • Single Pulse Avalanche Energy Rated • Simple Drive Requirements • Ease of Paralleling • Related Literature - TB334, “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Formerly developmental type TA17426. D Ordering Information PART NUMBER IRFBC40 PACKAGE TO-220AB BRAND G IRFBC40 S NOTE: When ordering, include the entire part number. Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) 4-263 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRFBC40 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 2) (See Figures 15,16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRFBC40 600 600 6.2 3.9 25 ±20 125 1.0 570 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS VGS = 0V, ID = 250µA, (Figure 11) 600 - - V Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V - - 25 µA - - 250 µA 6.2 - - A Zero Gate Voltage Drain Current IDSS TEST CONDITIONS VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC On-State Drain Current (Note 4) Gate to Source Leakage ID(ON) VGS = ±20V - - ±100 nA rDS(ON) VGS = 10V, ID = 3.4A (Figures 9, 10) - 0.97 1.2 Ω gfs VDS ≥ 100V, IDS = 3.4A (Figure 13) 4.7 70 - S - 13 20 ns - 18 27 ns - 55 83 ns IGSS Drain to Source On Resistance (Note 2) Forward Transconductance (Note 4) Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time VDS > ID(ON) x rDS(ON)MAX, VGS = 10V VDD = 300V, ID ≈ 6.2A, RG = 9.1Ω, VGS = 10V, RL = 47Ω Switching Speeds are Essentially ndependent of Operating Temperature td(OFF) Fall Time tf Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Qg(TOT) Qgs - 20 30 ns VGS = 10V, ID = 6.2A, VDS = 0.7 x Rated BVDSS (Figure 14) Gate Charge is Essentially Independent of Operating Temperature - 40 60 nC - 5.5 - nC - 20 - nC VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 12) - 1300 - pF Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance COSS - 160 - pF Reverse Transfer Capacitance CRSS - 45 - pF - 4.5 - nH - 7.5 - nH - - 1.0 oC/W - - 80 oC/W Internal Drain Inductance LD Measured from the Drain Lead, 6mm (0.25in) from Package to Center of Die Internal Source Inductance LS Measured from the Source Lead, 6mm (0.25in) from Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA 4-264 Typical Socket Mount IRFBC40 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current ISD Pulse Source to Drain Current (Note 3) ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode MIN TYP MAX UNITS - - 6.2 A - - 25 A - - 1.5 V 200 450 940 ns 1.8 3.8 8.0 µC D G S Diode Source to Drain Voltage (Note 2) VSD Reverse Recovery Time trr Reverse Recovery Charge QRR TJ = 25oC, ISD = 6.2A, VGS = 0V (Figure 8) TJ = 25oC, ISD = 6.2A, dISD/dt = 100A/µs TJ = 25oC, ISD = 6.2A, dISD/dt = 100A/µs NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 16mH, RG = 25Ω, peak IAS = 6.8A Typical Performance Curves Unless Otherwise Specified 10 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 0 8 6 4 2 0 0 50 100 150 25 50 TC, CASE TEMPERATURE (oC) 75 100 125 150 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 ZθJC, NORMALIZED TRANSIENT THERMAL IMPEDANCE (oC/W) POWER DISSIPATION MULTIPLIER 1.2 0.5 0.2 0.1 0.1 0.05 0.02 0.02 0.01 10-2 10-3 10-5 PDM SINGLE PULSE t1 t2 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 10-4 0.1 10-3 10-2 t1, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 4-265 1 10 IRFBC40 Typical Performance Curves (Continued) 10 OPERATION IN THIS REGION IS LIMITED BY rDS(ON) 10µs 10 100µs 1ms 1 10ms TC = 25oC TJ = MAX RATED 1 VGS = 6.0V 6 VGS = 5.0V 4 VGS = 4.5V 2 102 10 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS = 4.0V 0 103 0 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS =10V 6 VGS = 5.0V 4 2 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS ≥ 100V VGS = 4.5V VGS = 4.0V 0 0 3 6 9 12 VDS, DRAIN TO SOURCE VOLTAGE (V) 1 TJ = 150oC 10-2 0 15 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 FIGURE 7. TRANSFER CHARACTERISTICS 5 102 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX DRAIN TO SOURCE ON RESISTANCE ISD, SOURCE TO DRAIN CURRENT (A) TJ = 25oC 0.1 FIGURE 6. SATURATION CHARACTERISTICS 10 TJ = 150oC TJ = 25oC 1 0.1 0 300 10 VGS = 6.0V VGS = 5.5V 8 60 120 180 240 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. OUTPUT CHARACTERISTICS ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 10 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX DC SINGLE PULSE 0.1 VGS = 5.5V VGS = 10V 8 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 102 Unless Otherwise Specified PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 4 3 VGS = 10V 2 VGS = 20V 1 0 0.3 0.6 0.9 1.2 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 8. SOURCE TO DRAIN DIODE VOLTAGE 4-266 1.5 0 6 12 18 ID, DRAIN CURRENT (A) 24 FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 30 IRFBC40 Typical Performance Curves 2.4 1.25 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX ID = 3.4A, VGS = 10V 1.8 1.2 0.6 0 -60 -40 -20 0 20 40 (Continued) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 3.0 Unless Otherwise Specified 60 1.15 1.05 0.95 0.85 0.75 -60 100 120 140 160 80 ID = 250µA -40 -20 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 10 C, CAPACITANCE (pF) gfs, TRANSCONDUCTANCE (S) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 1800 20 40 60 80 100 120 140 160 FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 3000 2400 0 TJ, JUNCTION TEMPERATURE (oC) CISS 1200 COSS 600 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS ≥ 100V 8 TJ = 25oC TJ = 150oC 6 4 2 CRSS 0 0 2 0 102 10 20 50 5 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE GATE TO SOURCE VOLTAGE (V) 20 0 2 4 6 ID, DRAIN CURRENT (A) FIGURE 13. TRANSCONDUCTANCE vs DRAIN CURRENT ID = 6.2A 16 VDS = 120V VDS = 240V 12 VDS = 360V 8 4 0 0 12 24 36 48 60 Qg, GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 4-267 8 10 IRFBC40 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN + RG REQUIRED PEAK IAS VDS IAS VDD VDD - VGS DUT tP IAS 0V 0 0.01Ω tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 17. SWITCHING TIME TEST CIRCUIT 0.2µF 50% PULSE WIDTH 10% FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 50% VDD Qg(TOT) SAME TYPE AS DUT 50kΩ Qgd 0.3µF VGS Qgs D VDS DUT G 0 IG(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 4-268 IG(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRFBC40 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. 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