ESD8351P2 D

ESD8351P2, SZESD8351P2
ESD Protection Diodes
Low Capacitance ESD Protection Diode
for High Speed Data Line
The ESD8351P2 ESD protection diode is designed to protect high
speed data lines from ESD. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines.
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MARKING
DIAGRAM
Features
• Low Capacitance (0.55 pF Max, I/O to GND)
• Protection for the Following IEC Standards:
•
•
•
SOD−923
CASE 514AB
IEC 61000−4−2 (Level 4)
ISO 10605
Low ESD Clamping Voltage
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
X, XX
M
= Specific Device Code
= Date Code
PIN CONFIGURATION
AND SCHEMATIC
1
Cathode
• USB 2.0
• eSATA
AC M
2
Anode
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Operating Junction Temperature Range
TJ
−55 to +125
°C
Storage Temperature Range
Tstg
−55 to +150
°C
Lead Solder Temperature −
Maximum (10 Seconds)
TL
260
°C
ESD
ESD
ESD
±15
±15
±30
kV
kV
kV
Ipp
5.0
A
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ISO 10605 330 pF / 2 kW Contact
Maximum Peak Pulse Current
8/20 ms @ TA = 25°C
=
Rating
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2016
January, 2016 − Rev. 0
1
Publication Order Number:
ESD8351P2/D
ESD8351P2, SZESD8351P2
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
Symbol
VRWM
IR
VBR
IPP
Parameter
Working Peak Voltage
RDYN
Maximum Reverse Leakage Current @ VRWM
VBR
Breakdown Voltage @ IT
V
VC VRWMVHOLD
Test Current
IR
IT
VHOLD
Holding Reverse Voltage
IHOLD
IHOLD
Holding Reverse Current
RDYN
Dynamic Resistance
IT
VC
RDYN
IPP
Maximum Peak Pulse Current
VC
Clamping Voltage @ IPP
VC = VHOLD + (IPP * RDYN)
−IPP
VC = VHOLD + (IPP * RDYN)
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Symbol
VRWM
VBR
Conditions
Min
Typ
I/O Pin to GND
IT = 1 mA, I/O Pin to GND
5.5
7.0
Unit
3.3
V
7.8
V
500
nA
Reverse Leakage Current
IR
Holding Reverse Voltage
VHOLD
I/O Pin to GND
Holding Reverse Current
IHOLD
I/O Pin to GND
20
Clamping Voltage
TLP (Note 2)
See Figures 1 through 11
VC
IPP = 8 A
IEC 61000−4−2 Level 2 equivalent
(±4 kV Contact, ±4 kV Air)
5.7
6.5
IPP = 16 A
IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact, ±15 kV Air)
8.3
10
IPP = 5 A
tp = 8 x 20 ms
5.7
6.5
Clamping Voltage (Note 3)
VC
Dynamic Resistance
RDYN
Junction Capacitance
CJ
VRWM = 3.3 V, I/O Pin to GND
Max
1.15
Pin1 to Pin2
Pin2 to Pin1
0.44
0.37
VR = 0 V, f = 1 Mhz
VR = 0 V, f = 2.5 Ghz
0.37
0.35
V
mA
V
V
W
0.55
0.45
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see Figures 8 and 9 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
3. Non−repetitive current pulse at TA = 20°C, per IEC 61000−4−5 waveform.
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2
1.0
10
0.9
9
0.8
8
0.7
7
0.6
6
Vpk (V)
0.5
0.4
5
4
0.3
3
0.2
2
0.1
0
1
0
0.5
1.0
1.5
2.0
2.5
3.0
0
3.5
1
3
2.5
3.5
4
4.5
5
6
5.5
VBias (V)
Ipk (A)
Figure 2. Clamping Voltage vs Peak Pulse
Current ( tp = 8/20 ms)
2.0
m1
m2
0
1.8
1.6
CAPACITANCE (pF)
−2
−4
dB
2
Figure 1. CV Characteristics
2
−6
−8
−10
1.4
1.2
1.0
0.8
0.6
0.4
−12
0.2
−14
0
1E7
1E8
1
1E10 3E10
1E9
2
3
5
4
6
7
9
8
FREQUENCY (Hz)
FREQUENCY
Figure 3. RF Insertion Loss
Figure 4. Capacitance over Frequency
20
10
20
10
10
18
8
14
12
6
10
8
4
6
4
2
16
TLP CURRENT (A)
16
EQUIVALENT VIEC (kV)
18
TLP CURRENT (A)
1.5
8
14
12
6
10
8
4
6
4
2
2
2
0
0
0
0
2
4
6
8
10
12
14
16
18
0
0
20
VC, VOLTAGE (V)
2
4
6
8
10
12
14
16
18
VC, VOLTAGE (V)
Figure 5. Positive TLP I−V Curve
Figure 6. Negative TLP I−V Curve
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3
20
EQUIVALENT VIEC (kV)
C (pF)
ESD8351P2, SZESD8351P2
ESD8351P2, SZESD8351P2
Latch−Up Considerations
stable operating point of the circuit and the system is
therefore latch−up free. In the non−latch up free load line
case, the IV characteristic of the snapback protection device
intersects the load−line in two points (VOPA, IOPA) and
(VOPB, IOPB). Therefore in this case, the potential for
latch−up exists if the system settles at (VOPB, IOPB) after a
transient. Because of this, ESD8351P2 should not be used
for HDMI applications – ESD8104 or ESD8040 have been
designed to be acceptable for HDMI applications without
latch−up. Please refer to Application Note AND9116/D for
a more in−depth explanation of latch−up considerations
using ESD8000 series devices.
ON Semiconductor’s 8000 series of ESD protection
devices utilize a snap−back, SCR type structure. By using
this technology, the potential for a latch−up condition was
taken into account by performing load line analysis of
common high speed serial interfaces. Example load lines for
latch−up free applications and applications with the
potential for latch−up are shown below with a generic IV
characteristic of a snapback, SCR type structured device
overlaid on each. In the latch−up free load line case, the IV
characteristic of the snapback protection device intersects
the load−line in one unique point (VOP, IOP). This is the only
I
I
ISSMAX
ISSMAX
IOP
VOP
IOPB
IOPA
V
VDD
V
ESD8351P2 Latch*up free:
USB 2.0 LS/FS, USB 2.0 HS, USB 3.0 SS,
DisplayPort
VOPA
VOPB
VDD
ESD8351P2 Potential Latch*up:
HDMI 1.4/1.3a TMDS
Figure 7. Example Load Lines for Latch−up Free Applications and Applications with the Potential for Latch−up
Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH−UP FREE APPLICATIONS
Application
VBR (min)
(V)
IH (min)
(mA)
VH (min)
(V)
ON Semiconductor ESD8000 Series
Recommended PN
HDMI 1.4/1.3a TMDS
3.465
54.78
1.0
ESD8104, ESD8040
USB 2.0 LS/FS
3.301
1.76
1.0
ESD8004, ESD8351P2
USB 2.0 HS
0.482
N/A
1.0
ESD8004, ESD8351P2
USB 3.0 SS
2.800
N/A
1.0
ESD8004, ESD8006, ESD8351P2
DisplayPort
3.600
25.00
1.0
ESD8004, ESD8006, ESD8351P2
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4
ESD8351P2, SZESD8351P2
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 8. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 9. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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5
ESD8351P2, SZESD8351P2
Transmission Line Pulse (TLP) Measurement
L
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 10. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 11 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
50 W Coax
Cable
S Attenuator
÷
50 W Coax
Cable
10 MW
IM
VM
DUT
VC
Oscilloscope
Figure 10. Simplified Schematic of a Typical TLP
System
Figure 11. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
ORDERING INFORMATION
Device
ESD8351P2T5G,
SZESD8351P2T5G*
Package
Shipping†
SOD−923
(Pb−Free)
8000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
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6
ESD8351P2, SZESD8351P2
PACKAGE DIMENSIONS
SOD−923
CASE 514AB
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.
−X−
D
−Y−
E
1
2X b
0.08 X Y
2
DIM
A
b
c
D
E
HE
L
L2
TOP VIEW
A
c
MILLIMETERS
MIN
NOM MAX
0.34
0.37
0.40
0.15
0.20
0.25
0.07
0.12
0.17
0.75
0.80
0.85
0.55
0.60
0.65
0.95
1.00
1.05
0.19 REF
0.05
0.10
0.15
SOLDERING FOOTPRINT*
HE
SIDE VIEW
1.20
2X
2X
2X
0.36
L
PACKAGE
OUTLINE
2X
INCHES
MIN
NOM MAX
0.013 0.015 0.016
0.006 0.008 0.010
0.003 0.005 0.007
0.030 0.031 0.033
0.022 0.024 0.026
0.037 0.039 0.041
0.007 REF
0.002 0.004 0.006
L2
0.25
DIMENSIONS: MILLIMETERS
See Application Note AND8455/D for more mounting details
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
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For additional information, please contact your local
Sales Representative
ESD8351P2/D
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