ESD8008 D

ESD8008
ESD Protection Diode
Low Capacitance Array for High Speed
Data Lines
The ESD8008 is designed specifically to protect four high speed
differential pairs. Ultra−low capacitance and low ESD clamping
voltage make this device an ideal solution for protecting voltage
sensitive high speed data lines. The flow−through style package
allows for easy PCB layout and matched trace lengths necessary to
maintain consistent impedance for the high speed lines.
Features
•
•
•
•
•
•
•
Integrated 4 Pairs (8 Lines) High Speed Data
Single Connect, Flow through Routing
Low Capacitance (0.35 pF Max, I/O to GND)
Protection for the Following IEC Standards:
IEC 61000−4−2 Level 4 (ESD) ±15 kV (Contact)
IEC 61000−4−5 (Lightning) 5 A (8/20 ms)
UL Flammability Rating of 94 V−0
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
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MARKING
DIAGRAM
14
1
8008M
G
UDFN14
CASE 517CN
8008
M
G
= Specific Device Code
= Date Code
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping
ESD8008MUTAG
UDFN14
(Pb−Free)
3000 / Tape &
Reel
SZESD8008MUTAG
UDFN14
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• V−by−One HS
• LVDS
• Display Port
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range
TJ
−55 to +125
°C
Storage Temperature Range
Tstg
−55 to +150
°C
Lead Solder Temperature −
Maximum (10 Seconds)
TL
260
°C
ESD
ESD
±15
±15
kV
kV
IPP
5.0
A
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
Maximum Peak Pulse Current
8/20 ms @ TA = 25°C (I/O−GND)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2015
February, 2015 − Rev. 4
1
Publication Order Number:
ESD8008/D
ESD8008
I/O
Pin 1
I/O
Pin 2
I/O
Pin 4
I/O
Pin 5
I/O
Pin 7
I/O
Pin 8
I/O
Pin 10
I/O
Pin 11
Center Pins, Pin 3, 6, 9, 12, 13, 14
Note: Common GND − Only Minimum of 1 GND connection required
=
Figure 1. Pin Schematic
I/O 1
I/O 2
14 GND
GND 3
I/O 4
I/O 5
13 GND
GND 6
I/O 7
I/O 8
GND 9
12 GND
I/O 10
I/O 11
Figure 2. Pin Configuration
Note: Only minimum of one pin needs to be connected to
ground for functionality of all pins.
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2
ESD8008
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
Symbol
VRWM
IR
VBR
IPP
Parameter
Working Peak Voltage
RDYN
Maximum Reverse Leakage Current @ VRWM
VBR
Breakdown Voltage @ IT
V
VC VRWMVHOLD
Test Current
IR
IT
VHOLD
Holding Reverse Voltage
IHOLD
IHOLD
Holding Reverse Current
RDYN
Dynamic Resistance
IT
VC
RDYN
IPP
Maximum Peak Pulse Current
VC
Clamping Voltage @ IPP
VC = VHOLD + (IPP * RDYN)
−IPP
VC = VHOLD + (IPP * RDYN)
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Symbol
Reverse Working Voltage
VRWM
Breakdown Voltage
VBR
Conditions
Min
Typ
Max
Unit
3.3
V
I/O Pin to GND
IT = 1 mA, I/O Pin to GND
5.5
7.0
VRWM = 3.3 V, I/O Pin to GND
8.5
V
0.5
mA
Reverse Leakage Current
IR
Holding Reverse Voltage
VHOLD
I/O Pin to GND
1.19
V
Holding Reverse Current
IHOLD
I/O Pin to GND
25
mA
Clamping Voltage (Note 1)
VC
IEC61000−4−2, ±8 KV Contact
See Figures 3 and 4
V
Clamping Voltage
VC
IPP = 1 A, Any I/O to GND (8/20 ms pulse)
1.5
V
Clamping Voltage
VC
IPP = 5 A, Any I/O to GND (8/20 ms pulse)
5.0
V
Clamping Voltage
TLP (Note 2)
See Figures 7 through 10
VC
IPP = 8 A
IPP = −8 A
IEC 61000−4−2 Level 2 equivalent
(±4 kV Contact, ±4 kV Air)
4.6
−5.1
V
IPP = 16 A
IPP = −16 A
IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact, ±15 kV Air)
8.1
−10.3
Dynamic Resistance
RDYN
Junction Capacitance
CJ
I/O Pin to GND
GND to I/O Pin
0.43
0.50
VR = 0 V, f = 1 MHz between I/O Pins and GND
VR = 0 V, f = 2.5 GHz between I/O Pins and GND
VR = 0 V, f = 5.0 GHz between I/O Pins and GND
VR = 0 V, f = 1 MHz, between I/O Pins
0.30
0.20
0.20
0.10
W
0.35
pF
0.16
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see Figures 5 and 6 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
90
0
80
−10
70
−20
VOLTAGE (V)
VOLTAGE (V)
60
50
40
30
20
−30
−40
−50
−60
10
−70
0
−80
−10
−20
0
20
40
60
80
TIME (ns)
100
120
−90
−20
140
Figure 3. IEC61000−4−2 +8 kV Contact ESD
Clamping Voltage
0
20
40
60
80
TIME (ns)
100
120
Figure 4. IEC61000−4−2 −8 kV Contact
Clamping Voltage
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3
140
ESD8008
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 5. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 6. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8307/D − Characterization of ESD Clamping
Performance.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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4
ESD8008
20
−20
10
18
−14
6
12
6
−12
−10
10
4
8
6
4
2
VC = VHOLD + (IPP * RDYN)
2
NOTE:
8
−16
EQUIVALENT VIEC (kV)
TLP CURRENT (A)
TLP CURRENT (A)
14
2
4
6
8
10
12
14
16
4
−8
−6
2
−4
EQUIVALENT VIEC (kV)
8
16
0
0
10
−18
−2
18
0
0
20
0
2
4
6
8
10
12
14
16
VC, VOLTAGE (V)
VC, VOLTAGE (V)
Figure 7. Positive TLP I−V Curve
Figure 8. Negative TLP I−V Curve
18
0
20
TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
Transmission Line Pulse (TLP) Measurement
L
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 9. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 10 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
50 W Coax
Cable
S Attenuator
÷
50 W Coax
Cable
10 MW
IM
VM
DUT
VC
Oscilloscope
Figure 9. Simplified Schematic of a Typical TLP
System
Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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5
Peak
Value
100
8
tr = rise time to peak value [8 ms]
tf = decay time to half value [20 ms]
7
6
Vpk (V)
Ipp - PEAK PULSE CURRENT - %Ipp
ESD8008
Half Value
50
5
I/O−GND
4
3
2
1
0
0 tr
0
tf
0
1
TIME (ms)
2
3
4
Ipk (A)
5
6
7
8
Figure 12. Clamping Voltage vs. Peak Pulse Current
(tp = 8/20 ms per Figure 11)
Figure 11. IEC61000−4−5 8/20 ms Pulse
Waveform
Figure 13. Junction Capacitance; VR = 0, f = 500 MHz − 10 GHz
Interface
V−by−One HS
Full HD (1920 x 1080p)
240 Hz, 36bit color depth
Data Rate
(Gbps)
Fundamental
Frequency (GHz)
3rd Harmonic
Frequency (GHz)
ESD8008 Insertion
Loss (−dB)
3.71
1.854 (m1)
5.562 (m3)
m1 = 0.146
m3 = 0.451
Figure 14. ESD8008 Insertion Loss
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6
ESD8008
ESD8008
Rx0p
Rx0n
Rx1p
Rx1n
Rx2p
Rx2n
Rx3p
ESD8008
Rx4p
TCON Board
Connector
Timing Controller
Rx3n
Rx4n
Rx5p
Rx5n
Rx6p
Rx6n
Rx7p
Rx7n
Figure 15. V−by−One HS Layout Diagram (for LCD Panel)
PCB Layout Guidelines
♦
Steps must be taken for proper placement and signal trace
routing of the ESD protection device in order to ensure the
maximum ESD survivability and signal integrity for the
application. Such steps are listed below.
• Place the ESD protection device as close as possible to
the I/O connector to reduce the ESD path to ground and
improve the protection performance.
• Make sure to use differential design methodology and
impedance matching of all high speed signal traces.
♦
♦
Use curved traces when possible to avoid unwanted
reflections.
Keep the trace lengths equal between the positive
and negative lines of the differential data lanes to
avoid common mode noise generation and
impedance mismatch.
Place grounds between high speed pairs and keep as
much distance between pairs as possible to reduce
crosstalk.
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7
ESD8008
Latch-Up Considerations
stable operating point of the circuit and the system is
therefore latch-up free. In the non-latch up free load line
case, the IV characteristic of the snapback protection device
intersects the load-line in two points (VOPA, IOPA) and
(VOPB, IOPB). Therefore in this case, the potential for
latch-up exists if the system settles at (VOPB, IOPB) after a
transient. Because of this, ESD8008 should not be used for
HDMI applications – ESD8104 or ESD8040 have been
designed to be acceptable for HDMI applications without
latch-up. Please refer to Application Note AND9116/D for
a more in-depth explanation of latch-up considerations
using ESD8000 series devices.
ON Semiconductor’s 8000 series of ESD protection
devices utilize a snap-back, SCR type structure. By using
this technology, the potential for a latch-up condition was
taken into account by performing load line analyses of
common high speed serial interfaces. Example load lines for
latch-up free applications and applications with the potential
for latch-up are shown below with a generic IV
characteristic of a snapback, SCR type structured device
overlaid on each. In the latch-up free load line case, the IV
characteristic of the snapback protection device intersects
the load-line in one unique point (VOP, IOP). This is the only
I
I
ISSMAX
IOPB
ISSMAX
IOP
VOP
IOPA
V
VDD
VOPB
ESD8008 Latch−up free:
V−by−One HS, DisplayPort, LVDS
VOPA VDD
V
ESD8008 Potential Latch−up:
HDMI 1.4/1.3a TMDS
Figure 16. Example Load Lines for Latch-up Free Applications and Applications with the Potential for Latch-up
Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH-UP FREE APPLICATIONS
Application
VBR (min)
(V)
IH (min)
(mA)
VH (min)
(V)
ON Semiconductor ESD8000 Series
Recommended PN
HDMI 1.4/1.3a TMDS
3.465
54.78
1.0
ESD8104, ESD8040
DisplayPort
3.600
25.00
1.0
ESD8004, ESD8006, ESD8008
V−by−One HS
1.980
21.70
1.0
ESD8008
LVDS
1.829
9.20
1.0
ESD8008
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8
ESD8008
PACKAGE DIMENSIONS
UDFN14, 5.5x1.5, 0.5P
CASE 517CN
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.10 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
PIN ONE
REFERENCE
2X
0.10 C
2X
ÉÉ
ÉÉ
0.10 C
A B
D
L1
DETAIL A
OPTIONAL
CONSTRUCTION
E
TOP VIEW
(A3)
DETAIL B
0.05 C
EXPOSED Cu
A
0.10 C
ÉÉ
ÇÇ
MOLD CMPD
DETAIL B
NOTE 4
A1
SIDE VIEW
e
DETAIL C
D2
12
C
OPTIONAL
CONSTRUCTION
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.15
0.25
5.50 BSC
0.45
0.55
1.50 BSC
0.50
0.70
0.50 BSC
0.20
0.40
0.00
0.05
DETAIL A
1
E2
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
L
11
0.10
REF
14
14X
BOTTOM VIEW
DETAIL C
b
0.10
M
C A B
0.05
M
C
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT*
6X
3X
PACKAGE
OUTLINE
0.43
0.56
1.80
3X
0.62
14X
0.26
0.50
PITCH
14X
0.50
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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ESD8008/D
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