AK4678ECB

[AKD4678-B]
AKD4678-B
Evaluation board Rev.1 for AK4678
GENERAL DESCRIPTION
The AKD4678-B is an evaluation board for AK4678, 24bit stereo CODEC with Microphone/ Receiver/
Headphone/ Speaker/ Line amplifier. The AKD4678-B has the Digital Audio I/F and can achieve the interface
with digital audio systems via optical connector.
„ Ordering Guide
AKD4678-B --- AK4678 Evaluation Board
(A cable for connecting with USB port of PC and a control software are packed with this.)
FUNCTION
• DIR/DIT with optical input/output
• 10pin Header for Digital Audio I/F and PCM I/F (Baseband, Bluetooth)
• 10pin Header for I2C control mode
5.0V IN
4.2V
1.8V
3.3V
REG
REG
SVDD AVDD DVDD PVDD TVDD D3V
J3
LIN1
PORT1
(Bluetooth)
LIN2
PORT2
(Baseband)
LIN3
Mini
Jack
PORT3
(DSP)
LIN4
AK4678
RIN1
PORT5
Opt In
RIN2
AK4118A
(DIT/DIR)
RIN3
PIC4550
RIN4
LOL
LOR HPL
HPR
PORT6
Opt Out
U7
(USB Connector)
Regulator
PORT4
(up-I/F)
J1
Line out
Jack
J2
HP
Jack
SPP SPNRCP RCN
Figure 1. AKD4678-B Block Diagram
*Circuit diagram and PCB layout are attached at the end of this manual.
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„
Component layout
Figure 2. AKD4678-B Component layout
„
Component explanation
1. J1,2 (Mini Jacks)
Output terminal of analog signal
2. J3 (Mini Jacks)
Input terminal of analog signal
3. +4.2V, GND (Power Supply Connector)
Please connect to Power Supply. Each supply line should be distributed from the power supply unit.
4. PORT1, PORT2, PORT3 (10pin Header)
PORT1 (Bluetooth port) : MCLKB, BICKB, LRCKB, SDTOB, SDTIB can output and input from PORT1.
PORT2 (Baseband port) : MCLKA, BICKA, LRCKA, SDTOA, SDTIA can output and input from PORT2.
PORT3 (DSP port) : MCLK, BICK, LRCK, SDTI, SDTO can output and input from PORT3.
5. PORT5, PORT6 (Optical Connectors)
PORT6 (Output) : PORT6 outputs Optical Digital Signal from AK4118A.
PORT5 (Input) : PORT5 inputs Optical Digital Signal from AK4118A.
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EVALUATION BORAD
„
Operation Sequence
[1]
Power Supply
1) Set up the Power Supply Lines
Name
+4.2V
GND
Color
RED
BLACK
Power
+4.2V
0V
Function
Regulator
GND
Other
Please be sure to connect.
Please be sure to connect.
Table 1 . Set up the Power Supply Line
2) Set up the evaluation mode and jumper pins
See the followings
3) Power on
The AK4678 should be reset once bringing SW1 (PDN) “L” upon power-up.
[2]
Evaluation Mode
1). External Slave Mode
(a) Evaluation of A/D using DIT of AK4118A
(b) Evaluation of D/A using DIR of AK4118A <default>
(c) Evaluation of Loop-back using AK4118A
(d) All interface signals including master clock are fed externally
2). External Master Mode
(a) Evaluation of A/D using DIT of AK4118A
(b) Evaluation of D/A using DIR of AK4118A
(c) Evaluation of Loop-back using AK4118A
(d) All interface signals including master clock are fed externally
3). PLL Slave Mode
(a) All interface signals including master clock are fed externally
4). PLL Master Mode
(a) All interface signals including master clock are fed externally
5). PCM I/F A&B
(a) All interface signals including master clock are fed externally
[3] Jumper Pin and SW Setting
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[2]
Evaluation Mode
(2-1). External Slave Mode
In case of AK4678 evaluation using AK4118A, it is necessary to correspond to audio interface format for
AK4678 and AK4118A. Audio Interface Format of AK4678 refer to datasheet and Audio Interface Format of
AK4118A refer to Table 3, respectively.
In the case evaluation mode sets to Ext Slave Mode, AK4118A set to Master Mode and register setup for
AK4678 set to Ext Slave Mode.
Please refer to the data sheet about a register setup of AK4678.
AK4678
AK4118A or PORT3
256fs, 512fs, or
1024fs
MCKI
MCLK
≥ 32fs
BICK
BCLK
1fs
LRCK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 3. EXT Slave Mode
(a) Evaluation of A/D using DIT of AK4118A
X1(X’TAL) and PORT6 (DIT) are used. Nothing should be connected to PORT5 (DIR) and PORT3 (DSP).
MCLK, BICK and LRCK are supplied from AK4118A, AK4678 supplies SDTO to AK4118A.
JP7
MCLK
JP10
BICK_SEL
JP8
LRCK_SEL
JP11
M/S
Figure 4. JP Setting - 1
(b) Evaluation of D/A using DIR of AK4118A <default>
PORT5 (DIR) is used. Nothing should be connected to PORT3 (DSP) and PORT6 (DIT).
MCLK, BICK, LRCK, SDTI are supplied from AK4118A.
JP7
MCLK
JP10
BICK_SEL
JP8
LRCK_SEL
JP9
SDTI_SEL
ADC
JP11
M/S
DIR
Figure 5. JP Setting - 2
(c) Evaluation of Loop-back using AK4118A
X1(X’TAL) is used. Nothing should be connected to PORT5 (DIR), PORT3 (DSP) and PORT6 (DIT).
MCLK, BICK and LRCK are supplied from AK4118A, SDTO is loopback to SDTI.
JP7
MCLK
JP10
BICK_SEL
JP8
LRCK_SEL
JP9
SDTI_SEL
ADC
JP11
M/S
DIR
Figure 6. JP Setting – 3
※AK4118A accepts more than fs=32kHz. When evaluate AK4678 less than fs=32kHz, Please use the other
mode.
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(d) All interface signals including master clock are fed externally
PORT3 (DSP) is used. Nothing should be connected to PORT5 (DIR) and PORT6 (DIT).
MCLK, BICK and LRCK are supplied from PORT3, AK4678 supplies SDTO to PORT3.
JP7
MCLK
JP10
BICK_SEL
JP8
LRCK_SEL
JP9
SDTI_SEL
ADC
JP11
M/S
DIR
Figure 7. JP Setting – 4
(2-2). External Master Mode
In case of AK4678 evaluation using AK4118A, it is necessary to correspond to audio interface format for
AK4678 and AK4118A. Audio Interface Format of AK4678 refer to datasheet and Audio Interface Format of
AK4118A refer to Table 3, respectively.
In the case evaluation mode sets to Ext Master Mode, AK4118A set to Slave Mode and register setup for
AK4678 set to Ext Master Mode.
Please refer to the data sheet about a register setup of AK4678.
AK4678
AK4118A or PORT3
256fs, 512fs, or
1024fs
MCKI
32fs or 64fs
BICK
1fs
LRCK
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 8. EXT Master Mode
(a) Evaluation of A/D using DIT of AK4118A
X1(X’TAL) and PORT6 (DIT) are used. Nothing should be connected to PORT5 (DIR) and PORT3 (DSP).
MCLK is supplied from AK4118A, AK4678 supplies BICK, LRCK and SDTO to AK4118A.
JP7
MCLK
JP10
BICK_SEL
JP8
LRCK_SEL
JP11
M/S
Figure 9. JP Setting – 5
(b) Evaluation of D/A using DIR of AK4118A
PORT5 (DIR) is used. Nothing should be connected to PORT3 (DSP) and PORT6 (DIT).
MCLK and SDTI are supplied from AK4118A, AK4678 supplies BICK and LRCK to AK4118A.
JP7
MCLK
JP10
BICK_SEL
JP8
LRCK_SEL
JP9
SDTI_SEL
ADC
JP11
M/S
DIR
Figure 10. JP Setting – 6
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(c) Evaluation of Loop-back using AK4118A
X1(X’TAL) is used. Nothing should be connected to PORT5 (DIR), PORT3 (DSP) and PORT6 (DIT).
MCLK is supplied from AK4118A, AK4678 supplies BICK and LRCK to AK4118A.
SDTO is loopback to SDTI.
JP7
MCLK
JP10
BICK_SEL
JP8
LRCK_SEL
JP9
SDTI_SEL
ADC
JP11
M/S
DIR
Figure 11. JP Setting – 7
(d) All interface signals including master clock are fed externally
PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT6 (DIT).
MCLK and SDTI are supplied from PORT3, AK4678 supplies BICK, LRCK and SDTO to PORT3.
JP7
MCLK
JP10
BICK_SEL
JP8
LRCK_SEL
JP9
SDTI_SEL
ADC
JP11
M/S
DIR
Figure 12. JP Setting – 8
(2-3). PLL Slave Mode
A reference clock of PLL is selected among the input clocks to BICK pin. The required clock to the
AK4678 is generated by an internal PLL circuit.
AK4678
PORT3(DSP)
MCKI
BICK
32fs or 64fs
BICK
1fs
LRCK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 13. PLL Slave Mode (PLL Reference Clock: BICK pin)
(a) All interface signals including master clock are fed externally
PORT3 (DSP) is used. Nothing should be connected to PORT5 (DIR) and PORT6 (DIT).
BICK, LRCK and SDTI are supplied from PORT3, AK4678 supplies SDTO to PORT3.
This evaluation mode can use various fs by using the internal PLL circuit.
JP7
MCLK
JP10
BICK_SEL
JP8
LRCK_SEL
JP9
SDTI_SEL
ADC
JP11
M/S
DIR
Figure 14. JP Setting – 9
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(2-4). PLL Master Mode
A reference clock of PLL is selected among the input clocks to MCLK pin. The required clock to the AK4678 is
generated by an internal PLL circuit.
AK4678
PORT3(DSP)
MCKI
MCLK
32fs or 64fs
BICK
BICK
1fs
LRCK
11.2896MHz, 12MHz,
12.288MHz, 13MHz,
13.5MHz, 19.2MHz,
24MHz, 25MHz,
26MHz, 27MHz
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 15. PLL Master Mode
(a) All interface signals including master clock are fed externally
PORT3 (DSP) is used. Nothing should be connected to PORT5 (DIR) and PORT6 (DIT).
MCLK and SDTI are supplied from PORT3, AK4678 supplies BICK, LRCK and SDTO to PORT3.
This evaluation mode can use various fs by using the internal PLL circuit.
JP7
MCLK
JP10
BICK_SEL
JP8
LRCK_SEL
JP9
SDTI_SEL
ADC
JP11
M/S
DIR
Figure 16. JP Setting - 10
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(2-5). PCM I/F A&B
The AK4678 has two PCM I/F ports. PCM I/F A, PCM I/F B and Audio I/F can be operated by asynchronous
clock because the AK4678 has four SRCs.
AK4678
PORT2(Baseband)
SYNCA
BICKA
1fs2
SYNC
≥ 16fs2
BICK
SDTOA
SDTI
SDTIA
SDTO
PORT1(Bluetooth)
SYNCB
BICKB
1fs3
16fs3 or ≥ 32fs3
SYNC
BICK
SDTOB
SDTI
SDTIB
SDTO
Figure 17. PCM I/F A and B
(a) All interface signals including master clock are fed externally
When supplying a clock to PCM I/F A, PORT2(Baseband) is used. And PORT1(Bluetooth) is used,
When supplying a clock to PCM I/F B.
Nothing should be connected to PORT3(DSP), PORT5(DIR) and PORT6(DIT).
SYNCA, BICKA and SDTIA are supplied from PORT2, SDTOA outputs from PORT2.
SYNCB, BICKB and SDTIB are supplied from PORT1, SDTOB outputs from PORT1.
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[3]
Jumper Pin and SW Setting
1).Other Jumper pins Setup
[ JP1 (TVDD_SEL) ] : The selection of TVDD.
3.3V
: TVDD is supplied 3.3V.
1.8V
: TVDD is supplied 1.8V.
[ JP2 (Stereo_SEL) ] : The selection of output signal to J1(Mini Jack) connector.
Short
: Differential Output
Open
: Stereo Output
[ JP3 (MPWR1 SEL) ]: The selection of Mic-power1.
SHORT
: MIC-power1 is supplied.
OPEN
: MIC-power1 is not supplied. (Default)
[ JP4 (MPWR2 SEL) ]: The selection of Mic-power2.
SHORT
: MIC-power2 is supplied.
OPEN
: MIC-power2 is not supplied. (Default)
[ JP5 (RIN_SEL) ]: The selection of input signal from J3(Mini Jack) connector to AK4678 (RIN ch).
RIN1
: Connect to RIN1/IN1- pin. (Default)
RIN2
: Connect to RIN2/IN2- pin.
RIN3
: Connect to RIN3/IN3- pin.
RIN4
: Connect to RIN4/IN4- pin.
[ JP6 (LIN_SEL) ]: The selection of input signal from J3(Mini Jack) connector to AK4678 (LIN ch).
LIN1
: Connect to LIN1/IN1+ pin. (Default)
LIN2
: Connect to LIN2/IN2+ pin.
LIN3
: Connect to LIN3/IN3+ pin.
LIN4
: Connect to LIN4/IN4+ pin.
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2).SW Setting
Upper-side is “ON(H)” and lower-side is “OFF(L)”.
[S1] (SW DIP-4): AK4118A setting
No.
1
2
3
4
Name
DIF2
DIF1
DIF0
OCKS1
ON (“H”)
OFF (“L”)
AK4118A Audio Format Setting
See Table 3
AK4118A Master Clock Setting : See Table 4
Default
ON
OFF
OFF
OFF
Table 2. Mode Setting for AK4678 and AK4118A
DIF2
L
L
L
L
H
H
H
H
DIF1
L
L
H
H
L
L
H
H
DIF0
L
H
L
H
L
H
L
H
DAUX
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
SDTO
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
LRCK
H/L
O
H/L
O
H/L
O
H/L
O
H/L
O
L/H
O
H/L
I
L/H
I
BICK
64fs
64fs
64fs
64fs
64fs
64fs
64-128fs
64-128fs
O
O
O
O
O
O
I
I
Default
Table 3. Setting for AK4118A Audio Interface Format
OCKS1
L
H
MCKO1
256fs
512fs
X’tal
256fs
512fs
Default
Table 4. Setting for AK4118A Master Clock
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„ Board Control
It is possible to control AKD4678-B via general USB port. Connect cable with the U7 (USB Connector) on board
and PC.
Control software is packed with this board. The software operation sequence is included in the evaluation board
manual.
And it is possible to control AKD4678-B via the printer port (parallel port) of IBM-AT compatible PC.
PORT4(CTRL) with PC by 10 wire flat cable packed with the AKD4678-B.
Connect
PC
2
10 wire
flat cable
10pin
Connector
CSN
SCL/CCLK
SDA/CDTI
1
AKD4678-B
10pin Header
Figure 18. Connection of 10 wire flat cable
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„ Analog Input/Output Circuits
(1) Input circuit
Figure 19. Input Circuit
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(2) Output circuit
1.
HP Output Circuit
2.
Line Output Circuit
3.
Speaker Output Circuit
Figure 20 . HP Output Circuit
Figure 21 .Line Output Circuit
Figure 22 . Speaker Output Circuit
4.
Receiver Output Circuit
Figure 23. Receiver Output Circuit
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Control Soft Manual
■ Evaluation Board and Control Soft Settings
1.Set an evaluation board properly.
2. Connect Evaluation board to PC with USB cable.
USB control is recognized as HID (Human Interface Device) on the PC.
When it can not be recognized correctly please Connect Evaluation board to PC with USB cable.
3. Proceed evaluation by following the process below.
4. Start up the control program following the process above.
Note 1. After the evaluation board’s power is supplied, the AK4678 must be reset once bring SW1 (PDN) “L” to
“H”, and Click [Dummy Command] button.
5. The operation screen is shown below.
Figure 24. Window of Control Soft
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■ Function Button
[ MIC_Input_Record ]
When [MIC_Input_Record] button is clicked,
[LIN2/RIN2 → MICL/R → ADCL/R → ALC → Audio I/F → SDTO] sequence is set up.
Set up the evaluation board is referred to (2-1) External Slave Mode (a) Evaluation of A/D using DIT of AK4118A.
or (d) All interface signals including master clock are fed externally.
[ HP_Out ]
When [HP_Out] button is clicked,
[SDTI → Audio I/F → 5-band EQ → DATT-A → DACL/R → HPL/HPR] sequence is set up.
Set up the evaluation board is referred to (2-1) External Slave Mode (b) Evaluation of D/A using DIR of AK4118A.
or (d) All interface signals including master clock are fed externally.
[ SPK_Out ]
When [SPK_Out] button is clicked,
[SDTI → Audio I/F → 5-band EQ → DATT-A → DACL/R → SPP/SPN] sequence is set up.
Set up the evaluation board is referred to (2-1) External Slave Mode (b) Evaluation of D/A using DIR of AK4118A.
or (d) All interface signals including master clock are fed externally.
[ Stereo_Line_Out ]
When [Stereo_Line_Out] button is clicked,
[SDTI → Audio I/F → 5-band EQ → DATT-A → DACL/R → LOUT/ROUT] sequence is set up.
Set up the evaluation board is referred to (2-1) External Slave Mode (b) Evaluation of D/A using DIR of AK4118A.
or (d) All interface signals including master clock are fed externally.
[ PCMIF_AtoB ]
When [PCMIF_AtoB] button is clicked,
[SDTIAÆPCM I/F AÆSRCAIÆDATT-CÆMIX3ÆPCM I/F BÆSDTOB &
SDTIBÆPCM I/F BÆBIVOLÆMIX2AÆMIX2CÆSRCAOÆPCM I/F AÆSDTOA] sequence is set up.
Set up the evaluation board is referred to
(2-5) PCM I/F A&B (a) All interface signals including master clock are fed externally.
[ RCV_Out ]
When [RCV_Out] button is clicked,
[SDTIA→PCM I/F A→SRCAI→DATT-B→MIX1R→5-Band EQ→DATT-A→DACR→RCP/RCN]
sequence is set up.
Set up the evaluation board is referred to
(2-5) PCM I/F A&B (a) All interface signals including master clock are fed externally.
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■Operation Overview
CODEC Function
Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs.
Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the
switching tab window. Refer to the Dialog Boxes for details of each dialog box setting.
1.
[Port Reset]: For when connecting to USB Cable.
Click this button after the control soft starts up when connecting USB I/F.
2.
[Write Default]: Register Initializing
When the device is reset by a hardware reset, use this button to initialize the registers.
3.
[All Write]: Executing write commands for all registers displayed.
4.
[All Read]: Executing read commands for all registers displayed.
5.
[Save]: Saving current register settings to a file.
6.
[Load]: Executing data write from a saved file.
7.
[All Reg Write]: “All Reg Write” dialog box is popped up.
8.
[Data R/W]: “Data R/W” dialog box is popped up.
9.
[Sequence]: “Sequence” dialog box is popped up.
10. [Sequence(File)]: “Sequence(File)” dialog box is popped up.
11. [Read]: Reading current register settings and display on to the Register area on the right of the main window.
This is different from [All Read] button, it does not reflect to a register map, only displaying
hexadecimal.
12. [Dummy Command]: Write a dummy command
After the evaluation board power is supplied, the AK4678 must be reset once bring SW1
(PDN) “L” to “H”, and then the [Dummy Command] button should be clicked once to
reset the register setting of the AK4678.
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1. [Function]: Function control
This tab is for function control.
Each operation is executed by the function buttons on the left side of the screen.
Figure 25. Window of [Function]
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1-1. Power Management Setting
When [Power Management Setting] button is clicked, the window as shown in Figure 26 opens.
This window is for Power Management Setting.
Refer to the datasheet for register settings of the AK4678.
Figure 26. Window of [Power Management Setting]
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1-2. Audio Mode Setting
When [Audio Mode] button is clicked, the window as shown in Figure 27 opens.
This window is for Audio Mode Setting.
Refer to the datasheet for register settings of the AK4678.
Figure 27. Window of [Audio Mode Setting]
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1-3. System Clock, Audio I/F Setting
When [PLL Setting] button is clicked, the window as shown in Figure 28 opens.
This window is for System Clock and Audio I/F Setting
Refer to the datasheet for register settings of the AK4678.
Figure 28. Window of [PLL Setting]
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1-4. MIC Setting
When [MIC Setting] button is clicked, the window as shown in Figure 29 opens.
This window is for MIC Setting.
Refer to the datasheet for register settings of the AK4678.
Figure 29. Window of [MIC Setting]
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1-5. ALC Setting
When [ALC Setting] button is clicked, the window as shown in Figure 30 opens.
This window is for ALC setting.
Refer to the datasheet for register settings of the AK4678.
Figure 30. Window of [ALC Setting]
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1-6. Volume Setting
When [Volume Setting] button is clicked, the window as shown in Figure 31 opens.
This window is for Volume setting.
Refer to the datasheet for register settings of the AK4678.
Figure 31. Window of [Volume Setting]
Register map
Volume Control by Pull-down Menu
Slide bar is moved to
the selected value.
Figure 32. Volume Control by Pull
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The volume can be controlled by slide bars.
Register writing is made on every slide bar move.
After the volume slide is moved, it is reflected on to the register map and data writing dialog box.
The volume can also be changed by writing a value in a dialog box. The slide bar is moved to the value that written in
the dialog box. Use the mouse or arrow keys on the keyboard for small adjustments.
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1-7. Digital Filter Setting
When [Digital Filter Setting] button is clicked, the window as shown in Figure 33 opens.
Refer to the datasheet for register settings of the AK4679A.
A calculation of a coefficient of Digital Programmable Filters such as HPF / LPF and EQ filters,
a register writing and a frequency response checking of HPF / LPF and EQ filter can be made.
Figure 33. Window of [Digital Filter Setting]
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1-7-1. Parameter Setting
(1) Please set a parameter of each Filter.
Parameter
Function
Setting Range
Sampling Rate
HPF
Sampling frequency (fs)
7350Hz ≤ fs ≤ 48000Hz
Cut Off Frequency
High pass filter cut off frequency
fs/1000 ≤ Cut Off Frequency
≤ (0.497 * fs)
HPF2
Cut Off Frequency
Low pass filter cut off frequency
fs/1000 ≤ Cut Off Frequency
≤ (0.497 * fs)
FIL3
Cut Off Frequency
FIL3 cut off frequency
Gain
Gain
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
-10≤ Gain < 0
EQ for Gain Compensation(EQ0)
Pole Frequency
EQ0 Pole Frequency
Zero-point Frequency
EQ0 Zero-point Frequency
Gain
Gain
3 Band Equalizer
EQ1-3 Center Frequency
EQ1-3 Band Width
EQ1-3 Gain
EQ1-3 Center Frequency
EQ1-3 Band Width (Note 2)
EQ1-3 Gain
(Note 3)
DAC 5-Band Equalizer
Center Frequency
LPF1 EQ1-5 HPF1 Center Frequency
Band Width
Gain
EQ2-4 Band Width
LPF1 EQ1-5 HPF1 Gain
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
-20≤ Gain < 12
0Hz ≤ Center Frequency < (0.497 * fs)
1Hz ≤ Band Width < (0.497 * fs)
-1≤ Gain < 3
fs/1000 ≤ Cut Off Frequency
< (0.497 * fs)
1Hz ≤ Band Width < (0.497 * fs)
-12 ≤ Gain ≤ 12
Note 2. Gain difference is a bandwidth of 3dB from center frequency.
Note 3. When the gain is smaller than 0, EQ becomes a notch filter.
(2) “HPFAD Enable”, “HPF Enable” , “LPF Enable” “FIL3 Enable”, “EQ0 Enable”, “EQ1”, “EQ2”, “EQ3”.
Please set ON/OFF of Filter with a check button. When checked it, Filter becomes ON. When “Notch Filter
Auto Correction” is checked, perform automatic correction of the center frequency of the notch filter is executed.
Figure 34. Filter ON/OFF setting button
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1-7-2. Calculation of Register
Register set value is displayed when push a [Register Setting] button. When a value out of a setting range is set,
error message is displayed, and a calculation of register setting is not carried out.
Figure 35. Register setting calculation result
Followings are the cases when a register set value is updated.
(1) When [Register Setting] button was pushed.
(2) When [Frequency Response] button was pushed.
(3) When [UpDate] button was pushed on a frequency characteristic indication window.
(4) When set ON/OFF of a check button “Notch Filter Auto Correction”
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1-7-3. Indication of Frequency Characteristic
Frequency characteristic is displayed when push a [F Response] button. Then, a register set point is also updated.
Change “Frequency Range”, and indication of a frequency characteristic is updated when push a [UpDate] button.
Figure 36. Frequency Characteristic Indication Result
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1-7-4. Filter Setting
(a) 3-band Equalizer, DAC 5-band Equalizer
The filter setting can be executed by dragging the number to each equalizers in the mouse.
Band Width can be adjusted in the operation of Center Frequency, K and Gain right-clicking in the operation of
the left-click.
After operating the mouse ,
the value of the center frequency
and the gain is updated.
The number is selected ,
the movement operation is done
while left-clicking.
Figure 37. Filter Setting (Right-clicking operation)
After operating the mouse ,
the value of the bandwidth is updated.
Figure 38. Filter Setting (Left-clicking operation)
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The number is selected ,
the movement operation is done
while left-clicking.
After operating the mouse ,
the value of the center frequency
and the gain is updated.
Figure 39. Filter Setting (Gain-Control operation)
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1-8. DRC Setting
When [DRC Setting] button is clicked, the window as shown in opens.
This window is for DRC setting.
Refer to the datasheet for register settings of the AK4678.
Figure 40. Window of [DRC Setting]
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1-8-1. Parameter Setting
(1)
Please set a parameter of each Filter and Gain.
Parameter
Function
Sampling Rate
Noise Suppression
LPF
Sampling frequency (fs)
HPF
High pass filter cut off frequency
Gain
Threshold Level
Reference Value Setting
Noise Suppression Threshold Low/High Level
7350Hz ≤ fs ≤ 48000Hz
Low pass filter cut off frequency
Dynamic Volume Control
Low Frequency Range
LPF
Low pass filter cut off frequency
Volume Control
Setting Range
Volume point setting
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
-9 ≤ Gain < -54 (Note 4)
-82.5≤ Threshold Level < -36.0
(Note 5)
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
-70.5≤ Gain < 0 (Note 6)
Middle Frequency Range Low Frequency Range
LPF
Low pass filter cut off frequency
HPF
High pass filter cut off frequency
Volume Control
Volume point setting
High Frequency Range
HPF
High pass filter cut off frequency
Volume Control
Volume point setting
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
-70.5≤ Gain < 0
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
-70.5≤ Gain < 0
Note 4. Gain step of “Reference Value of Noise Suppression” is 3dB.
Note 5. Gain step of “Threshold level Value of Noise Suppression” is 3dB.
Note 6. Gain step of “Volume point Value of Dynamic Volume Control” is 3dB.
(2) When “NSLPF” button is checked, the filter is enabled. When “NSHPF” button is checked, the filter is enabled.
When “DVLC Enable” button is checked, the filters of Low/Middle/High Range are enabled according to setting
of pull-down menu. When “fc Auto” button is checked, the frequency response of low frequency and high
frequency ranges becomes flat automatically.
Figure 41. Filter ON/OFF setting button
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1-8-2. Frequency Response
Frequency characteristic is displayed when pushing a [F Response] button. Then, a register set point is also updated.
When changing “Frequency Range”, frequency characteristic indication window is updated after [UpDate] button is
pushed.
Figure 42. A frequency characteristic indication result
Followings are the cases when a register set value is updated.
(1).
(2).
(3).
(4).
When [Register Setting] button was pushed.
When [Frequency Response] button was pushed.
When [UpDate] button was pushed on a frequency characteristic indication window.
When set ON/OFF of a check button “fc Auto”
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1-8-3. Filter Setting
The filter setting can be executed by checking the “NSLPF”, “NSHPF” or “DVLC Enable” button.
Band width can be adjusted in the operation of Center Frequency in the operation of the left-click and Filter selecting
in the [DRC Setting] window.
After operating the mouse ,
the value of the cut-off frequency
is updated.
The filter name is selected ,
the movement operation is done
while left-clicking.
Figure 43. Filter Setting (Left-clicking operation)
The filter mode is selected ,
the movement operation is done.
Figure 44. Filter Setting (Filter Selecting)
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1-8-4. Noise Suppression
Noise Suppression Control is displayed when “NS” button is checked after [DRV Curve] button is pushed.
Then, a register set point is also updated.
Noise Suppression Threshold Low Level and Reference Value can be adjusted by the left-click.
Noise Suppression
Threshold Low Level
Reference Value
Register map
After “Threshold Low Level” point is moved,
setting value is reflected.
The “Threshold Low Level” point is selected,
the movement operation is done while left- clicking.
Figure 45. Noise Suppression Setting
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1-8-5. Dynamic Volume Control
Dynamic Volume is displayed when “LOW”, ”MIDDLE” or “HIGH” buttons in “DVLC” is checked after [DRV
Curve] button is pushed.
Then, a register set point is also updated.
Dynamic Volume Control Points can be adjusted by the left-click.
Select the frequency range
for DVLV curve。
Red: LOW
Blue: MIDDLE
Green: HIGH
Register map
DVLC volume control point
in Low range
After volume control point is moved,
setting value is reflected.
The volume control point is selected,
the movement operation is done
while left-clicking.
Figure 46. DVLC Curve Setting
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1-8-6. Dynamic Range Control
Dynamic Range Control is displayed when “DRC” button is checked after [DRV Curve] button is pushed. Then, a
register set point is also updated.
Dynamic Range Compression Level can be adjusted by the left-click.
Register map
After “DRC Compression Level” is moved,
setting value is reflected.
The “DRC Compression Level” is selected, the
movement operation is done while left- clicking.
Figure 47. Dynamic Range Control Setting
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2. [REG]: Register Map
This tab is for a register writing and reading.
Each bit on the register map is a push-button switch.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray)
Gray out registers are Read Only registers. They can not be controlled.
The registers which is not defined in the datasheet are indicated as “---”.
Figure 48. Window of [REG]
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[Write]: Data Writing Dialog
It is for when changing two or more bits on the same address at the same time.
Click [Write] button located on the right of the each corresponded address for a pop-up dialog box.
When checking the checkbox, the register will be “H” or “1”, when not checking the register will be “L” or ”0”.
Click [OK] to write setting value to the registers, or click [Cancel] to cancel this setting.
Figure 49. Window of [Register Set]
[Read]: Data Read
Click [Read] button located on the right of the each corresponded address to execute register reading.
After register reading, the display will be updated regarding to the register status.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray)
Please be aware that button statuses will be changed by Read command.
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3. [Tool]: Test tool
This tab screen is for evaluation testing tool.
Click buttons for each testing tool.
Figure 50. Window of [Tool]
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[Repeat Test]: Repeat Test Dialog
Click [Repeat Test] button to open repeat test setting dialog box.
A repetition write test of the setting register files can be applied.
Figure 51. Window of [Repeat Test]
[ Start ]
[ Close ]
[ Address ]
[ Start Data ]
[ End Data ]
[ Step ]
[ Repeat Count ]
[ Up and Down ]
: When [Start] button is clicked,
The dialog of saving test data settings as a file is shown.
Please set the file name.
After setting save file, repeat test is started.
:
:
:
:
:
:
:
Close this dialog and finish the process.
Input data address in hexadecimal numbers for data writing.
Input start data address in hexadecimal numbers for data writing.
Input finish data address in hexadecimal numbers for data writing.
Rewrite data at intervals of step.
Set the count of repetition write test.
Set the data flow at 1 count.
Click [OK] to write setting value to the registers, or click [Cancel] to cancel this setting.
・Click [OK]
: After rewrite the intervals of step from Start Data to End Data,
Rewrite the intervals of step from End Data to Start Data.
[Execution example]
Start Data = 00, End Data = 05, Step = 1, [ ]…Test Flow of 1 count.
Data Flow
: [00→01→02→03→04→05→05→04→03→02→01→00]×Repeat Count
・Click [Cancel]
: Rewrite the intervals of step from Start Data to End Data.
[Execution example]
Start Data = 00, End Data = 05, Step = 1, [ ]…Test Flow of 1 count
Data Flow
: [00→01→02→03→04→05]×Repeat Count
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[ Sampling Frequency ] : Select the samplimg frequency 44.1kHz or 48kHz.
[ Count ]
: Show the count under test execution.
[ Lch Level ]
: Show the Lch Level under test execution.
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[Loop Setting] : [Loop] Dialog
Click [Loop Setting] button to open loop setting dialog box.
Write test of the setting register files can be applied.
Figure 52. Window of [Loop]
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„
Dialog Boxes
[All Reg Write]
Click [All Reg Write] button in the main window to open register setting files.
Register setting files saved by [SAVE] button can be applied.
Figure 53. Window of [All Register Write]
[Open (left)]
[Write]
[Write All]
[Help]
[Save]
[Open (right)]
[Close]
: Selecting a register setting file (*.akr).
: Executing register writing.
: Executing all register writings.
Writings are executed in descending order.
: Help window is popped up.
: Saving the register setting file assignment. The file name is “*.mar”.
: Opening a saved register setting file assignment “*. mar”.
: Closing the dialog box and finish the process.
*Operating Suggestions
(1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be
stored in the same folder.
(2) When register settings are changed by [Save] button in the main window, re-read the file to reflect new
register settings.
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[Data R/W]
Click the [Data R/W] button in the main window for data read/write dialog box.
Data write is available to specified address.
Figure 54. Window of [Data Read/Write]
Address Box
Data Box
Mask Box
: Input data address in hexadecimal numbers for data writing.
: Input data in hexadecimal numbers.
: Input mask data in hexadecimal numbers.
This is “AND” processed input data.
[Write]
[Close]
: Writing to the address specified by “Address” box.
: Closing the dialog box and finish the process.
Data writing can be cancelled by this button instead of [Write] button.
*The register map will be updated after executing [Write] or [Read] commands.
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[Sequence]
Click [Sequence] button to open register sequence setting dialog box.
Register sequence can be set in this dialog box.
Figure 55. Window of [ Sequence ]
Sequence Setting
Set register sequence by following process bellow.
(1)Select a command
Use [Select] pull-down box to choose commands.
Corresponding boxes will be valid.
< Select Pull-down menu >
· No_use
: Not using this address
· Register
: Register writing
· Reg(Mask)
: Register writing (Masked)
· Interval
: Taking an interval
· Stop
: Pausing the sequence
· End
: Finishing the sequence
(2)Input sequence
[Address]
: Data address
[Data]
: Writing data
[Mask]
: Mask
[Data] box data is ANDed with [Mask] box data. This is the actual writing data.
When Mask = 0x00, current setting is hold.
When Mask = 0xFF, the 8bit data which is set in the [Data] box is written.
When Mask =0x0F, lower 4bit data which is set in the [Data] box is written.
Upper 4bit is hold to current setting.
[ Interval ]
: Interval time
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Valid boxes for each process command are shown bellow.
· No_use
· Register
· Reg(Mask)
· Interval
· Stop
· End
: None
: [Address], [Data], [Interval]
: [Address], [Data], [Mask], [Interval]
: [Interval]
: None
: None
Control Buttons
The function of Control Button is shown bellow.
[Start]
[Help]
[Save]
[Open]
[Close]
: Executing the sequence
: Opening a help window
: Saving sequence settings as a file. The file name is “*.aks”.
: Opening a sequence setting file “*.aks”.
: Closing the dialog box and finish the process.
Stop of the Sequence
When “Stop” is selected in the sequence, processing is paused and it starts again when [Start] button is clicked.
Restarting step number is shown in the “Start Step” box. When finishing the process until the end of sequence,
“Start Step” will return to “1”.
The sequence can be started from any step by writing the step number to the “Start Step” box.
Write “1” to the “Start Step” box and click [Start] button, when restarting the process from the beginning.
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[Sequence(File)]
Click [Sequence(File)] button to open sequence setting file dialog box.
Those files saved in the “Sequence setting dialog” can be applied in this dialog.
Figure 56. Window of [ Sequence(File) ]
[Open (left)]
[Start]
[Start All]
[Help]
[Save]
[Open(right)]
[Close]
: Opening a sequence setting file (*.aks).
: Executing the sequence setting.
: Executing all sequence settings.
Sequences are executed in descending order.
: Pop up the help window.
: Saving sequence setting file assignment. The file name is “*.mas”.
: Opening a saved sequence setting file assignment “*. mas”.
: Closing the dialog box and finish the process.
*Operating Suggestions
(1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog
“*.mas” should be stored in the same folder.
(2) When “Stop” is selected in the sequence the process will be paused and a pop-up message will appear. Click
“OK” to continue the process.
Figure 57. Window of [ Sequence Pause ]
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Measurement Result
[Measurement condition]
• Measurement Unit
• MCLK
• BICK
• fs
• Power Supply
• Band Width
• Measurement Mode
• Temperature
: Audio Precession System Two Cascade
: 11.2896MHz
: 64fs
: 44.1kHz
: AVDD=DVDD=PVDD=TVDD=1.8V, SVDD=4.2V
: 22Hz ~ 20kHz
: External Slave Mode
: Room Temperature
[Measurement Result]
1. ADC
a). LIN1, RIN1 pins, MGNL=MGNR=+18dB
Parameter
Result
Lch / Rch
S/(N+D) (-1dBFS Input)
79.4
/
79.7
dB
D-Range (-60dBFS Input, A-weighted)
87.2
/
87.2
dB
S/N (A-weighted)
87.5
/
87.6
dB
106.8
/
104.8
dB
Interchannel Isolation
Unit
b). LIN2, RIN2 pins, MGNL=MGNR=0dB
Parameter
Result
Lch / Rch
S/(N+D) (-1dBFS Input)
81.0
/
81.4
dB
D-Range (-60dBFS Input, A-weighted)
92.3
/
92.4
dB
S/N (A-weighted)
93.4
/
93.4
dB
110.7
/
103.5
dB
Interchannel Isolation
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2. DAC
a) Line out (LOUT/ROUT pins, LVL=0dB, RL=20kΩ)
Parameter
Result
Lch / Rch
S/(N+D) (0dBFS Input)
81.6
/
81.0
dB
S/N (A-weighted)
92.3
/
92.3
dB
Interchannel Isolation
91.8
/
92.3
dB
Unit
b) Mono Line Out (LOP/LON pins, LVL=0dB, RL=20kΩ)
Parameter
Result
Unit
S/(N+D) (0dBFS Input)
73.5
dB
S/N (A-weighted)
95.8
dB
c) Mono Receiver Out (RCP/RCN pins, RCVG=-6dB, RL=32Ω)
Parameter
Result
Unit
S/(N+D) (0dBFS Input)
58.8
dB
S/(N+D) (0dBFS Input, RCVG=0dB)
37.7
dB
S/N (A-weighted)
95.1
dB
-100.8
dBV
Output Noise Level (RCVG=-9dB)
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d) HP Out (HPL/HPR pins, HPG=0dB, RL=32Ω)
Result
Lch / Rch
Parameter
HPG=-4dB
9.3
/ 9.6
mW
Output Power (RL=32Ω)
HPG=0dB
23.4
/
24.2
HPG=-4dB
17.6
/
18.9
mW
Output Power (RL=16Ω)
S/(N+D) (RL=32Ω)
S/(N+D) (RL=16Ω)
Unit
HPG=0dB
38.1
/
41.3
HPG=-4dB
70.1
/
69.5
HPG=0dB
42.5
/
46.5
HPG=-4dB
64.7
/
64.0
HPG=0dB
20.2
/
20.1
95.0
/
94.7
-107.1
/
-107.1
99.6
/
103.0
dB
dB
S/N (A-weighted)
Output Noise Level
(A-weighted, HPG=-14dB)
Interchannel Isolation
dB
dBV
dB
e) SPK Out (SPP/SPN pins, SPKG=-6dB, RL=8Ω+10uH)
Parameter
Output Power
Result
SVDD=5.0V THD+N=10%
SPKG=-3dBFS
SVDD=4.2V THD+N=10%
SPKG=-3dBFS
SVDD=4.2V THD+N=1%
SPKG=0dBFS
SVDD=3.7V THD+N=1%
SPKG=-6dBFS
Unit
1.53
1.07
W
0.87
0.67
Output Voltage (-3dBFS Input)
5.48
Vpp
S/(N+D) (SVDD=3.7V, Po=0.35W)
58.3
dB
Output Noise Level (A-Weighted)
-82.3
dBV
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REVISION HISTORY
Date
Manual
Board
(YY/MM/DD)
Revision
Revision
12/04/19
KM107900
1
Reason
Page
Contents
First Edition
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products.
You are fully responsible for the incorporation of these external circuits, application circuits, software and other
related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by
you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of
any patent, intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency
exchange, or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to
function or perform may reasonably be expected to result in loss of life or in significant injury or damage to
person or property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and
the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from
any and all claims arising from the use of said product in the absence of such notification.
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5
4
3
2
1
J3
LIN/RIN
+
1
3
OUT
C4
0.1u
DVDD
C5
0.1u
+
C26
100u
R2 0
VSS1
AVDD
D
RIN4
RIN3
RIN2
RIN1
IN
C1
100u
LIN4
LIN3
LIN2
LIN1
1
VDD
R1 5.1
GND
REG1
2
SVDD
T1
TA48018BF
JP6
LIN-SEL
R3 0
JP5
RIN-SEL
D
PVDD
JP1
TVDD-SEL
TVDD
R36 2.2k
TEST9
IN1-
TEST10
IN1+
R33
C18 1u
DMCLK
2.2k
R32
1M
+
B5
C49
10u
VSS2
TVDD
R30
1M
VEE
VSS2
PVDD
C7
C
C6
C15
2.2u
C31
10u
+
C7
0.1u
+
DVDD
9
7 SDTIB
5 SYCNB
3 BICKB
1
VSS1
CNA
B6
A7
2.2u
CNB
A6
CPB
RIN1/IN1-
G7
F7
LIN1/IN1+
F4
E5
MPWR1
RIN3
F6
G4
E6
E7
LIN3
VSS1
R31
1M
C16
E1
DVDD
R38
(Open)
PORT1
SDTOB 10
8
6
4
2
TVDD
RIN2/IN2-
C6
0.1u
LIN2/IN2+
C28
10u
MPWR2
A5
TVDD
C
RIN4
LIN4
D5
D4
2.2u
B7
C17
CPA
TEST8 DMDAT
JP3 MP1-SEL
C20 1u
C21 1u
2.2k
LIN1
RIN1
TEST11
IN2R35
LIN2
RIN2
JP4 MP2-SEL
C22 1u
C23 1u
AVSS
C24 1u
2.2k
TEST12
IN2+
TEST13 IN3-
TEST14 IN3+
D3V
10u
+ C27
100u
TEST15 IN4-
C3
0.1u
C25 1u
GND
OUT
2
TEST16 IN4+
1
GND1
L1
1
GND
IN
C2
0.1u
R34
3.3V
C19 1u
T2
TA48033BF
TEST7
1.8V
AVDD
G5
C12
0.1u
C30
10u
TEST6
AVDD
AVDD
+
R4
B1
51
SDTIB
VSS1
R24
100k
VCOM
Bluetooth
R5
B2
51
U1
A1
51
BICKB
C2
51
HPR
HPL
AK4678
R26
100k
R7
C13
1u
ROUT/LON
SDTOB
LOUT/LOP
R53
1M
D7
RCN
R8
51
B3
SDTO
R9
51
A4
LRCK
R10
51
C3
R11
51
MCKI
R12
51
A2
15
VSS1
2
J2
C51 1u
E3
C10
R28
0.22u
15
HP
2
TEST4
RCN
G3
TEST3
RCP
F3
J1
3
1
C50 1u
E4
R63
22k
R64
22k
LineOUT
JP2
Stereo
B
VSS1
SDTO
C9
LRCK
SPFIL
BICK
R29
0.22u
3
1
SDTI
RCP
A3
C11
D6
B
SDTI
TEST5
GND
SYNCB
R25
100k
R6
R54
1M
G6
F5
C14
0.1u
PVDD
E2
BICK
2.2n
VSS3
F2
VSS1
SVDD
C8+
0.1u
C29
10u
G1
SPP
F1
G2
SPN
SDTOA
C1
BICKA
D2
D3
SDTIA
SDA
D1
B4
C5
SCL
PDN
C4
SYNCA
SVDD
MCKI
VSS3
R60
(Open)
PDN
SCL
R21
100k
9
7SDTIA
5SYCNA
3BICKA
1
R37
TVDD
R19 51
R18 51
R20
100k
SDA
R17 51
R16 51
R15 51
A
R14 51
R13
R43
470
51
TVDD
TEST1
SPN
TEST2
SPP
A
R22
100k
AVSS
VSS1
VSS2
VSS3
(Open)
SDTOA 10
8
6
4
2
-53-
PORT2
Baseband
Title
AKD4678-B
Size
Date:
5
4
3
Document Number
Rev
A2
2
0
AK4678
Tuesday, February 07, 2012 Sheet
1
1
of
3
5
4
3
2
1
D
D
U4
DSP
C41
10u
JP10
BICK
26
27
C
28
2
X1
11.2896MHz
29
1
U3
XTO
32
33
15
16
NC/GP1
13
14
15
TX0/GP2
TVDD
7
RP1
47k
6
5
4
3
C32
0.1u
1OCKS1
2 DIF0
3 DIF1
4 DIF2
S1
SW DIP-4
8
7
6
5
C33
0.47u
C35 10u
2
3
C36
0.1u
5
IN
GND OUT
TC7SG07FE
4
PORT5
R46 470
R42 470
1
B
C34 0.1u
R41 470
U5
NC VCC
H (ON)
L(OFF)
RX3
VSS4
RX2
1
48
47
46
TEST1
45
RX1
IPS0/RX4
2
+
SW1
RESET
NC
INT0
R45
10k
1
H
3
10k
R40
DIF0/RX5
OCKS0/CSN/CAD0
37
R44
10k
2
10k
R39
L
PC-SCL
TEST2
OCKS1/CCLK/SCL
INT1
K
D1
HSU119
A
B
CTRL
16
CM1/CDTI/SDA
44
9
35
SN74AVC4T245PW
9
7 SCL
5 SDA
3 SDA(ACK)
1
8
D3V
C48
0.1u
D3V
PORT4
C
14
36
10
8
6
4
2
DIF1/RX6
NC
GND GND
CM0/CDTO/CAD1
43
8
VCCA
VCCB
10
9
10
RX0
1
C47
0.1u
11
1
2
3
4
11
VSS3
2DIR 2OE
VSS1
42
1DIR 1OE
PDN
41
2A2 2B2
DIF2/RX7
12
12
34
TVDD
XTI
VCOM
3
2A1 2B1
IPS1/IIC
U2
AK4118A
R
2
1A2 1B2
TX1/GP3
P/SN
40
SDTO
7
17
DAUX
AVDD
6
18
XTL0
39
5
SDA
31
19
MCKO2
38
SCL
13
VIN/GP0
XTL1
C44 5p
1A1 1B1
C40
0.1u
BICK
C43 5p
30
BOUT/GP4
SDTO
COUT/GP5
25
DIR
UOUT/GP6
LRCK
ADC
C39
10u
C42
0.1u
20
+
JP8 LRCK
JP9
SDTI-SEL
4
VCC
IN
JP7 MCLK
D3V
C46
0.1u
+
GND GND
VOUT/GP7
16
9
SN74AVC4T245PW
PDN
GND
2
3
OPT-OUT
VCCA
VCCB
8
PORT6
1
C38
0.1u
14
2DIR 2OE
1
R51(Open)
PORT3
2
4
6
8
10
21
C45
0.1u
1
3
5
7
9
15
1DIR 1OE
3
JP11
Master
TVDD
10
2A2 2B2
2
R52 10k
11
2A1 2B1
MCLK
BICK
LRCK
SDTI
DVDD
LRCK
7
51
51
51
51
22
6
R47
R48
R49
R50
D3V
12
1A2 1B2
VSS2
BICK
13
1A1 1B1
MCKO1
5
24
4
SDTI
23
MCKI
2
D3V
C52
0.1u
1
2
C37
0.1u
OUT
GND
3
1
L2 (short)
VCC
OPT-IN
PC-SDA
D3V
PC-SDA(ACK)
A
A
-54-
Title
AKD4678-B
Size
Document Number
Date:
5
4
3
2
Rev
0
DIR/DIT
A2
Monday, May 30, 2011
1
Sheet
2
of
3
5
4
3
2
1
D
D
T3
TA48033BF
IN
GND
C59
1u
C54
2.2u
R61
OUT
4.7k
C
17
16
15
14
11
10
9
8
38
39
40
41
2
3
4
5
32
35
36
R55
R56
C57
0.1u
C58
0.1u
0
0
42
43
44
1
VDD0
6
VSS0
VDD1
7
C56
10u
28
C55
10u
VSS1
VDD
MCLR
PGD
PGC
GND
B
U7
1
VBUS 2
D- 3
D+ 4
ID 5
GND
USB Connector
+
JP12
1
2
3
4
5
PIC
+
29
C
MCLR_N/Vpp/RE3
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
NC/ICCK/ICPGC
RB3/AN9/CPP2/VPO
NC/ICDT/ICPGD
RB2/AN8/INT2/VMO
NC/ICRST_N/ICVpp
RB1/AN10/INT1/SCK/SCL
NC/ICPORTS
RB0/AN12/INT0/FLT0/SDI/SDA
OSC1/CLKI
RD0/SPP0 PIC18F4550
OSC2/CLKO/RA6
RD1/SPP1 TQFP 44-PIN
RD2/SPP2
RD3/SPP3
RE0/AN5/CK1SPP
RD4/SPP4
RE1/AN6/CK2SPP
RD5/SPP5/P1B
RE2/AN7/OESPP
RD6/SPP6/P1C
RD7/SPP7/P1D
VUSB
U6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2/UOE_N
RC2/CCP1/P1A
RA0/AN0
RA1/AN1
RA2/AN2/Vref-/CVref
RA3/AN3/Vref+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS_N/HLVDIN/C2OUT
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
18 USB-RST
C60
0.1u
12
13
33
34
R62
100k
B
30 XTI
31 XTO
25
26
27
C63
22p
X2
20MHz
C64
22p
37
C65
470n
19
20
21
22
23
24
R57
R58
R59
51
51
51
PC-SCL
PC-SDA
PC-SDA(ACK)
PIC18F4550
A
A
Title
-55-
AKD4678-B
Size
A3
Date:
5
4
3
2
Document Number
Rev
0
Control
Monday, May 30, 2011
Sheet
1
3
of
3
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