AK4637EN

[AKD4637-B]
AKD4637-B
Evaluation board Rev.1for AK4637
GENERAL DESCRIPTION
The AKD4637-B is an evaluation board for the AK4637 24bit CODEC with built-in PLL and MIC/SPK Amplifier.
The AKD4637-B has the interface with AKM’s A/D evaluation boards. Therefore, it’s easy to evaluate the
AK4637. The AKD4637-B also has the digital audio interface and can achieve the interface with digital audio
systems via opt-connector.
 Ordering Guide
AKD4637-B ---
Evaluation board for AK4637
(Control software is included in this package.)
FUNCTION
 Compatible with 2 types of interface
- Direct interface with AKM’s A/D converter evaluation boards
- DIT/DIR with optical input/output
 USB port for board control
GND1
REG1
0V
5V
3.3V
Digital
MIC
1.8V
DMCK DMDT
AIN/IN+
/DMDAT
J1
BEEP/IN/DMCLK
Mini
Jack
REG
REG
TVDD DVDD AVDD
PIC4550
AK4637
External
Clock
BEEP
LDO
(T3)
USB
Port
PORT3
PORT1
Opt In
AK4118A
(DIT/DIR)
PORT2
Opt Out
J2
LINEOUT
Jack
SPP SPN
SPK
Figure 1. AKD4637-B Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
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 Operation Sequence
(1) Set up the power supply lines.
(1-1) In case of using the power supply connectors. <Default>
JP13
AVDDSEL
3.3V
JP11
USB5V
5V
(1-2) In case of supplying the power from regulator.
JP13
AVDDSEL
3.3V
Name of
Jack
REG1
GND1
Color
red
black
JP11
USB5V
5V
Using
Default Setting
for regulator input
5V
ground
0V
Table 1. Set up of power supply lines
(2) Set up the evaluation mode, jumper pins and DIP switch. (See the followings.)
(3) Power on.
The control software must be opened after the power supplies are applied.
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 Evaluation mode
In case of using the AK4118A when evaluating the AK4637, audio interface format of both devices must be matched.
Refer to the datasheet for audio interface format of the AK4637, and Table 2 for audio interface format of the
AK4118A.
The AK4118A operates at fs of 32kHz or more. If the fs is slower than 32kHz, please use other mode.
In addition, MCLK of AK4118A supports 256fs and 512fs. When evaluating in a condition except above, please use
other mode.
Refer to the datasheet for register setting of the AK4637.
Applicable Evaluation Mode
(1) A/D Evaluation using the AK4118A (DIT).
(1-1) Setting in External Slave Mode
(2) D/A Evaluation using the AK4118A (DIR). <Default>
(2-1) Setting in External Slave Mode
(3) Evaluation of A/D or D/A using the external clock.
(3-1) Setting in PLL Master Mode
(3-2) Setting in PLL Slave Mode
(3-3) Setting in External Slave Mode
(4) Evaluation of Loop-back.
(4-1) Setting in PLL Master Mode
(4-2) Setting in PLL Slave Mode
(4-3) Setting in External Slave Mode
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(1) A/D Evaluation using the AK4118A (DIT)
(1-1) Setting in External Slave Mode
X1 (X’tal: 12.288MHz) and PORT2 (DIT) are used. Do not connect anything to PORT1 (DIR).
Registers of the AK4637 should be set to “EXT Slave Mode”. MCKI, BICK and FCK are supplied from the
AK4118A, and SDTO of the AK4637 is output to the AK4118A.
The jumper pins should be set as follows.
JP5
MCKI
EXT
JP6
BICK
DIR
EXT
JP7
FCK
EXT
DIR
JP8
SDTO
DIR
(2) Evaluation of D/A using DIR of AK4118A. <Default>
(2-1) Setting in External Slave Mode
PORT1 (DIR) is used. Do not connect anything to PORT2 (DIT).
Registers of the AK4637 should be set to “EXT Slave Mode”.
The jumper pins should be set as follows.
JP5
MCKI
EXT
JP6
BICK
DIR
EXT
JP7
FCK
DIR
EXT
<KM120601>
DIR
JP9
SDTI
JP10
SDTI-SEL
ADC
DIR
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(3) A/D or D/A Evaluation using the external clock.
External clocks are used. Do not connect anything to PORT1 (DIR) and PORT2 (DIT).
(3-1) Setting in PLL Master Mode
The master clock is input from the MCKI pin of JP5. An internal PLL circuit generates BICK and FCK.
Registers of the AK4637 should be set to “PLL Master Mode”.
MCKI and SDTI are input into JP5 and JP9. FCK, BICK and SDTO are output from JP7, JP6 and JP8.
11.2896MHz, 12MHz, 12.288MHz,
13.5MHz, 24MHz, 27MHz
DSP or P
AK4637
MCKI
16fs, 32fs, 64fs
BICK
1fs
FCK
BCLK
FCK
SDTO
SDTI
SDTI
SDTO
Figure 2. PLL Master Mode
(3-2) Setting in PLL Slave Mode
A reference clock of PLL is selected among the input clocks that are supplied to the BICK pin. The required clock
to operate the AK4637 is generated by an internal PLL circuit.
Registers of the AK4637 should be set to “PLL Slave Mode” (Reference Clock = BICK).
BICK, FCK and SDTI are input into JP6, JP7 and JP9. SDTO is output from JP8.
DSP or P
AK4637
MCKI
BICK
16fs, 32fs, 64fs
1fs
FCK
BCLK
FCK
SDTO
SDTI
SDTI
SDTO
Figure 3. PLL Slave Mode 2(PLL Reference Clock: BICK pin)
The jumper pins should be set as follows.
JP5
MCKI
DIR
EXT
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(3-3) Setting in External Slave Mode
Registers of the AK4637 should be set to “EXT Slave Mode”.
MCLK, BICK, FCK and SDTI are input into JP5, JP6, JP7 and JP9. SDTO is output from JP8.
AK4951EN
DSP or P
256fs,384fs
512fs or 1024fs
MCKI
BICK
LRCK
MCLK
 32fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 4. EXT Slave Mode
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(4) Evaluation in Loop-back Mode
(4-1) Setting in PLL Master Mode
Do not connect anything to PORT1 (DIR), PORT2 (DIT).
Registers of the AK4637 should be set to “PLL Master Mode”. MCLK should be supplied to JP5.
The jumper pins should be set as follows.
JP9
SDTI
JP8
SDTO
JP10
SDTI-SEL
ADC
DIR
(4-2) Setting in PLL Slave Mode
Do not connect anything to PORT1 (DIR) and PORT2 (DIT).
Registers of the AK4637 should be set to “PLL Slave Mode” (Reference Clock: BICK).
BICK and FCK should be supplied to JP6 and JP7.
The jumper pins should be set as follows.
JP5
MCKI
EXT
JP9
SDTI
JP8
SDTO
JP10
SDTI-SEL
ADC
DIR
DIR
(4-3) Setting in External Slave Mode
Do not connect anything to PORT1 (DIR), PORT2 (DIT).
Registers of the AK4637 should be set to “EXT Slave Mode”.
Use clocks from AK4118A. In case, use X1 (12.288MHz).
The jumper pins should be set as follows.
JP5
MCKI
EXT
DIR
JP6
BICK
EXT
JP7
FCK
DIR
EXT
JP8
SDTO
DIR
<KM120601>
JP9
SDTI
JP10
SDTI-SEL
ADC
DIR
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 DIP Switch Setting
[S1] (SW DIP-4): Mode setting of the AK4118A.
No.
1
2
3
4
Name
OCKS1
DIF0
DIF1
DIF2
ON (“H”)
OFF (“L”)
AK4118A Master Clock Setting : See Table 4
Default
L
L
L
H
AK4118A Audio Format Setting
See Table 3
Table 2. Mode Setting of the AK4118A
Mode
DIF2
DIF1
DIF0
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DAUX
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
FCK
SDTO
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
H/L
H/L
H/L
H/L
H/L
L/H
H/L
L/H
BICK
I/O
O
O
O
O
O
O
I
I
64fs
64fs
64fs
64fs
64fs
64fs
64 -128fs
64 -128fs
I/O
O
O
O
O
O
O
I
I
Default
Table 3. AK4118A Audio Interface Format Setting
OCKS1
MCKO1
X’tal
Default
0
256fs
256fs
1
512fs
512fs
Table 4. AK4118A Master Clock Setting
 Tact SW Function
[SW1] (PDN): Resets AK4637 and AK4118A. When Tact switch is pushed, PDN is “L”.
 Control Port
It is possible to control AKD4637-B via general USB port. Connect cable with the USB connection (PORT3) on the
board and PC.
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 Analog Input/Output Circuits
(1) Input Circuits
Figure 5. AIN, IN+/IN- Input Circuits
(1-1) AIN Input Circuit (Single-ended Input) <Default>
AIN is input to J1.
When the Mic Power is not used, JP2 should be set to open.
JP1
S/D
JP3
IN-
JP2
MPWR
IN+
AIN
(1-2) IN+/IN- Input Circuit (Differential input)
IN+ and IN- are input to J1.
When the Mic Power is not used, JP2 and JP3 should be set to open.
JP1
S/D
JP3
IN-
JP2
MPWR
IN+
AIN
(1-3) BEEP Input Circuit
BEEP is input to TP10.
Do not connect anything to J1.
(1-4) Digital Mic Input Circuit
DMCK is output from TP11 and DMDT is input to TP12.
Do not connect anything to J1.
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(2) Output Circuits
Figure 6. AOUT, SPP/SPN Output Circuit
(2-1) SPP/SPN Output Circuit <Default>
SPP and SPN are output from TP3 and TP4.
JP4
AOUT
(2-2) Monaural Line Output Circuit
AOUT is output from J2.
JP4
AOUT
* AKM assumes no responsibility for the trouble when using the above circuit examples.
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Control Software Manual
 Evaluation Board and Control Software Settings
1.
2.
3.
4.
Set up the evaluation board as needed, according to the previous terms.
Connect the evaluation board and PC with a USB cable.
The USB control is recognized as HID (Human Interface Device) on the PC.
Double-click the icon “akd4637.exe” to open the control program. (Note 1)
When the screen does not display “AKDUSBIF-B” at bottom left, reconnect the PC and the USB cable, and push
the [Port Reset] button.
5. Begin evaluation by following the procedure below.
Figure 7. Window of Control Soft
Note 1. The AK4637 should be reset by the SW1 after the power supplies are applied.
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 Operation Overview
Function and Register map are controlled by this control software. These controls may be selected by the upper tabs.
Frequently used buttons, such as the register initializing button “Write Default”, are located outside of the switching tab
window.
1. [Port Reset]: Resets the connection to PC.
Click this button when connecting USB cable after the control software set up.
2. [Write Default]: Register Initialization.
When the device is reset by a hardware reset, use this button to initialize the registers.
3. [All Write]: Executes write commands for all registers displayed.
4. [All Read]: Executes read commands for all registers displayed.
5. [Save]: “Save Address of Register” dialog box pops up.
6. [Load]: Executes data write from a saved file.
7. [All Reg Write]: “All Reg Write” dialog box pops up.
8. [Sequence]: “Sequence” dialog box pops up.
9. [Sequence (File)]: “Sequence (File)” dialog box pops up.
10. [Read]: Reads current register settings and displays to the register area (on the right of the main window).
(Add: Address, R: AK4637 Read value, W: Last Write value (= Register Map))
This is different from [All Read] button as it does not reflect to the register map. It only displays register
values in hexadecimal numbers.
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 Tab Functions
(1) [Function] Tab: Function Control
Sequence operation and a setup of a register are executed with the function button arranged at the upper part, and each
button in a block diagram.
Figure 8. [Function] Window
Function block
: Executes a sequential process shown on each button. (Refer to (1-(1-1))
Path and Each Setting block : Executes a setup of the path or functions. (Refer to (1-(1-2))
~ Explanation of the color of a pass line ~
Thick lines (blue, red, yellow, and sour orange) show that the paths are connected.
・thick line (blue):
The path is connected and the power of block on this path is "OFF".
・thick line (red):
The path is connected and the power of block on this path is "ON".
・thick line (yellow):
The clock line is connected.
・thick line (sour orange):
The clock line is connected and used.
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(1-1) Function block
Figure 9. [Function] Block
A function button executes the sequence process shown on the each button and updates several registers.
These functions are mainly for path settings.
Function Name
Analog MIC
(Recording_MIC+18dB(ALC ON))
Digital MIC
(Recording_DigitalMIC(ALC ON))
Speaker
(Playback_Speaker+8.4dB(ALC ON))
Line
(Playback_Lineout)
AMIC-Line
(Loopback_MIC+18dB_LineOut
(ALC ON))
Description
MIC Input
Recording
Digital MIC
Input Recording
Speaker Output
Input
AMIC
Output
SDTO
DMDAT
/DMCLK
SDTI
SDTO
SPP/SPN
Line Output
SDTI
AOUT
Loopback
AMIC,
AOUT
(MIC Input,
Line Output)
Table 5. Sequence Process Setting
Path
AMIC→ADC→Digi.Fil→SDTO
DMDAT/DMCLK→Deci.Fil→
Digi.Fil→SDTO
SDTI→Digi.Fil→DAC→
SPP/SPN
SDTI→DAC→AOUT
AMIC→ADC→Digi.Fil→DAC
→AOUT
※The Setting of Clock mode and I/F mode are not changed. The default values are follows.
I/F mode: 24bit MSB justified
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(1-1-1) [Analog MIC (Recording_MIC+18dB(ALC ON))] Sequential process
When [Analog MIC] button in the main window is clicked, the sequence for MIC input Settings is executed.
(Note 2)
Figure 10. [Analog MIC] Setting (After)
Note 2. The function button makes some block power up, but [Power Down/Up] button is not changed.
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(1-1-2) [Digital MIC (Recording_DigitalMIC(ALC ON))] Sequential process
When [Digital MIC] button in the main window is clicked, the sequence for Digital MIC input Settings is executed.
(Note 2)
Figure 11. [Digital MIC] Setting (After)
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(1-1-3) [Speaker (Playback_Speaker+8.4dB(ALC ON)] Sequential process
When [Speaker] button in the main window is clicked, the sequence for Speaker output Settings is executed.
(Note 2)
Figure 12. [Speaker] Setting (After)
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(1-1-4) [Lineout (Playback_Lineout)] Sequential process
When [Lineout] button in the main window is clicked, the sequence for Line output Settings is executed. (Note 2)
Figure 13. [Line out] Setting (After)
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(1-1-5) [AMIC-Line (Loopback_MIC+18dB_LineOut(ALC ON))] Sequential process
When [AMIC-Line] button in the main window is clicked, the sequence of Loopback settings is executed. (Note 2)
Figure 14. [AMIC-Line] Setting (After)
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(1-2) Path and Various Setting Block
The enabled paths are shown. The FS and CM bits, etc… can be set up.
[Input_ADC Setting], [Digital Filter Setting], [ALC Setting], [DAC_Output Setting], [BEEP Setting] -- each
setting dialog can be opened.
Figure 15. [Path and Various Setting] Block
[Input_ADC Setting] button
[Digital Filter Setting] button
[ALC Setting] Button
[DAC_Output Setting] button
: Opens “Input_ADC” dialog box.
: Opens “Filter Setting” dialog box.
: Opens “ALC Setting” dialog box.
: Opens “DAC_Output Setting” dialog box.
This dialog also has a setup of Speaker amplifier and lineout amplifier.
[BEEP Setting] button
: Opens “BEEP Setting” dialog box.
BEEP Power [OFF/ON] button : The path of a BEEP output is controlled and performs a BEEPS output
“OFF/ON.”
[ON]: BEEPS is set “1” and BEEPS bit Switch is connected. (Note 3)
BEEPS bit switch
: This switch is interlocked with BEEPS bit.
DACS/L bit switch
: This switch is interlocked with DACS bit and DACL bit. (Note 4)
[Power Down/Up] button
: Using the present path setting, the path for recording is set and ON/OFF of
PMx bit is changed. (Note 3)
Note 3. There are some register bits which are set up automatically at Power Up/Down. (Refer to the next page.)
Note 4. The DACS (or DACL) switch on a GUI screen is updated by selection situation of a speaker/lineout.
When "LOSEL=0 and DACS=1" or "LOSEL=1 and DACL=1", the switch "is connected".
Other case, the switch "is disconnected".
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BEEP Power: [OFF/ON] Button
Register bit
Setup value
ON
PMVCM
“1” (Note 5)
BEEPS,PMBP
“1”
PMSL, SLPSN
“1” (Note 6)
OFF
PMSL, SLPSN
“0” (Note 6)
PMBP
“0”
Recording: [Power Down/Up] Button
Register bit
Setup value
Power Up
PMVCM
“1” (Note 5)
PMPFIL
When PFSDO bit = 1, PMPFIL bit = 1
PMADC (or PMDM)
-When DMIC bit = 0, PMADC bit = 1
-When DMIC bit = 1, PMDM bit = 1
Power Down
PMADC,PMDM
“0”
PMPFIL
“0” (Note 7)
Playback: [Power Down/Up] Button
Register bit
Setup value
Power Up
PMVCM
“1” (Note 5)
DACS (or DACL)
-When LOSEL bit = 0, DACS bit = 1
-When LOSEL bit = 1, DACL bit = 1
PMPFIL
When PFDAC1-0 bits = 1 or 2, PMPFIL bit = 1
PMDAC
“1”
PMSL, SLPSN
“1” (Note 8)
Power Down
PMSL, SLPSN
“0” (Note 8)
PMDAC
“0”
PMPFIL
“0” (Note 7)
Note 5. Once PMVCM bit is set to “1”, PMVCM is not set to “0” in this Function Tab.
Note 6. These bits keep “1” when Playback is “Power Up”.
Note 7. PMPFIL keep “1” when this is used by Playback or Recording.
Note 8. These bits keep “1” when BEEP Power is “ON”.
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(2) [REG] Tab: Register Map
This tab is for register read and write.
Each bit on the register map is a push-button switch. The register is updated by mouse operation.
Button Down indicates “1” and the bit name is shown in red (when read-only the name is shown in dark red).
Button Up indicates “0” and the bit name is shown in blue (when read-only the name is shown in gray)
Grayed out registers are Read-Only registers. They cannot be controlled.
The registers which are not defined on the datasheet are indicated as “---”.
Figure 16. [REG] Window
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(2-1) [Write]: Data Write Dialog
Select the [Write] button located on the right of the each corresponding address when changing two or more bits on
the same address simultaneously.
Click the [Write] button located on the right of the each corresponded address for a pop-up dialog box.
When the checkbox next to the bit name is checked, the data will become “1”. When the checkbox is not checked,
the data will become “0”.
Click [OK] to write the set values to the registers, or click [Cancel] to cancel this setting.
Figure 17. [Register Set] Window
(2-2) [Read]: Data Read
Click the [Read] button located on the right of the each corresponding address to execute a register read.
The current register value will be displayed in the register window as well as in the upper right hand DEBUG
window.
Button Down indicates “1” and the bit name is shown in red (when read-only the name is shown in dark red).
Button Up indicates “0” and the bit name is shown in blue (when read-only the name is shown in gray).
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 Dialog Box
(1) [Save]: [Save Address of Register] Dialog Box
Click the [Save] button in the main window for save address setting dialog box.
Figure 18. [Save] Window
[All Address] check box
[Start Address] edit box
[End Address] edit box
[OK] button
[Cancel] button
: When the [All Address] checkbox is checked, all register settings will be saved.
: When the [All Address] check box is not checked, set starts register address to save.
: When the [All Address] check box is not checked, set end register address to save.
: Selects a file to save and saves register settings.
: Cancel and finish this process.
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(2) [All Reg Write]: [All Register Write] Dialog Box
Click the [All Reg Write] button in the main window to open register setting file window show below.
Register setting files saved by the [Save] button may be applied.
Figure 19. [All Reg Write] Window
[Open (left)] button
[Write] button
[Help] button
[Save] button
[Open (right)] button
[Close] button
[All Write] flame
: Selects a register setting file (*.akr).
: Executes register write with selected file setting.
: Opens a help window.
: Saves a register setting file assignment. File name is “*.mar”.
: Opens a saved register setting file assignment “*. mar”.
: Closes the dialog box and finish the process.
: Executes all register write.
Selected files are executed in descending order.
[Start] button
: Start the register writing.
[Stop] button
: Stop the register writing.
[Interval time] edit box: Set interval time to start next register setting file. (5msec ~ 10,000msec)
[Current No] edit box : The file number which is being processed is displayed. (File number is assigned 1-10
from top to bottom.)
~ Operating Suggestions ~
1. Files saved by the [Save] button and opened by the [Open] button on the right of the dialog “*.mar” should be
stored in the same folder.
2. Then register settings are changed by the [Save] button in the main window, re-read the file to reflect new
register settings.
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(3) [Sequence]: [Sequence] Dialog Box
Click the [Sequence] button in the main window to open register sequence setting dialog box.
Register sequence can be set in this dialog box.
Figure 20. [Sequence] Window
~ Sequence Setting ~
Set register sequence according to the following process.
1. Select a command
Use [Select] pull-down box to choose commands.
Corresponding boxes will be valid.
< Select items>
・No use
・Register
・Reg_Mask
・Interval
・Stop
・End
: Not using this address
: Register write
: Register write (Masked)
: Takes an interval
: Pauses the sequence
: Ends the sequence
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2.
Input sequence
[Address] : Data address
[Data] : Write data
[Mask]
: Mask
This value “ANDed” with the write data becomes the input data. The bits which corresponding Mask bit =
“0” are not changed. At this time, data read is not executed, and the storage data of this software is used.
“Write Default” must be executed after power up the AK4958 or when the AK4958 is reset by the PDN pin
since the storage data and register values are different.
This is the actual write data.
When Mask = 0x00, current setting is hold.
When Mask = 0xFF, the 8bit data which is set in the [Data] box is written.
When Mask = 0x0F, lower 4bit data which is set in the [Data] box is written.
Upper 4bit is hold to current setting.
[Interval] : Interval time
Valid boxes for each process command are shown below.
・No use
: None
・Register
: [ Address ], [ Data ], [ Interval ]
・Reg_Mask
: [ Address ], [ Data ], [ Mask ], [ Interval ]
・Interval
: [ Interval ]
・Stop
: None
・End
: None
~ Control Buttons ~
Functions of Control Button are shown below.
[DEL] button
: Checked step is deleted.
[INS] button
: The last deleted step is inserted to checked step.
[Start Step] select: Select start step.
No.1 Step
: Start from No.1 step.
Checked Step : Start from checked step.
[Start] button
: Executes the sequence.
[Stop] button
: Stops the sequence.
[Help] button
: Opens a help window.
[Save] button
: Saves sequence settings as a file. The file name is “*.aks”.
[Open] button
: Opens a sequence setting file “*.aks”.
[Close] button : Closes the dialog box and finishes the process.
~ Stop of the Sequence ~
When “Stop” is selected in the sequence, the process is paused at this step and restart step number is checked.
It starts again from the checked step by clicking the [Start] button. When the process at the end of sequence is
finished, “Step No.1” of [start step] is selected automatically.
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[AKD4637-B]
(4) [Sequence (File)]: [Sequence by *.aks file] Dialog Box
Click the [Sequence (File)] button to open sequence setting file dialog box shown below.
Files saved in the “Sequence setting dialog” can be applied in this dialog.
Figure 21. [Sequence (File)] Window
[Open (left)] button
[Start] button
[Start All] button
: Opens a sequence setting file (*.aks).
: Executes the sequence by the setting of selected file.
: Executes all sequence settings.
Selected files are executed in descending order.
[Stop] button
: Stops the sequence process.
[Help] button
: Opens a help window.
[Save] button
: Saves a sequence setting file assignment. The file name is “*.mas”.
[Open (right)] button : Opens a saved sequence setting file assignment “*. mas”.
[Close] button
: Closes the dialog box and finishes the process.
~ Operating Suggestions ~
1. Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mas” should be
stored in the same folder.
2. When “Stop” is selected in the sequence, the process will be paused and a pop-up message will appear. Click
“OK” to continue the process.
Figure 22. [Sequence Pause] Window
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[AKD4637-B]
(5) [Input_ADC Setting]: [Input_ADC Setting] Dialog Box
Click the [Input_ADC Setting] button in the main window to open MIC and ADC setting dialog.
The settings on this dialog are interlocked with the settings on register map.
(Refer to the datasheet for register definitions.)
Figure 23. [Audio I/F] Window
~ Gain Control by Slider ~
The volume can also be changed by slider.
When a value is input in the edit box, the slider is moved to the value that selected by the edit box.
Use the mouse or arrow keys on the keyboard for fine tuning.
Slider is moved to
the selected value.
Input value is adjusted automatically to the
value which can be set up.
Figure 24. Slider operation
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[AKD4637-B]
(6) [Digital Filter Setting]: [Filter Setting] Dialog Box
Click the [Digital Filter] button in the main window to open digital filter setting dialog.
Coefficient and frequency of digital filter are calculated on this dialog.
(Refer to the datasheet for register definitions.)
Figure 25. [Filter Setting] Window
[Register Setting] button : Opens the register setting dialog.
Register writes of a filter factor are also executed.
[F Response] button
: Opens the frequency response plot dialog [Filter Plot].
Register writes of a filter factor are also executed.
[Write] button
: Calculation of all the filters and coefficient writing are executed.
[Example Setting] button : The example parameters are set in dialog and the filter coefficients are written.
EQ Sequence for Noise [ON/OFF] button: ON: EQCx bit, EQxT bits and EQxG bits are set for noise processing.
OFF: The bits will return to the state of before the button is set to ON.
[Notch ON/OFF] button : ON: The gain is fixed to “-1.0” in order to use as Notch filter.
OFF: Gain is set to “1.0” when this is changed to “OFF”.
[Close] button
: Closes the dialog box and finishes the process.
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[AKD4637-B]
(6-1) Parameter Setting
“HPF1 Enable”, “HPF2 Enable”, “LPF Enable”, “EQ1”, “EQ2”, “EQ3”, “EQ4”, “EQ5”
Please set ON/OFF of Filter with a check button.
When checked it, Filter becomes ON. When “Notch Filter Auto Correction” is checked, perform automatic
correction of the center frequency of the notch filter is executed.
Figure 26. Filter ON/OFF Check Box
Please set a parameter of each Filter (Note 9)
Parameter
Detail
Sampling Rate
Sampling Frequency (fs)
HPF
HPF1 Cut Off Frequency
HPF2 Cut Off Frequency
LPF
Cut Off Frequency
5 Band Equalizer
EQ1-5 Center Frequency
EQ1-5 Band Width
EQ1-5 Gain
High Pass Filter 1 cut off frequency
High Pass Filter 2 cut off frequency
Low Pass Filter cut off frequency
Setting Range
8, 11.025, 12, 16, 22.05, 24
32, 44.1 or 48kHz
3.7×fs/48 ∼ 236.8×fs/48 (kHz)
0.0001 ≦ fc/fs < 0.497
0.05 ≦ fc/fs < 0.497
EQ1-5 Center frequency
0.003 < fo/fs < 0.497
EQ1-5 Band width
(Note 10)
fo/fs < 0.497
EQ1-5 Gain
(Note 11)
-1 ≦ Gain < 3
Table 6. Parameter Setting of [Filter Setting]
Note 9. When the value smaller than a setting range is set, the minimum value of setting range is set.
When the value bigger than a setting range is set, the maximum value of setting range is set.
When set error value to the filter of “OFF”, an error message is not displayed.
Note 10. A gain difference is a bandwidth of 3dB from center frequency.
Note 11. When a gain is “-1”, EQ becomes a notch filter.
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[AKD4637-B]
(6-2) [Register Setting]: [Register Setting for Filter] Dialog Box
Click the [Register Setting] button, a register set value is displayed.
Figure 27. [Register Setting for Filter] Window
Followings are the cases when a register set value is updated.
1. When [Register Setting] button was pushed.
2. When [F Response] button was pushed.
3. When [Write] button was pushed.
4. When [UpDate] button was pushed on a frequency characteristic indication window.
5. When Enter or the Tab key is pressed after setting each parameter.
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[AKD4637-B]
(6-3) [F Response]: [Filter Plot] Dialog Box
The frequency response of digital filter is displayed when push a [F Response] button.
Then, the register setting for digital filter are also updated.
Change Frequency Range, and indication of a frequency characteristic is updated when push a [UpDate] button.
Figure 28. [F Response] Window
[Frequency Range] edit box : The width of the frequency display is specified.
[UpDate] button
: It draws in the graph again.
[Log View] check button
: Switch of “Linear/Log” display.
[Mouse Control of Left Button] radio button :
The item (fo, Gain) which can be adjusted with a mouse can be chosen. (at using EQx) (Note 12)
fo: Center frequency can be adjusted.
Gain: Gain can be adjusted.
fo and Gain: Center frequency and Gain can be adjusted.
[Close] button
: Closing the dialog box and finish the process.
Note 12. EQx of “Notch ON” is able to adjust only “fo”.
~ Adjustment of vertical range ~
1.[ Y-axis Ref ] edit box : Display setting of center value.
2.[Vertical slider]
: Movement of vertical display.
3.[Horizontal slider]
: Adjustment of the horizontal display.
(The left side reduces, and the right side expands.)
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[AKD4637-B]
(6-4) 5-BandEQ operation on Filter Plot screen
When EQ (1~5) is turning “ON”, a green number is displayed on the Filter Plot dialog box.
This number shows the setting of the center frequency and the gain of each EQ.
(The horizontal coordinates of a number is the center frequency of EQ, and the vertical ordinate is a gain of EQ
(-1 ∼ 2.99).)
The number under the display is operated with the mouse, and it is possible to set the filter characteristic on this
screen.
The center frequency and the gain setting are changed by moving the mouse while left-clicking. (Note 12)
The setting of the bandwidth is changed by moving the mouse while right-clicking.
After operating the mouse,
the value of the center frequency and the gain is
updated.
The number is selected.
The movement operation is done
while left-clicking.
Figure 29. Filter Setting (Left-clicking operation)
Band width can be updated by
right-clicking and move of mouse.
Figure 30. Filter Setting (Right-clicking operation)
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[AKD4637-B]
(6-5) About “Notch Auto Correct”
If the gain of 5-Band EQ is set to “-1”, Equalizer becomes a notch filter.
When the center frequency of two or more notch filters is adjacent, the gap is generated in the center frequency.
(Figure 31) When “Notch Auto Correct” button is checked, the center frequency of the notch filter is automatically
corrected. The gain setting of the automatic correction function is effective and only EQ of “-1” is effective.
(Figure 32)
This automatic compensation is effective to EQ which set the gain as “-1”. (Note 12, Note 13, Note 14)
Note 13. There is a possibility that the automatic compensation is not correctly done when the width of the center
frequency is smaller than that of the bandwidth setting.
Note 14. Gain is fixed to “-1.0” by [Notch OFF/ON] button “ON”.
Gain is fixed to “-1.0”
by [Notch OFF/ON]
button"ON."
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Bandwidth: 200Hz (EQ2~4))
Figure 31. 5Band Equalizer Operation (Not Check of “Notch Auto Correct”)
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Bandwidth: 200Hz (EQ2~4))
Figure 32. 5Band Equalizer Operation (Checked of “Notch Auto Correct”)
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[AKD4637-B]
(6-6) Common Gain Sequence for Noise
If “EQ Sequence for Noise (ON/OFF)” button is pushed, setup bit about EQ2-5 shown below are changed.
When the button pushed to OFF, each setup is returned the state of before pushing a button.
Please use the button when it expected that a noise continues.
Figure 33. Equalizer Gain Setting
Button ON:EQCx bit: OFF, EQxG5-0 bits: 0x3F (-0.03dB), EQxT1-0 bits: 00 (256/fs)
Figure 34. Equalizer Gain Setting (Setting for Noise button is “ON”)
Button OFF:the state of before pushing a button.
Figure 35. Equalizer Gain Setting (Setting for Noise button is “OFF”)
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[AKD4637-B]
(7) [ALC Setting]: [ALC Setting] Dialog Box
Click the [ALC Setting] button in the main window to open ALC setting dialog.
ALC parameters are controlled in this dialog.
The settings on this dialog are interlocked with the settings on register map.
(Refer to the datasheet for register definitions.)
Figure 36. [ALC Setting] Window
~ Volume Read ~
When the [Start] button on the bottom right of the dialog is clicked, reading “VOL” register is executed
periodically.
This interval time is set by the edit box beside the button. This reading continues until the stop button is pushed.
The read value is displayed on the progress control and
edit box.
The Interval of read-out can set up in 100~1000 msec.
Figure 37. Volume Progress Control
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[AKD4637-B]
(8) [DAC_Output Setting]: [DAC_Output Setting] Dialog Box
Click the [DAC Setting] button in the main window to open DAC setting dialog.
Output mode, DAC and output gain setting are available.
The settings on this dialog are interlocked with the settings on register map.
(Refer to the datasheet for register definitions.)
Figure 38. [DAC_Output Setting] Window
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[AKD4637-B]
(9) [BEEP Setting]: [BEEP Setting] Dialog Box
Click the [BEEP Setting] button in the main window to open BEEP setting dialog.
The settings on this dialog are interlocked with the settings on register map.
(Refer to the datasheet for register definitions.)
Figure 39. [BEEP Setting] Window
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[AKD4637-B]
測定結果
[測定条件]
・
・
・
・
・
・
・
・
・
・
Measurement unit
MCKI
BICK
fs
Bit
Measurement Mode
Power Supply
Input Frequency
Measurement Frequency
Temperature
: Audio Precision, System two Cascade
: 256fs (12.288MHz)
: 64fs
: 48kHz
: 24bit
: EXT Slave Mode
: AVDD = TVDD = 3.3V, DVDD = 1.8V
: 1kHz
: 20 ~ 20kHz
: Room
[測定結果]
1. ADC
ADC: AIN → ADC → SDTO, IVOL=0dB, ALC=OFF
MGAIN = +18dB
S/(N+D)
(-1dBFS)
DR
(-60dBFS, A-Weighted)
S/N
(A-weighted)
MGAIN = 0dB
S/(N+D)
(-1dBFS)
DR
(-60dBFS, A-Weighted)
S/N
(A-weighted)
ADC: IN+/IN- → ADC → SDTO, IVOL=0dB, ALC=OFF
MGAIN = +18dB
S/(N+D)
(-1dBFS)
DR
(-60dBFS, A-Weighted)
S/N
(A-weighted)
MGAIN = 0dB
S/(N+D)
(-1dBFS)
DR
(-60dBFS, A-Weighted)
S/N
(A-weighted)
Result
Unit
82.5
88.1
88.1
dB
dB
dB
84.3
94.9
95.0
dB
dB
dB
80.0
85.7
85.7
dB
dB
dB
83.0
93.2
93.1
dB
dB
dB
2. DAC
Result
Unit
Speaker-Amp: DAC  SPP/SPN, IVOL=DVOL=0dB, SPKG=+8.45dB, RL=8
fs=48kHz, BW=20kHz
S/(N+D)
(-0.5dBFS)
77.1
dB
S/N
(A-weighted)
97.0
dB
Stereo Line Output: DAC  AOUT, IVOL=DVOL=0dB, RL=22kΩ
LVCM1-0 bits = “01”, fs=48kHz, BW=20kHz
(0dBFS)
81.6
dB
S/(N+D)
(-3dBFS)
86.0
dB
S/N
(A-weighted)
94.3
dB
<KM120601>
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[AKD4637-B]
[Plot]
1. ADC (AIN  ADC) (Single-ended Input)
[MGAIN=+18dB]
AK4637 ADC FFT (-1dBFS)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 40. FFT (Input level = -1dBFS)
AK4637 ADC FFT (-60dBFS)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
Hz
Figure 41. FFT (Input level = -60dBFS)
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[AKD4637-B]
AK4637 ADC FFT (No signal)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
-10
+0
Hz
Figure 42. FFT (No signal)
AK4637 ADC THD+N vs Input Level (fin=1kHz)
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-100
-90
-80
-70
-60
-50
-40
-30
-20
dBr
Figure 43. THD+N vs Input Level
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[AKD4637-B]
AK4637 ADC THD+N vs Input
Frequency
(-1dBF)
Frequency
(-1dBFS)
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 44. THD+N vs Input Frequency
AK4637 ADC Linearity (fin=1kHz)
+0
T
-20
-40
d
B
F
S
-60
-80
-100
-120
-120
-100
-80
-60
-40
-20
+0
dBr
Figure 45. Linearity
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[AKD4637-B]
AK4637 ADC Frequency Response (-1dBFS)
+0
-0.2
-0.4
-0.6
d
B
F
S
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
Hz
Figure 46. Frequency Response
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[AKD4637-B]
[MGAIN=0dB]
AK4637 ADC FFT (-1dBFS)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 47. FFT (Input level = -1dBFS)
AK4637 ADC FFT (-60dBFS)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
Hz
Figure 48. FFT (Input level = -60dBFS)
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[AKD4637-B]
AK4637 ADC FFT (No signal)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
-10
+0
Hz
Figure 49. FFT (No signal)
AK4637 ADC THD+N vs Input Level (fin=1kHz)
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-100
-90
-80
-70
-60
-50
-40
-30
-20
dBr
Figure 50. THD+N vs Input Level
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[AKD4637-B]
AK4637 ADC THD+N vs Input
Frequency
(-1dBFS)
Frequency
(-1dBFS)
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 51. THD+N vs Input Frequency
AK4637 ADC Linearity (fin=1kHz)
+0
T
-20
-40
d
B
F
S
-60
-80
-100
-120
-120
-100
-80
-60
-40
-20
+0
dBr
Figure 52. Linearity
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[AKD4637-B]
AK4637 ADC Frequency Response (-1dBFS)
+0
-0.2
-0.4
-0.6
d
B
F
S
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
Hz
Figure 53. Frequency Response
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[AKD4637-B]
2. ADC (IN+/IN-  ADC) (Differential Input)
[MGAIN=+18dB]
AK4637 ADC FFT (-1dBFS)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 54. FFT (Input level = -1dBFS)
AK4637 ADC FFT (-60dBFS)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
Hz
Figure 55. FFT (Input level = -60dBFS)
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[AKD4637-B]
AK4637 ADC FFT (No signal)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
-10
+0
Hz
Figure 56. FFT (No signal)
AK4637 ADC THD+N vs Input Level (fin=1kHz)
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-100
-90
-80
-70
-60
-50
-40
-30
-20
dBr
Figure 57. THD+N vs Input level
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[AKD4637-B]
AK4637 ADC THD+N vs Input
Frequency
(-1dBFS)
Frequency
(-1dBFS)
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 58. THD+N vs Input Frequency (C8 and C9: Ceramic Capacitor)
AK4637 ADC Linearity (fin=1kHz)
+0
T
-20
-40
d
B
F
S
-60
-80
-100
-120
-120
-100
-80
-60
-40
-20
+0
dBr
Figure 59. Linearity
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[AKD4637-B]
AK4637 ADC Frequency Response (-1dBFS)
+0
-0.2
-0.4
-0.6
d
B
F
S
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
Hz
Figure 60. Frequency Response
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[AKD4637-B]
[MGAIN=0dB]
AK4637 ADC FFT (-1dBFS)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 61. FFT (Input level = -1dBFS)
AK4637 ADC FFT (-60dBFS)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
Hz
Figure 62. FFT (Input level = -60dBFS)
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[AKD4637-B]
AK4637 ADC FFT (No signal)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
-10
+0
Hz
Figure 63. FFT (No signal)
AK4637 ADC THD+N vs Input Level (fin=1kHz)
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-100
-90
-80
-70
-60
-50
-40
-30
-20
dBr
Figure 64. THD+N vs Input Level
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[AKD4637-B]
AK4637 ADC THD+N vs Input
Frequency
(-1dBFS)
Frequency
(-1dBFS)
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 65. THD+N vs Input Frequency
AK4637 ADC Linearity (fin=1kHz)
+0
TT
-20
-40
d
B
F
S
-60
-80
-100
-120
-120
-100
-80
-60
-40
-20
+0
dBr
Figure 66. Linearity
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[AKD4637-B]
AK4637 ADC Frequency Response (-1dBFS)
+0
-0.2
-0.4
-0.6
d
B
F
S
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
Hz
Figure 67. Frequency Response
<KM120601>
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[AKD4637-B]
3. DAC (DAC  Speaker (SPP/SPN))
AK4637 DAC=>SPK FFT (-0.5dBFS; SPKG=01)
+0
-20
-40
d
B
r
-60
-80
A
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 68. FFT (Input level = -0.5dBFS)
AK4637 DAC=>SPK FFT (-60dBFS; SPKG=01)
+0
-20
-40
d
B
r
-60
-80
A
-100
-120
-140
20
50
100
200
500
1k
2k
5k
Hz
Figure 69. FFT (Input level = -60dBFS)
<KM120601>
2015/06
- 57 -
[AKD4637-B]
AK4637 DAC=>SPK FFT (No signal; SPKG=01)
+0
-20
-40
d
B
r
-60
-80
A
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 70. FFT (No signal)
AK4637 DAC=>SPK Out of band noise (SPKG=01)
+0
-20
-40
d
B
r
-60
-80
A
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
50k 100k
Hz
Figure 71. FFT (Out-of-band Noise)
<KM120601>
2015/06
- 58 -
[AKD4637-B]
AK4637 DAC=>SPK THD+N vs Frequency (-0.5dBFS; SPKG=01)
-40
-50
-60
-70
d
B
-80
-90
-100
-110
-120
20
50
100
200
500
1k
2k
5k
10k
20k
-10
+0
Hz
Figure 72. THD+N vs Input Frequency
AK4637 DAC=>SPK Linearity (fin=1kHz; SPKG=01)
+0
-10
-20
-30
d
B
r
-40
A
-60
-50
-70
-80
-90
-100
-100
-90
-80
-70
-60
-50
-40
-30
-20
dBFS
Figure 73. Linearity
<KM120601>
2015/06
- 59 -
[AKD4637-B]
AK4637 DAC=>SPK Frequency Response (-0.5dBFS; SPKG=01)
+0
-0.1
-0.2
-0.3
d
B
r
-0.4
A
-0.6
-0.5
-0.7
-0.8
-0.9
-1
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
Hz
Figure 74. Frequency Response
AK4637 DAC=>SPK THD+N vs Output Power (fin=1kHz; SPKG=00)
d
B
-40
200m
-45
180m
-50
160m
-55
140m
-60
120m
-65
100m W
-70
80m
-75
60m
-80
40m
-85
20m
-90
-40
-35
-30
-25
-20
-15
-10
-5
+0
0
dBFS
Figure 75. THD+N vs Output Power (SPKG=00)
<KM120601>
2015/06
- 60 -
[AKD4637-B]
AK4637 DAC=>SPK THD+N vs Output Power (fin=1kHz; SPKG=01)
-40
300m
-45
250m
-50
-55
200m
-60
d
B
-65
150m W
-70
100m
-75
-80
50m
-85
-90
-40
-35
-30
-25
-20
-15
-10
-5
+0
0
dBFS
Figure 76. THD+N vs Output Power (SPKG=01)
AK4637 DAC=>SPK THD+N vs Output Power (fin=1kHz; SPKG=10)
d
B
+0
500m
-10
450m
-20
400m
-30
350m
-40
300m
-50
250m W
-60
200m
-70
150m
-80
100m
-90
50m
-100
-40
-35
-30
-25
-20
-15
-10
-5
+0
0
dBFS
Figure 77. THD+N vs Output Power (SPKG=10)
<KM120601>
2015/06
- 61 -
[AKD4637-B]
AK4637 DAC=>SPK THD+N vs Output Power (fin=1kHz; SPKG=11)
d
B
+0
1.2
-20
1
-40
800m
-60
600m W
-80
400m
-100
200m
-120
-40
-35
-30
-25
-20
-15
-10
-5
+0
0
dBFS
Figure 78. THD+N vs Output Power (SPKG=11)
<KM120601>
2015/06
- 62 -
[AKD4637-B]
4. DAC (DAC  Line-out (AOUT))
AK4637 DAC=>Line-out FFT (0dBFS; LVCM=01)
+0
-20
-40
d
B
r
-60
-80
A
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 79. FFT (Input level = 0dBFS)
AK4637 DAC=>Line-out FFT (-3dBFS; LVCM=01)
+0
-20
-40
d
B
r
-60
-80
A
-100
-120
-140
20
50
100
200
500
1k
2k
5k
Hz
Figure 80. FFT (Input level = -3dBFS)
<KM120601>
2015/06
- 63 -
[AKD4637-B]
AK4637 DAC=>Line-out FFT (-60dBFS; LVCM=01)
+0
-20
-40
d
B
r
-60
-80
A
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 81. FFT (Input level = -60dBFS)
AK4637 DAC=>Line-out FFT (No signal; LVCM=01)
+0
-20
-40
d
B
r
-60
-80
A
-100
-120
-140
20
50
100
200
500
1k
2k
5k
Hz
Figure 82. FFT (No signal)
<KM120601>
2015/06
- 64 -
[AKD4637-B]
AK4637 DAC=>Line-out Out of band noise (LVCM=01)
+0
-20
-40
d
B
r
-60
-80
A
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
50k 100k
Hz
Figure 83. FFT (Out-of-band Noise)
AK4637 DAC=>Line-out Input Level (fin=1kHz; LVCM=01)
-60
-70
-80
d
B
r
-90
A
-100
-110
-120
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 84. THD+N vs Input Level
<KM120601>
2015/06
- 65 -
[AKD4637-B]
AK4637 DAC=>Line-out THD+N vs Frequency (-3dBFS; LVCM=01)
-60
-70
-80
d
B
r
-90
A
-100
-110
-120
20
50
100
200
500
1k
2k
5k
10k
20k
-10
+0
Hz
Figure 85. THD+N vs Input Frequency
AK4637 DAC=>Line-out Linearity (fin=1kHz; LVCM=01)
+0
-10
-20
-30
d
B
r
-40
A
-60
-50
-70
-80
-90
-100
-100
-90
-80
-70
-60
-50
-40
-30
-20
dBFS
Figure 86. Linearity
<KM120601>
2015/06
- 66 -
[AKD4637-B]
AK4637 DAC=>Line-out Frequency Response (-3dBFS; LVCM=01)
-2.5
-2.6
-2.7
-2.8
d
B
r
-2.9
A
-3.1
-3
-3.2
-3.3
-3.4
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
Hz
Figure 87. Frequency Response
<KM120601>
2015/06
- 67 -
[AKD4637-B]
REVISION HISTORY
Date
(YY/MM/DD)
15/01/19
15/06/18
Manual
Revision
KM120600
KM120601
Board
Revision
0
1
Reason
Page
First edition
Board change
Error
correction
Error
correction
1
2
Description
addition
40-67
<KM120601>
9
Contents
AK4637: Rev.A → Rev.B
Correction of Figure and Name of Jumper pin
JP3→JP13
Correction of Name of Jumper pin and Test
pins
(1-1) JP4→JP2
(1-3) JP10→TP10
(1-4) JP11→TP11, JP12→TP12
Measurement data were added.
2015/06
- 68 -
[AKD4637-B]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information
contained in this document without notice. When you consider any use or application of AKM product
stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized
distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy
or completeness of the information contained in this document nor grants any license to any intellectual
property rights or any other rights of AKM or any third party with respect to the information in this document.
You are fully responsible for use of such information contained in this document in your product design or
applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD
PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR
APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily
high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life,
bodily injury, serious property damage or serious public impact, including but not limited to, equipment used
in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for
automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control
combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and
equipment used in finance-related fields. Do not use Product for the above use unless specifically agreed by
AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for
complying with safety standards and for providing adequate designs and safeguards for your hardware,
software and systems which minimize risk and avoid situations in which a malfunction or failure of the
Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information contained in this
document for any military purposes, including without limitation, for the design, development, use,
stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products
(mass destruction weapons). When exporting the Products or related technology or any information
contained in this document, you should comply with the applicable export control laws and regulations and
follow the procedures required by such laws and regulations. The Products and related technology may not be
used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any
applicable domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations
that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with
applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth in this
document shall immediately void any warranty granted by AKM for the Product and shall not create or extend
in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
consent of AKM.
<KM120601>
2015/06
- 69 -
DVDD
C16 10u
AOUT
VSS2
1
VDD
INT0
R4 Open
VSS2
T2
A
+C1
47u
C5
0.1u
NC
GND
Vcont
PCL
Vin
Vout
Pad
NC
NC
TK73633AME
10
9
1
2
3
4
8
7
S1
SW DIP-4
6
R23
5.1
H (ON)
8
7
6
5
L(OFF)
OCKS1
DIF0
DIF1
DIF2
5
4
1
2
3
4
3
2
B
RP1
47k
1
13
TVDD
14
NC/GP1
15
TX0/GP2
16
TX1/GP3
17
BOUT/GP4
18
COUT/GP5
19
UOUT/GP6
20
R18
470
C24 10u
5V JP13
R3 0
AVDD-SEL
3.3V
R2 5.1
4
3
2
1
C
0.47u
C23 0.1u
1
5
6
7
8
IPS0/RX4
11
C22
R17
10k
DVDD
+C4
10u
VOUT/GP7
NC
VSS3
R1 0
C3
0.1u
21
OCKS0/CSN/CAD0
37
4
3
2
1
DVDD
DIF0/RX5
+
GND
C2
0.1u
NC
GND
Vcont
PCL
Vin
Pad Vout
NC
NC
TK73618AME
9
GND1
5
6
7
8
9
VSS3
T1
36
OCKS1/CCLK/SCL
INT1
2
USB5V
REG1
C19
0.1u
TEST2
12
8
7
6
5
35
SW1
RESET
OPT-OUT
RX3
B
34
DIF1/RX6
CM1/CDTI/SDA
VSS4
R22
10k
CM0/CDTO/CAD1
VCC
IN
48
D1
HSU119
VSS4
VSS1
47
VSS3
A
VSS2
1
VSS1
AK4118A
PDN
RX2
2.2k
DIF2/RX7
46
33
XTI
TEST1
R25
K
USB-PDN
IPS1/IIC
45
32
U2
XTO
RX1
31
P/SN
44
C21 5p
SDA
GND1デバイス近傍で1点アース
30
2
SCL
DAUX
NC
29
XTL0
RX0
C20 5p
12.288MHz
X1
VIN/GP0
MCKO2
43
SDTO
28
42
JP8
VSS3
R16
2.2k
GND
C26
0.1u
XTL1
41
R15
2.2k
22
12
VSS2
13
SPN/NC
14
TP9
SCL
TP8
SDA
2
3
C27
10u
BICK
VCOM
26
SDTO
VSS2
25
23
24
VSS3
JP10 DIR
SDTI-SEL
ADC
MCKO1
JP9
SDTI
1
VSS1
R14 51
27
TP12
DMDAT
C8 1u
VSS1
R13 51
JP7 DIR
FCK
EXT
C29
10u
C28
0.1u
40
R5
2.2k
6
JP6 DIR
BICK
EXT
R
R6
1k
R12 51
C41
0.1u
AVDD
C
SDTO
7
PORT2
1
JP5 DIR
MCKI
EXT
39
JP3
IN-
JP2
MPWR
BEEP/IN/DMCLK
R11 51
8
D3V
38
JP1
S/D
20
AIN
R7
1k
IN+
2
1
FCK
9
TP7
TVDD
TVDD
R10 51
SDTI
3
TP11
DMCLK
BICK
2
C9 1u
AK4637
MPWR
AIN/IN+
/DMDAT
TP10
BEEP
REGFIL
SDA
19
MCKI
C18
10u VSS2
+
18
U1
VCOM
C17
0.1u
10
+
C11
2.2u
D
TVDD
4
17
VSS1
C15 0.1u
SCL
C10
2.2u
EP
3
16
PDN
EP
SPP/AOUT
C12
0.1u
TP2
VSS1
VSS1
TP4
SPN
15
VSS1
+
AVDD
C13
10u
TP6
DVDD
11
AVDD TP1
AVDD
+
R9
22k
D
J1
MIC-IN
JP4
1
TP5
VSS2
TP3
SPP
LRCK
C14 1u
2
5
R8 220
2
1
3
DVDD
3
1
J2
LINE-OUT
4
+
5
PORT1
1
2
AVDD
C25
0.1u
3
TVDD
OUT
GND
VCC
OPT-IN
VSS3
D3V
A
+C7
22u
C6
0.1u
VSS1
Title
AKD4637-B
Size
A3
- 70 5
4
3
Date:
2
Document Number
Rev
A
AK4637 & DIR_DIT
Thursday, December 25,
2014 Sheet
1
1
of
2
5
4
3
2
1
GND
ID
D+
DVBUS
PORT3
USB Connector
USB5V
D
9
5
4
3
2
1
T3
5
6
7
8
JP11
USB5V
NC
GND
Vcont
PCL
Vin
Vout
NC
Pad NC
TK73633AME
C32
1u
4
3
2
1
D
C33
0.1u
+
C34
10u
VSS4
U4
VSS4
1
C42
0.1u
A
2
SCL
3
SDA
4
EN
VREF1 VREF2
SCL1
SCL2
SDA1
SDA2
R28
1k
R27
1k
34
NC/ICPORTS
36
35
RC1/T1OSI/CCP2/UOE_N
VUSB
RC2/CCP1/P1A
37
38
RD0/SPP0
RD1/SPP1
39
40
RD2/SPP2
RB1/AN10/INT1/SCK/SCL
RE0/AN5/CK1SPP
32
C
C30 22p
31
XTO
X2
20MHz
30
XTI
C31 22p
29
28
C36
0.1u
27
26
25
B
24
23
RA3/AN3/Vref+
RA4/T0CKI/C1OUT/RCV
33
22
RA2/AN2/Vref-/CVref
21
20
RA0/AN0
19
18
RB3/AN9/CPP2/VPO
RA1/AN1
RA5/AN4/SS_N/HLVDIN/C2OUT
MCLR_N/Vpp/RE3
RB2/AN8/INT2/VMO
R21
100k
R24 4.7k
8
7
41
RE1/AN6/CK2SPP
R26 100k
PCA9306DP1
GND
RC4/D-/VM
RB0/AN12/INT0/FLT0/SDI/SDA
12
C37 0.1u
RD3/SPP3
43
RE2/AN7/OESPP
NC/ICCK/ICPGC
11
VDD1
VDD0
RB7/KBI3/PGD
10
VSS0
17
9
B
VSS1
U3
PIC18F4550
RB6/KBI2/PGC
8
RD7/SPP7/P1D
16
7
OSC1/CLKI
RB5/KBI1/PGM
C38
0.1u
RD6/SPP6/P1C
15
6
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
RB4/AN11/KBI0/CSSPP
5
NC/ICRST_N/ICVpp
RD5/SPP5/P1B
14
4
RD4/SPP4
NC/ICDT/ICPGD
3
RC7/RX/DT/SDO
13
2
C
RC5/D+/VP
44
RC6/TX/CK
1
C35
0.47u
R20
0
42
R19
0
VSS4
C40
0.1u
VDD
1
MCLR
2
PGD
3
PGC
4
GND
5
JP12 PIC
A
VSS4
6
5
Title
AKD4637-B
Size
USB-PDN
A3
- 71 5
4
3
Date:
2
Document Number
Rev
A
CONTROL I/F (USB)
Tuesday, December 09, 2014
Sheet
1
2
of
2
Symbol-A
- 72 -
Symbol-B
- 73 -
Pattern-A
- 74 -
Pattern-B
- 75 -
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