AK4954AEN

[AKD4954A-B]
AKD4954A-B
Evaluation board Rev.0 for AK4954A
GENERAL DESCRIPTION
The AKD4954A-B is an evaluation board for the AK4954A 32bit CODEC with built-in PLL and MIC/HP/SPK
Amplifier. On-board USB port enables a GUI on Windows to control various settings. The AKD4954A-B
has the interface with AKM’s A/D evaluation boards. Therefore, it’s easy to evaluate the AK4954A. The
AKD4954A-B also has the digital audio interface and can achieve the interface with digital audio systems via
opt-connector.
 Ordering Guide
AKD4954A-B ---
Evaluation board for AK4954A
(Cable for connecting with USB port and control software are included in this package.
This control software does not operate on Windows NT.)
FUNCTION
 Compatible with 2 types of interface
- Direct interface with AKM’s A/D converter evaluation boards
- DIT/DIR with optical input/output
 USB port for board control
TVDD DVDD AVDD SVDD GND1
3.3V
1.8V
3.3V
3.3V
REG1
5V
0V
3.3V
REG
1.8V
REG
LDO
LIN1
Digital
MIC
(T3)
RIN1
PIC4550
USB
LIN2
Mini
Jack
AK4954A
RIN2
External
Clock
Opt In
LIN3
AK4118A
(DIT/DIR)
RIN3
Opt Out
SPP SPN
LINEOUT
Jack
HP
Jack
SPK
Figure 1. AKD4954A-B Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
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 Operation Sequence
(1) Set up the power supply lines.
(1-1) In case of supplying the power from regulator. <Default>
JP3
JP17
SVDD
USB5V
1.8V
5V
3.3V
Name of
Jack
REG1
GND1
Color
red
black
Using
Default Setting
for regulator input
5V
ground
0V
Table 1. Set up of power supply lines
(1-2) In case of using the power supply connectors.
JP3
SVDD
JP17
USB5V
1.8V
5V
3.3V
(2) Set up the evaluation mode, jumper pins and DIP switch. (See the followings.)
(3) Power on.
The AK4954A and AK4118A must be reset after the power supplies are applied.
The AK4954A and AK4118A should be reset once by bringing SW1 (PDN) “L” upon power-up. Click the
Dummy Command button on the control software after releasing the reset by SW1= “H”.
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 Evaluation mode
In case of using the AK4118A when evaluating the AK4954A, audio interface format of both devices must be
matched.
Reter to the datasheet for audio interface format of the AK4954A, and Table 2 for audio interface format of the
AK4118A.
The AK4118A operates at fs of 32kHz or more. If the fs is slower than 32kHz, please use other mode.
In addition, MCLK of AK4118A supports 256fs and 512fs. When evaluating in a condition except above, please use
other mode.
Refer to the datasheet for register setting of the AK4954A.
Applicable Evaluation Mode
(1) A/D Evaluation using the AK4118A (DIT).
(1-1) Setting in External Slave Mode
(2) D/A Evaluation using the AK4118A (DIR). <Default>
(2-1) Setting in External Slave Mode
(3) Evaluation of A/D or D/A using the external clock.
(3-1) Setting in PLL Master Mode
(3-2) Setting in PLL Slave Mode
(3-3) Setting in External Slave Mode
(4) Evaluation of Loop-back.
(4-1) Setting in PLL Master Mode
(4-2) Setting in PLL Slave Mode
(4-3) Setting in External Slave Mode
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(1) A/D Evaluation using the AK4118A (DIT)
(1-1) Setting in External Slave Mode
X1 (X’tal: 11.2896MHz) and PORT2 (DIT) are used. Do not connect anything to PORT1 (DIR).
Registers of the AK4954A should be set to “EXT Slave Mode”. MCKI, BICK and LRCK are supplied from the
AK4118A, and SDTO of the AK4954A is output to the AK4118A.
The jumper pins should be set as follows.
JP11
MCKI
EXT
JP14
BICK
DIR
EXT
JP12
LRCK
DIR
EXT
JP15
SDTO
DIR
(2) Evaluation of D/A using DIR of AK4118A. <Default>
(2-1) Setting in External Slave Mode
PORT1 (DIR) is used. Do not connect anything to PORT2 (DIT).
Registers of the AK4954A should be set to “EXT Slave Mode”.
The jumper pins should be set as follows.
JP11
MCKI
EXT
JP14
BICK
DIR
EXT
DIR
JP12
LRCK
EXT
<KM114100>
DIR
JP13
SDTI
EXT
DIR
JP10
SDTI-SEL
ADC
DIR
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(3)
A/D or D/A Evaluation using the external clock.
External clocks are used. Do not connect anything to PORT1 (DIR) and PORT2 (DIT).
(3-1) Setting in PLL Master Mode
The master clock is input from the MCKI pin of JP11. An internal PLL circuit generates BICK and LRCK.
Registers of the AK4954A should be set to “PLL Master Mode”.
BICK, LRCK SDTI and SDTO are input into and output from JP14, JP12, JP13 and JP15.
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz
DSP or P
AK4954A
MCKI
BICK
LRCK
32fs, 64fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 2. PLL Master Mode
.
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(3-2) Setting in PLL Slave Mode
A reference clock of PLL is selected among the input clocks that are supplied to the BICK pin. The required clock
to operate the AK4954A is generated by an internal PLL circuit.
Registers of the AK4954A should be set to “PLL Slave Mode” (Reference Clock = BICK).
BICK, LRCK SDTI and SDTO are input into and output from JP14, JP12, JP13 and JP15.
DSP or P
AK4954A
MCKI
32fs, 64fs
BICK
1fs
LRCK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 3. PLL Slave Mode 2(PLL Reference Clock: BICK pin)
The jumper pins should be set as follows.
JP11
MCKI
DIR
EXT
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(3-3) Setting in External Slave Mode
Registers of the AK4954A should be set to “EXT Slave Mode”.
MCLK, BICK, LRCK SDTI and SDTO are input into and output from JP11, JP14, JP12, JP13 and JP15.
AK4954A
DSP or P
256fs,384fs
512fs or 1024fs
MCKI
MCLK
 32fs
BICK
BCLK
1fs
LRCK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 4. EXT Slave Mode
(4)
Evaluation in Loop-back Mode.
(4-1) Setting in PLL Master Mode
Do not connect anything to PORT1 (DIR), PORT2 (DIT).
Registers of the AK4954A should be set to “PLL Master Mode”.
(4-1-1) In case of supplying MCLK to JP11
The jumper pins should be set as follows.
JP15
SDTO
JP13
SDTI
EXT
<KM114100>
DIR
JP10
SDTI-SEL
ADC
DIR
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(4-2) Setting in PLL Slave Mode
Registers of the AK4954A should be set to “PLL Slave Mode” (Reference Clock: BICK).
Do not connect anything to PORT1 (DIR) and PORT2 (DIT).
(4-2-1) In case of supplying BICK and LRCK from the external clock
The jumper pins should be set as follows.
JP11
MCKI
EXT
JP13
SDTI
JP15
SDTO
EXT
DIR
DIR
JP10
SDTI-SEL
ADC
DIR
(4-3) Setting in External Slave Mode
Registers of the AK4954A should be set to “EXT Slave Mode”.
Do not connect anything to PORT1 (DIR), PORT2 (DIT).
(4-3-1) In case of using clocks from AK4118A
Use X1 (11.2896MHz).
The jumper pins should be set as follows.
JP11
MCKI
EXT
JP14
BICK
DIR
EXT
DIR
JP12
LRCK
EXT
JP15
SDTO
DIR
<KM114100>
JP13
SDTI
EXT
DIR
JP10
SDTI-SEL
ADC
DIR
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 DIP Switch Setting
[S1] (SW DIP-4): Mode setting of the AK4118A.
No.
1
2
3
4
Name
OCKS1
DIF0
DIF1
DIF2
ON (“H”)
OFF (“L”)
AK4118A Master Clock Setting : See Table 4
AK4118A Audio Format Setting
See Table 3
Default
L
L
L
H
Table 2. Mode Setting of the AK4118A
Mode
DIF2
DIF1
DIF0
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DAUX
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
SDTO
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
LRCK
I/O
H/L
O
H/L
O
H/L
O
H/L
O
H/L
O
L/H
O
H/L
I
L/H
I
BICK
64fs
64fs
64fs
64fs
64fs
64fs
64 -128fs
64 -128fs
I/O
O
O
O
O
O
O
I
I
Default
Table 3. AK4118A Audio Interface Format Setting
OCKS1
MCKO1
X’tal
Default
0
256fs
256fs
1
512fs
512fs
Table 4. AK4118A Master Clock Setting
 Toggle SW Function
*Upper-side is “H” and lower-side is “L”.
[SW1] (PDN): Power downs AK4954A and AK4118A. Keep “H” during normal operation.
 Control Port
It is possible to control AKD4954A-B via general USB port. Connect cable with the USB connection(PORT3) on the
board and PC.
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 Analog Input/Output Circuits
(1) Input Circuits
+
RIN3
C19
1n
C18
1u
+
VSS1
LIN3
JP2
RIN-SEL
VSS1
RIN3
RIN2
RIN1
3
J1
MIC-IN
C16
1u
2
1
R7
2.2k
RIN2
LIN3
LIN2
LIN1
VSS1
MPWR2
JP9
MP-RIN2
JP8
MP-LIN2
C17
1n
C15
1n
R6
2.2k
C14
1u
VSS1
JP1
LIN-SEL
LIN2
MPWR1
JP7
MP-RIN1
JP6
MP-LIN1
R4
2.2k
C13
1n
C12
1u
VSS1
R5
2.2k
JP5
DMCK
RIN1
C11
1n
C10
1u
JP4
DMDT
VSS1
LIN1
C9
1n
C8
1u
VSS1
Figure 5. LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 Input Circuits
(1-1) LIN1/RIN1Input Circuit <Default>
LIN1 and RIN1are input to J1.
When the Mic Power is not used, JP6 and JP7 should be set to open.
JP1
JP2
LIN3
RIN3
LIN2
RIN2
LIN1
LIN-SEL
JP4
JP5
JP6
JP7
DMDT
DMCK
MP-LIN1
MP-RIN1
RIN1
RIN-SEL
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(1-2)
LIN2/RIN2 Input Circuit <Default>
LIN2 and RIN2 are input to J2 and J3.
When the Mic Power is not used, JP8 and JP9 should be set to open.
JP1
JP2
LIN3
RIN3
LIN2
RIN2
LIN1
RIN1
LIN-SEL
JP8
JP9
MP-LIN2
MP-RIN2
RIN-SEL
(1-3) LIN3/RIN3 Input Circuit
LIN3 and RIN3 are input to J2 and J3.
JP1
JP2
LIN3
RIN3
LIN2
RIN2
LIN1
RIN1
LIN-SEL
RIN-SEL
(1-4) Digital Mic Input Circuit
DMCK is output from JP5 and DMDT is input to JP4.
JP4
JP5
DMDT
DMCK
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(2) Output Circuits
(2-1) HPL/HPR Output Circuit
3
HPR
J2 HP-OUT
2
1
HPL
C29
0.22u
C28
0.22u
R18
33
R17
33
VSS1
Figure 6. HPL/HPR Output Circuit
HPL and HPR are output from J2
(2-2) SPP/SPN Output Circuit
1
TP1
SPP
SPP
1
TP2
SPN
SPN
Figure 7. SPP/SPN Output Circuit
SPP and SPN are output from TP1 and TP2.
(2-3) Stereo Line Output Circuit
+
3
+
C25 1u
2
1
ROUT
LOUT
J3 LINE-OUT
C24 1u
R15
22k
R16
22k
VSS3
.Figure 8. LOUT/ROUT Output Circuit
LOUT and ROUT are output from J3.
* AKM assumes no responsibility for the trouble when using the above circuit examples.
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AK4954A Control Software Manual
■ Evaluation Board and Control Software Settings
1. Set up the evaluation board as needed, according to the previous terms.
2. Connect cable with the USB connection on the board and PC.
3. The USB I/F board is recognized as HID (Human Interface Device) on PC. It is not necessary to install a new
driver.
4. Start up the control program.(Note 1)
Note 1. After power up the evaluation board, put SW1 to “L” to power down the AK4954A and the AK4118A,
and return them to “H” to release the power-down state. Then, an initialization must be executed by
pressing the Dummy Command button.
5. Begin evaluation by following the procedure below.
Figure 9. Window of Control Soft
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■ Operation Overview
Function, register map and testing tool are controlled by this control software. These controls may be selected by the
upper tabs.
Frequently used buttons, such as the register initializing button “Write Default”, are located outside of the switching tab
window. Refer to the “■ Dialog Boxes” section for details of each dialog box setting.
1. [Port Reset]: Click this button after the control soft starts up.
2. [Write Default]: Initializes Registers
When the device is reset by a hardware reset, use this button to initialize the registers.
3. [All Write]: Executes write command for all registers displayed.
4. [All Read]: Executes read command for all registers displayed.
5. [Save]: Saves current register settings to a file.
6. [Load]: Executes data write from a saved file.
7. [All Req Write]: Opens “All Req Write” dialog box.
8. [Data R/W]: Opens “Data R/W” dialog box
9. [Sequence]: Opens “Sequence” dialog box.
10.
[Sequence (File)]: Opens “Sequence(File)” dialog box.
11.
[Read]: Reads current register settings and displays on to the register area (on the right of the main window).
This is different from [All Read] button as it does not reflect to the register map. It only displays register
values in hexadecimal numbers.
12.
[Dummy Command]: The dummy command is written (Note 2).
Note 2. After power up the evaluation board, put SW1 to “L” to power down the AK4954A and the AK4118A,
and return them to “H” to release the power-down state. Then, an initialization must be executed by
pressing the Dummy Command button.
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■ Tab Functions (Note 3)
1. [Function]: Function control
The dialog box setting is open when click the each button
Each operation is executed by [Function] buttons on the left side of the screen. (Refer to the “■ Dialog Box” for
details of each dialog box setting.)
Note 3. After power up the evaluation board, put SW1 to “L” to power down the AK4954A and the AK4118A,
and return them to “H” to release the power-down state. Then, an initialization must be executed by
pressing the Dummy Command button.
Figure 10. [Function] Window
[Power Management Setting]
[Audio Mode Setting]
[System Clock Audio I/F]
[ALC Setting]
[Volume Setting]
[Beep Setting]
[Digital Filter]
[DRC Setting]
: Open [Power Management Setting] dialog.
: Open [Audio Mode Setting] dialog.
: Open [System Clock Audio I/F] dialog.
: Open [ALC Setting] dialog.
: Open [Volume Setting] dialog.
: Open [Beep Setting] dialog.
: Open [Filter Setting] dialog.
: Open [DRC Function] dialog.
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2. [REG]: Register Map
This tab is for a register write and read.
Each bit on the register map is a push-button switch.
Button Down indicates “H” or “1” and the bit name is shown in red (when read-only, the name is shown in dark red).
Button Up indicates “L” or “0” and the bit name is shown in blue (when read-only, the name is shown in gray).
Grayed-out registers are Read-only registers. They cannot be controlled.
The registers which are not defined on the datasheet are indicated as “---”.
Figure 11. [REG] Window
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2-1. [Write]: Data Write Dialog
Select the [Write] button located on the right of the each corresponding address when changing tow or more bits
on the same address simultaneously. Click the [Write] button for the register pop-up dialog box shown below.
When the checkbox next to the register name is checked, the data will become “1”. When the checkbox is not
checked, the data will become “0”. Click [OK] to write setting values to the registers, or click [Cancel] to cancel
this setting.
Figure 12. [Register Set] Window
2-2. [Read]: Data Read
Click the [Read] button located on the right of the each corresponding address to execute a register read.
The current register value will be displayed in the register window as well as in the upper right hand DEBUG
window.
Button Down indicates “1” and the bit name is shown in red (when read-only, the name is shown in dark red).
Button Up indicates “0” and the bit name is shown in blue (when read-only, the name is shown in gray).
Please be aware that button statuses will be changed by a Read command.
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■ Dialog Box
1. [All Req Write]: All Reg Write dialog box
Click the [All Reg Write] button in the main window to open register setting file window shown below.
Register setting files saved by the [SAVE] button may be applied.
Figure 13. [All Reg Write] Window
[Open (left)] : Selects a register setting file (*.akr).
[Write]
: Executes register write with selected setting file.
[Write All] : Executes register write with all selected setting files.
Selected files are executed in descending order.
[Help]
: Opens a help window.
[Save]
: Saves a register setting file assignment. File name is “*.mar”.
[Open (right)]: Opens a saved register setting file assignment “*. mar”.
[Close]
: Closes the dialog box and finish process.
~ Operating Suggestions ~
1.
2.
Files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be stored in
the same folder.
When register settings are changed by [Save] button in the main window, re-read the file to reflect new register
settings.
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2. [Data R/W]: Data R/W Dialog Box
Click the [Data R/W] button in the main window for data read/write dialog box.
Data is written to the specified address.
Figure 14. [Data R/W] Window
[Address] Box : Input data write address in hexadecimal numbers.
[Data] Box
: Input write data in hexadecimal numbers.
[Mask] Box
: Input masks data in hexadecimal numbers.
This value “ANDed” with the write data becomes the input data.
[Write]
: Writes the data generated from Data and Mask value is written to the address specified in
“Address” box (Note 4).
[Read]
: Reads data from the address specified in “Address” box (Note 4).
The result will be shown in the Read Data Box in hexadecimal numbers.
[Close]
: Closes the dialog box and finishes process.
Data write will not be executed unless the [Write] button is clicked.
Note 4. The register map will be updated after executing the [Write] or [Read] command.
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3. [Sequence]: Sequence Dialog Box
Click the [Sequence] button to open register sequence setting dialog box.
Register sequence may be set in this dialog box.
Figure 15. [Sequence] Window
~ Sequence Setting ~
Set register sequence according to the following process bellow.
1.
Select a command
Use [Select] pull-down box to choose commands.
Corresponding boxes will be valid.
< Select Pull-down menu >
· No_use
: Not using this address
· Register
: Register write
· Reg(Mask)
: Register write (Masked)
· Interval
: Takes an interval
· Stop
: Pauses the sequence
· End
: Ends the sequence
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2.
Input sequence
[Address] : Data address
[Data]
: Write data
[Mask]
: Mask
The value in the [Data] box is ANDed with the value in the [Mask] box. This data becomes the
actual input data.
When Mask = 0x00, current setting is hold.
When Mask = 0xFF, the 8bit data which is set in the [Data] box is written.
When Mask =0x0F, lower 4bit data which is set in the [Data] box is written.
Upper 4bit is hold to current setting.
[Interval] : Interval time
Valid boxes for each process command are shown bellow.
· No_use
· Register
· Reg(Mask)
· Interval
· Stop
· End
: None
: [Address], [Data], [Interval]
: [Address], [Data], [Mask], [Interval]
: [Interval]
: None
: None
~ Control Buttons~
Functions of Control Buttons are shown bellow.
[Start] Button : Executes the sequence
[Help] Button : Opens a help window
[Save] Button : Saves sequence settings as a file. The file name is “*.aks”.
[Open] Button: Opens a sequence setting file “*.aks”.
[Close] Button: Closes the dialog box and finishes the process.
~ Stop of the sequence~
When “Stop” is selected in the sequence, the process is paused. It starts again when the [Start] button is clicked
Restart step number is shown in the “Start Step” box. When executing the process until the end of sequence, the
“Start Step” value will return to “1”.
The sequence can be started from any step by writing a step number to the “Start Step” box.
Write “1” to the “Start Step” box and click [Start] button, when restarting the process from the beginning.
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4. [Sequence(File)]: Sequence Setting File Dialog Box
Click the [Sequence(File)] button to open sequence setting file dialog box shown below.
Files saved in the “Sequence setting dialog” can be applied in this dialog.
Figure 16. [Sequence(File)] Window
[Open (left)]
[Start]
[Start All]
[Help]
[Save]
[Open(right)]
[Close]
: Select a sequence setting file (*.aks).
: Executes the sequence by the setting of selected file.
: Executing all sequence settings.
Selected files are executed in descending order.
: Opens a help window.
: Saves a sequence setting file assignment. File name is “*.mas”.
: Select a saved sequence setting file assignment “*. mas”.
: Closes the dialog box and finishes the process.
~ Operating Suggestions ~
1. Files saved by the [Save] button and opened by the [Open] button on the right of the dialog “*.mas” should be
stored in the same folder.
2. When “Stop” is selected in the sequence, the process will be paused and the message box shown below pops up.
Click “OK” to continue the process.
Figure 17. Window of [Sequence Pause]
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5. [Power Management Setting]: Power Management Setting Dialog Box
Click [Power Management Setting] button in the function tab to open the power management setting dialog box
shown in Figure 18.
Refer to the datasheet for register settings of the AK4954A.
Figure 18. [Power Management Setting] Window
6. [Audio Mode Setting]: Audio Mode Setting Dialog Box
Click the [Audio Mode Setting] button in the function tab to open the audio mode setting dialog box shown in Figure
19.
Refer to the datasheet for register settings of the AK4954A.
Figure 19. [Audio Mode Setting] Window
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7. [System Clock Audio I/F]: System Clock Audio I/F Dialog Box
Click the [System Clock Audio I/F] button in the function tab to open the System Clock Audio I/F dialog box shown
in Figure 20. Refer to the datasheet for register settings of the AK4954A.
Figure 20. [System Clock Audio I/F] Window
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8. [ALC Setting]: ALC Setting Dialog Box
Click the [ALC Setting] button in the function tab to open the ALC setting dialog box shown in Figure 21.
Refer to the datasheet for register settings of the AK4954A.
Figure 21. [ALC Setting] Window
Volume Control by Slider Menu
The volume can also be changed by writing a value in a dialog box. The slide bar is moved to the value that is written
in the dialog box. Use the mouse or arrow keys on the keyboard for fine adjustments.
Slide bar is
moved to the
selected value.
The configurable value is automatically
selected.
Figure 22. Volume Slider
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[AKD4954A-B]
9. [Volume Setting]: Volume Setting Dialog Box
Click the [Volume Setting] button in the function tab to open the volume setting dialog box shown in Figure 23.
Refer to the datasheet for register settings of the AK4954A.
Figure 23. [Volume Setting] Window
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10. [BEEP Setting]: BEEP Setting Dialog Box
Click the [BEEP Setting] button in the function tab to open is the Beep setting dialog box shown in Figure 24.
Refer to the datasheet for register settings of the AK4954A.
Figure 24. [BEEP Setting] Window
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11. [Digital Filter]: Filter Setting Dialog Box
Click the [Digital Filter] button in the function tab to open the filter setting dialog box shown in Figure 25.
Refer to the datasheet for register settings of the AK4954A.
Figure 25. [Filter Setting] Window
[Register Setting]
[F Response]
[Write]
[Close]
: Opens “Register Setting for Filter” dialog box.
: Opens the filter characteristic dialog.
Executes all filter calculation, but filter coefficients are not written.
: Executes all filter calculation, and filter coefficients are written.
: Closes the dialog box and ends process.
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11-1. Parameter Setting
(1) Please set a parameter of each Filter.
Parameter
Function
Sampling Rate
Sampling frequency (fs)
HPF
Cut Off Frequency
High pass filter cut off frequency
LPF
Cut Off Frequency
Low pass filter cut off frequency
FIL3
Cut Off Frequency
FIL3 cut off frequency
Filter type
Gain
EQ0
Pole Frequency
The selection of filter type
Gain
Zero-point Frequency
EQ0 Zero-point Frequency
Gain
Gain2
5 Band Equalizer
EQ1-5 Center Frequency
Gain
Gain2
EQ1-5 Band Width
EQ1-5 Gain
EQ0 Pole Frequency
Setting Range
7350Hz ≤ fs ≤ 96000Hz
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
fs/20 ≤ Cut Off Frequency
≤ (0.497 * fs)
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
LPF or HPF
-10dB ≤ Gain < 0dB
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
-20dB ≤ Gain < +12dB
0 / +12 / +24dB
0Hz ≤ Center Frequency < (0.497 * fs)
(Note 5)
1Hz ≤ Band Width < (0.497 * fs)
EQ1-5 Band Width
-1≤ Gain < 3
EQ1-5 Gain
(Note 6)
Table 5. Parameter Setting of [Filter Setting]
EQ1-5 Center Frequency
Note 5. A gain difference is a bandwidth of 3dB from center frequency.
Note 6. When a gain is “-1”, EQ becomes a notch filter.
(2) “LPF Enable”, “HPF Enable”, “HPFAD Enable”, “FIL3 Enable”, “EQ0 Enable”,
“EQ1”, “EQ2”, “EQ3”, “EQ4”, “EQ5” Please set ON/OFF of Filter by a check box.
When the check box next to the filter name is checked, the filter will become ON. When “Notch Filter Auto
Correction” is checked, automatic correction of the center frequency of the notch filter is performed.
Figure 26. Filter ON/OFF Setting Check Box
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[AKD4954A-B]
11-2. [Register Setting]: Register Setting for Filter Dialog Box
Click the [Register Setting] button in the filter setting window to open the register setting dialog box shown
below. When a value out of a setting range is set, error message is displayed, and a calculation of register
setting is not carried out.
Figure 27. [Register Setting for Filter] Window
Followings are the cases when register set values are updated.
(1) When [Register Setting] button is pushed.
(2) When [Frequency Response] button is pushed.
(3) When [UpDate] button on a frequency characteristic indication window is pushed.
(4) When “Notch Filter Auto Correction” is ON/OFF.
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11-3. [F Response]: Filter Plot Dialog Box
Click the [F Response] button in the filter setting window to open the filter plot dialog box shown below.
Change Frequency Range, and indication of a frequency characteristic is updated when push a [UpDate]
button.
Figure 28. [F Response] Window
[Frequency Range] : The width of the frequency display is specified.
[Update]
[Gain/Phase]
[Log View]
[Close]
: Redraws the filter characteristics.
: “Gain/Phase” display Switch.
: “Linear/Log” display Switch.
: Closes the dialog box and ends process.
~ Adjustment of vertical range ~
[Y-axis Ref]
[Vertical slider]
[Horizontal slider]
: Set the center value of Y-axis.
: Moves center reference of the Y-axis.
: Adjust scale of the X-axis.
(Left: shrinking, Right: expanding)
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11-4. 5-BandEQ operation in Filter Plot screen
When EQ(1~5) is turned on, a green number is displayed on the Filter Plot dialog box.
This number shows the setting of the center frequency and the gain of each EQ.
The displayed number can be moved by dragging, and filter characteristics are set on this screen.
The center frequency and the gain setting are changed by left click dragging.
The setting of the bandwidth is changed by right click dragging.
After dragging the number, the value
of the center frequency and the gain
are updated.
Select the number, left click and
drag to set the characteristics.
Figure 29. Filter Setting (Left-clicking operation)
The bandwidth is set by right click dragging.
Figure 30. Filter Setting (Right-clicking operation)
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11-5. Simulation of Fil3 Filter
Setting of Stereo-MIC
[L-ch Level]/[R-ch Level] : Input the level of the MIC input.
[Distance]
: Set the distance between the sound source and the MIC.
[Angle]
: Set the angle between the sound source and the MIC.
Figure 31. Simulation of Fil3 Filter
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11-6. “Notch Auto Correct” Function
If the gain of 5-Band EQ is set to “-1”, Equalizer becomes a notch filter.
If the center frequency of two or more notch filters are adjacent, each center frequency will shift slightly
(Figure 32).
Check the “Notch Auto Correct” check box to correct notch filter center frequency automatically (Figure 33).
The automatic correction of center frequency is only effective for the equalizer that the gain is set to “-1”
(Note 7).
Note 7. There is a possibility that the automatic correction is not applied appropriately if the width of the
center frequency is smaller than that of the bandwidth setting.
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Bandwidth : 200Hz(EQ2~4)
Figure 32. “Notch Auto Correct” function is “OFF”
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Bandwidth : 200Hz(EQ2~4)
Figure 33. “Notch Auto Correct” function is “ON”
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12. [DRC Setting]: [DRC Function] Dialog Box
Click the [DRC Setting] button in the function tab to open the DRC function dialog box shown in Figure 34.
Refer to the datasheet for register settings of the AK4954A.
Figure 34. [DRC Setting] Window
[Write]
[F Response]
[DRC Curve]
[Close]
: Executes all filter calculations, and coefficients are written.
: Opens the filter characteristic dialog.
Executes all filter calculations, but filter coefficients are not written.
: Opens the DRC Curve dialog.
: Closes the dialog box and ends process.
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12-1. Parameter Setting
(1) Set a parameter of each Filter and Gain.
Parameter
Setting Range
Function
7350Hz ≤ fs ≤ 96000Hz
Sampling Rate
Sampling frequency (fs)
Noise Suppression
LPF
HPF
Low pass filter cut off frequency
High pass filter cut off frequency
fs/10000 ≤ Cut Off Frequency ≤ (0.497 * fs)
fs/10000 ≤ Cut Off Frequency ≤ (0.497 * fs)
Low pass filter cut off frequency
fs/10000 ≤ Cut Off Frequency ≤ (0.497 * fs)
LPF
Low pass filter cut off frequency
fs/10000 ≤ Cut Off Frequency ≤ (0.497 * fs)
HPF
High pass filter cut off frequency
fs/10000 ≤ Cut Off Frequency ≤ (0.497 * fs)
High pass filter cut off frequency
fs/10000 ≤ Cut Off Frequency ≤ (0.497 * fs)
Dynamic Volume Control
Low Frequency Range
LPF
Middle Frequency Range
High Frequency Range
HPF
Table 6. Parameter Setting of [DRC Function]
(2) When the checkbox next to each filter name is checked, the filter will be enabled. When “DVLC Enable” button is
checked, the filters of Low/Middle/High Range are enabled according to setting of pull-down menu. When “fc Auto”
checkbox is checked, the frequency responses of low frequency and high frequency ranges become flat automatically.
Figure 35. Filter ON/OFF setting button
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12-2. Frequency Response
Click the [F Response] button in the DRC setting window to display frequency characteristics.
Figure 36. A frequency characteristic indication result
[Frequency Range]
[Update]
[Gain/Phase]
[Close]
: The width of the frequency display is specified.
: Redraws the filter characteristics.
: “Gain/Phase” display Switch.
: Closes the dialog box and ends process.
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12-3. Filter Setting
The filter setting can be executed by checking the “NSLPF”, “NSHPF” or “DVLC Enable” checkbox in the [DRC
function] dialog box.
Select a filter name by left
clicking and drag to adjust
the filter characteristics.
After changing the
characteristics, the value of the
cut-off frequency is updated.
Figure 37. Filter Setting (Left-clicking operation)
After changing the filter mode by pull-down box,
the filter characteristics on the graph is update.
Figure 38. Filter Setting (Filter Selecting)
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12-4. Noise Suppression
Click the [DRC curve] button in the DRC setting window to open the DRC curve window. Click the “NS” radio button to
adjust the noise suppression setting.
Noise Suppression Threshold Low Level and Reference Value can be adjusted by left-click dragging.
Noise Suppression
Threshold Low Level
Reference Value
Register map
After “Threshold Low Level” point is moved,
the setting value is reflected on the register map.
The “Threshold Low Level” point is adjusted, by
left- click dragging
Figure 39. Noise Suppression Setting
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12-5. Dynamic Volume Control
Dynamic Volume is displayed when “LOW”, ”MIDDLE” or “HIGH” radio button in “DVLC” is checked. Then, a
register set point is also updated.
Dynamic Volume Control Points can be adjusted by left-click dragging.
Select the frequency range
for DVLV curve。
Red: LOW
Blue: MIDDLE
Green: HIGH
DVLC volume control point
in Low range
レジスタマップ
After volume control point is moved,
the setting value is reflected on the
register map.
The volume control point is adjusted by
left-click dragging.
Figure 40. DVLC Curve Setting
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12-6. Dynamic Range Control
Dynamic Range Control is displayed when “DRC” radio button is checked. Then, a register set point is also updated.
Dynamic Range Compression Level can be adjusted by left-click dragging.
Register map
After “DRC Compression Level” is
moved, the setting value is reflected
on the register map.
The “DRC Compression Level” is
adjusted by left- click dragging.
Figure 41. Dynamic Range Control Setting
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MEASUREMENT RESULTS
[Measurement condition]
・ Measurement unit
・ MCKI
・ BICK
・ fs
・ Bit
・ Measurement Mode
・ Power Supply
・ Input Frequency
・ Measurement Frequency
・ Temperature
: Audio Precision, System two Cascade
: 256fs (11.2896MHz, 24.576MHz)
: 64fs
: 44.1kHz, 96kHz
: 24bit
: EXT Slave Mode
: AVDD = SVDD = TVDD = 3.3V, DVDD = 1.8V
: 1kHz
: 20 ~ 20kHz (fs=44.1kHz), 20 ~ 40kHz (fs=96kHz)
: Room
[Measurement Results]
1. ADC
Result
Lch
ADC: LIN1/RIN1 → ADC → IVOL, IVOL=0dB, ALC=OFF
MGAIN = +20dB
fs=44.1kHz, BW=20kHz
89.2
S/(N+D)
(-1dBFS)
fs=96kHz, BW=40kHz
84.9
DR
(-60dBFS, A-Weighted)
97.0
S/N
(A-weighted)
97.1
MGAIN = 0dB
fs=44.1kHz, BW=20kHz
88.2
S/(N+D)
(-1dBFS)
fs=96kHz, BW=40kHz
81.5
DR
(-60dBFS, A-Weighted)
100.9
S/N
(A-weighted)
101.0
Rch
Unit
88.9
85.2
96.7
96.8
dB
dB
dB
dB
89.0
82.2
101.0
101.1
dB
dB
dB
dB
2. DAC
Result
Unit
Lch
Rch
Headphone-Amp: DAC  HPL/HPR, IVOL=DVOL=0dB, RL=16Ω
fs=44.1kHz, BW=20kHz
69.9
68.9
dB
S/(N+D)
fs=96kHz, BW=40kHz
69.8
68.7
dB
S/N
(A-weighted)
100.7
100.6
dB
Speaker-Amp: DAC  SPP/SPN, IVOL=DVOL=0dB, SPKG=+6.26dB, RL=8
fs=44.1kHz, BW=20kHz
S/(N+D)
(-0.5dBFS)
76.1
dB
Output Noise Level
(A-Weighted)
-96.3
dBV
Stereo Line Output: DAC  LOUT/ROUT, IVOL=DVOL=0dB, RL=20kΩ
fs=44.1kHz, BW=20kHz
S/(N+D)
85.6
85.4
dB
S/N
(A-weighted)
89.1
89.1
dB
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[Plot]
1. ADC (LIN1/RIN1  ADC) (+20dB)
[fs=44.1kHz]
AK4954 FFT [LIN3/RIN3]
fs=44.1kHz, fin=1kHz, -1dBFS Input, MGAIN="+20dB"
+0
-20
-40
-60
d
B
F
S
-80
-100
-120
-140
-160
-180
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 42. FFT (Input level= -1dBFS)
AK4954 FFT [LIN3/RIN3]
fs=44.1kHz, fin=1kHz, -60dBFS Input, MGAIN="+20dB"
+0
-20
-40
-60
d
B
F
S
-80
-100
-120
-140
-160
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 43. FFT (Input level= -60dBFS)
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[AKD4954A-B]
AK4954 FFT [LIN3/RIN3]
fs=44.1kHz, No Signal, MGAIN="+20dB"
+0
-20
-40
-60
d
B
F
S
-80
-100
-120
-140
-160
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 44. FFT (No signal)
AK4954 S/(N+D) vs. Input Level [LIN3/RIN3]
fs=44.1kHz, fin=1kHz, MGAIN="+20dB"
-70
-75
-80
d
B
F
S
-85
-90
-95
-100
-120
-100
-80
-60
-40
-20
+0
dBr
Figure 45. THD+N vs. Input Level
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[AKD4954A-B]
AK4954 S/(N+D) vs. Input Frequency [LIN3/RIN3]
fs=44.1kHz, -1dBFS Input, MGAIN="+20dB"
d
B
F
S
-70
-72
-74
-76
-78
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
-100
20
50
100
200
500
1k
2k
5k
10k
Hz
Figure 37. THD+N vs. Input Frequency
AK4954 Linearity [LIN3/RIN3]
fs=44.1kHz, fin=1kHz, MGAIN="+20dB"
+0
T T TTT
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
-140
-120
-100
-80
-60
-40
-20
+0
dBr
Figure 47. Linearity
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20k
[AKD4954A-B]
AK4954 Frequency Responce [LIN3/RIN3]
fs=44.1kHz, -1dBFS Input, MGAIN="+20dB"
+0
-0.5
-1
d
B
F
S
-1.5
-2
-2.5
-3
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
5k
10k
20k
Hz
Figure 48. Frequency Response
AK4954 Crosstalk [LIN3/RIN3]
fs=44.1kHz, -1dBFS Input, MGAIN="+20dB"
-60
T
T
-70
-80
-90
d
B
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
Hz
Figure 49. Crosstalk
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2. ADC (LIN1/RIN1  ADC) (+20dB)
[fs=96kHz]
AK4954 FFT [LIN3/RIN3]
fs=96kHz, fin=1kHz, -1dBFS Input, MGAIN="+20dB"
+0
-20
-40
-60
d
B
F
S
-80
-100
-120
-140
-160
-180
40 50
100
200
500
1k
2k
5k
10k
20k
40k
20k
40k
Hz
Figure 50. FFT (Input level= -1dBFS)
AK4954 FFT [LIN3/RIN3]
fs=96kHz, fin=1kHz, -60dBFS Input, MGAIN="+20dB"
+0
-20
-40
-60
d
B
F
S
-80
-100
-120
-140
-160
-180
40 50
100
200
500
1k
2k
5k
10k
Hz
Figure 51. FFT (Input level= -60dBFS)
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AK4954 FFT [LIN3/RIN3]
fs=96kHz, No Signal, MGAIN="+20dB"
+0
-20
-40
-60
d
B
F
S
-80
-100
-120
-140
-160
-180
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 52. FFT (No signal)
AK4954 S/(N+D) vs. Input Level [LIN3/RIN3]
fs=96kHz, fin=1kHz, MGAIN="+20dB"
-70
-75
-80
d
B
F
S
-85
-90
-95
-100
-120
-100
-80
-60
-40
-20
+0
dBr
Figure 53. THD+N vs. Input Level
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[AKD4954A-B]
AK4954 S/(N+D) vs. Input Frequency [LIN3/RIN3]
fs=96kHz, -1dBFS Input, MGAIN="+20dB"
-70
-75
-80
d
B
F
S
-85
-90
-95
-100
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 54. THD+N vs. Input Frequency
AK4954 Linearity [LIN3/RIN3]
fs=96kHz, fin=1kHz, MGAIN="+20dB"
+0
T T TT T
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
-140
-120
-100
-80
-60
-40
-20
+0
dBr
Figure 55. Linearity
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[AKD4954A-B]
AK4954 Frequency Response [LIN3/RIN3]
fs=96kHz, -1dBFS Input, MGAIN="+20dB"
+0
-0.5
-1
d
B
F
S
-1.5
-2
-2.5
-3
5k
10k
15k
20k
25k
30k
35k
40k
45k
Hz
Figure 56. Frequency Response
AK4954 Crosstalk [LIN3/RIN3]
fs=96kHz, -1dBFS Input, MGAIN="+20dB"
-60
T
-70
-80
-90
d
B
-100
-110
-120
-130
-140
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 57. Crosstalk
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3. DAC (DAC HPL/HPR)
[fs=44.1kHz]
AK4954 FFT [HPL/HPR]
fs=44.1kHz, fin=1kHz, 0dBFS Input
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 58. FFT (Input level= 0dBFS)
AK4954 FFT [HPL/HPR]
fs=44.1kHz, fin=1kHz, -60dBFS Input
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
20
50
100
200
500
1k
2k
Hz
Figure 59. FFT (Input level= -60dBFS)
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[AKD4954A-B]
AK4954 FFT [HPL/HPR]
fs=44.1kHz, No Signal
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 60. FFT (No signal)
AK4954 Out of Band Noise [HPL/HPR]
fs=44.1kHz, No Signal
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
Figure 61. FFT (Out-of-band Noise)
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[AKD4954A-B]
AK4954 S/(N+D) vs. Input Level[HPL/HPR]
fs=44.1kHz, fin=1kHz
-60
-65
-70
-75
d
B
r
-80
A
-90
-85
-95
-100
-105
-110
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 62. THD+N vs. Input Level
AK4954 S/(N+D) vs. Input Frequency [HPL/HPR]
fs=44.1kHz, 0dBFS Input
-40
-50
-60
d
B
r
-70
A
-90
-80
-100
-110
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 63. THD+N vs. Input Frequency
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[AKD4954A-B]
AK4954 Linearity[HPL/HPR]
fs=44.1kHz, fin=1kHz
+0
-20
-40
d
B
r
-60
-80
A
-100
-120
-140
-140
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 64. Linearity
AK4954 Frequency Responce[HPL/HPR]
fs=44.1kHz, 0dBFS Input
+0.5
+0.4
+0.3
+0.2
d
B
r
A
+0.1
+0
-0.1
-0.2
-0.3
-0.4
-0.5
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
Hz
Figure 65. Frequency Response
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[AKD4954A-B]
AK4954 Crosstalk [HPL/HPR]
fs=44.1kHz, 0dBFS Input
-60
-70
-80
d
B
-90
-100
-110
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 66. Crosstalk
<KM114100>
2013/06
- 55 -
[AKD4954A-B]
4. DAC (DAC HPL/HPR)
[fs=96kHz]
AK4954 FFT [HPL/HPR]
fs=96kHz, fin=1kHz, 0dBFS Input
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
20
50
100
200
500
1k
2k
5k
10k
20k
40k
5k
10k
20k
40k
Hz
Figure 67. FFT (Input level= 0dBFS)
AK4954 FFT [HPL/HPR]
fs=96kHz, fin=1kHz, -60dBFS Input
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
20
50
100
200
500
1k
2k
Hz
Figure 68. FFT (Input level= -60dBFS)
<KM114100>
2013/06
- 56 -
[AKD4954A-B]
AK4954 FFT [HPL/HPR]
fs=96kHz, No Signal
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 69. FFT (No signal)
AK4954 Out of Band Noise [HPL/HPR]
fs=96kHz, No Signal
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
40
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
Figure 70. FFT (Out-of-band Noise)
<KM114100>
2013/06
- 57 -
[AKD4954A-B]
AK4954 S/(N+D) vs. Input Level [HPL/HPR]
fs=96kHz, fin=1kHz
-60
-65
-70
-75
d
B
r
A
-80
-85
-90
-95
-100
-105
-110
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 71. THD+N vs. Input Level
AK4954 S/(N+D) vs. Input Frequency [HPL/HPR]
fs=96kHz, 0dBFS Input
-40
-50
-60
d
B
r
-70
A
-90
-80
-100
-110
-120
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 72. THD+N vs. Input Frequency
<KM114100>
2013/06
- 58 -
[AKD4954A-B]
AK4954 Linearity[HPL/HPR]
fs=96kHz, fin=1kHz
+0
-20
-40
d
B
r
-60
-80
A
-100
-120
-140
-140
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 73. Linearity
AK4954 Frequency Response[HPL/HPR]
fs=96kHz, 0dBFS Input
+0.25
+0
-0.25
d
B
r
A
-0.5
-0.75
-1
-1.25
-1.5
-1.75
-2
5k
10k
15k
20k
25k
30k
35k
40k
45k
Hz
Figure 74. Frequency Response
<KM114100>
2013/06
- 59 -
[AKD4954A-B]
AK4954 Crosstalk [HPL/HPR]
fs=96kHz, 0dBFS Input
-70
-80
-90
d
B
-100
-110
-120
-130
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 75. Crosstalk
<KM114100>
2013/06
- 60 -
[AKD4954A-B]
5. DAC (DAC SPK)
[fs=44.1kHz]
AK4954 FFT [SPP/SPN]
fs=44.1kHz, fin=1kHz, -0.5dBFS Input, SLG1-0 bits="01"
+0
-20
-40
d
B
r
-60
-80
A
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 76. FFT (Input level= -0.5dBFS)
AK4954 FFT [SPP/SPN]
fs=44.1kHz, fin=1kHz, -60dBFS Input, SLG1-0 bits="01"
+0
-20
-40
d
B
r
-60
-80
A
-100
-120
-140
20
50
100
200
500
1k
2k
5k
Hz
Figure 77. FFT (Input level= -60dBFS)
<KM114100>
2013/06
- 61 -
[AKD4954A-B]
AK4954 FFT [SPP/SPN]
fs=44.1kHz, No Signal, SLG1-0 bits="01"
+0
-20
-40
d
B
r
-60
-80
A
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 78. FFT (No Signal)
AK4954 Out of Band Noise [SPP/SPN]
fs=44.1kkHz, No Signal, SLG1-0 bits="01"
+0
-20
-40
d
B
r
-60
-80
A
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
50k 100k
Hz
Figure 79. FFT (No Signal)
<KM114100>
2013/06
- 62 -
[AKD4954A-B]
AK4954 S/(N+D) vs. Input Frequency[SPP/SPN]
fs=44.1kHz, -0.5dBFS Input, SLG1-0 bits="01"
-60
-65
-70
d
B
r
-75
A
-85
-80
-90
-95
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 80. THD+N vs. Input Frequency
AK4954 Linearity [SPP/SPN]
fs=44.1kHz, fin=1kHz, SLG1-0 bits="01"
+0
-20
-40
d
B
r
-60
-80
A
-100
-120
-140
-140
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 81. Linearity
<KM114100>
2013/06
- 63 -
[AKD4954A-B]
AK4954 Frequency Responce [SPP/SPN]
fs=44.1kHz, -0.5dBFS Input, SLG1-0 bits="01"
+0
-0.1
-0.2
-0.3
d
B
r
A
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
Hz
Figure 82. Frequency Response
AK4954 THD+N ratio, Output Power vs. Input Level [SPP/SPN]
fs=44.1kHz, fin=1kHz, RL=8ohm, Po=250mW(SLG1-0 bits="01")
d
B
-40
300m
-50
250m
-60
200m
-70
150m W
-80
100m
-90
50m
-100
-40
-35
-30
-25
-20
-15
-10
-5
+0
0
dBFS
Figure 83. THD+N vs. Output Power
<KM114100>
2013/06
- 64 -
[AKD4954A-B]
6. DAC (DAC LOUT/ROUT)
[fs=44.1kHz]
AK4954 FFT [LOUT/ROUT]
fs=44.1kHz, fin=1kHz, 0dBFS Input
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 84. FFT (Input level= 0dBFS)
AK4954 FFT [LOUT/ROUT]
fs=44.1kHz, fin=1kHz, -60dBFS Input
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
20
50
100
200
500
1k
2k
Hz
Figure 85. FFT (Input level= -60dBFS)
<KM114100>
2013/06
- 65 -
[AKD4954A-B]
AK4954 FFT [LOUT/ROUT]
fs=44.1kHz, No Signal
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 86. FFT (No signal)
AK4954 Out of Band Noise [LOUT/ROUT]
fs=44.1kkHz, No Signal
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
Figure 87. FFT (Out-of-band Noise)
<KM114100>
2013/06
- 66 -
[AKD4954A-B]
AK4954 S/(N+D) vs. Input Level [LOUT/ROUT]
fs=44.1kHz, fin=1kHz
-50
-55
-60
-65
d
B
r
-70
A
-80
-75
-85
-90
-95
-100
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 88. THD+N vs. Input Level
AK4954 S/(N+D) vs. Input Frequency [LOUT/ROUT]
fs=44.1kHz, 0dBFS Input
-60
-65
-70
d
B
r
-75
A
-85
-80
-90
-95
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 89. THD+N vs. Input Frequency
<KM114100>
2013/06
- 67 -
[AKD4954A-B]
AK4954 Linearity[LOUT/ROUT]
fs=44.1kHz, fin=1kHz
+0
-20
-40
d
B
r
-60
-80
A
-100
-120
-140
-140
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 90. Linearity
AK4954 Frequency Responce [LOUT/ROUT]
fs=44.1kHz, 0dBFS Input
+0.5
+0.4
+0.3
+0.2
d
B
r
A
+0.1
+0
-0.1
-0.2
-0.3
-0.4
-0.5
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
Hz
Figure 91. Frequency Response
<KM114100>
2013/06
- 68 -
[AKD4954A-B]
AK4954 Crosstalk [LOUT/ROUT]
fs=44.1kHz, 0dBFS Input
-60
T T
TTTTTT
T
-70
-80
d
B
-90
-100
-110
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 92. Crosstalk
<KM114100>
2013/06
- 69 -
[AKD4954A-B]
7. DAC (DAC LOUT/ROUT)
[fs=96kHz]
AK4954 FFT [LOUT/ROUT]
fs=96kHz, fin=1kHz, 0dBFS Input
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
40 50
100
200
500
1k
2k
5k
10k
20k
40k
10k
20k
40k
Hz
Figure 93. FFT (Input level= 0dBFS)
AK4954 FFT [LOUT/ROUT]
fs=96kHz, fin=1kHz, 0dBFS Input
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
40 50
100
200
500
1k
2k
5k
Hz
Figure 94. FFT (Input level= -60dBFS)
<KM114100>
2013/06
- 70 -
[AKD4954A-B]
AK4954 FFT [LOUT/ROUT]
fs=96kHz, No Signal
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 95. FFT (No signal)
AK4954 Out of Band Noise [LOUT/ROUT]
fs=96kHz, No Signal
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
Figure 96. FFT (Out-of-band Noise)
<KM114100>
2013/06
- 71 -
[AKD4954A-B]
AK4954 S/(N+D) vs. Input Level [LOUT/ROUT]
fs=96kHz, fin=1kHz
-50
-55
-60
-65
d
B
r
-70
A
-80
-75
-85
-90
-95
-100
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 97. THD+N vs. Input Level
AK4954 S/(N+D) vs. Input Frequency[LOUT/ROUT]
fs=96kHz, 0dBFS Input
-60
-65
-70
d
B
r
-75
A
-85
-80
-90
-95
-100
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 98. THD+N vs. Input Frequency
<KM114100>
2013/06
- 72 -
[AKD4954A-B]
AK4954 Linearity[LOUT/ROUT]
fs=96kHz, fin=1kHz
+0
-20
-40
d
B
r
-60
-80
A
-100
-120
-140
-140
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 99. Linearity
AK4954 Frequency Responce [LOUT/ROUT]
fs=96kHz, 0dBFS Input
+0.2
+0
-0.2
-0.4
d
B
r
A
-0.6
-0.8
-1
-1.2
-1.4
-1.6
5k
10k
15k
20k
25k
30k
35k
40k
45k
Hz
Figure 100. Frequency Response
<KM114100>
2013/06
- 73 -
[AKD4954A-B]
AK4954 Crosstalk [LOUT/ROUT]
fs=96kHz, 0dBFS Input
-60
T T
-70
-80
d
B
-90
-100
-110
-120
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 101. Crosstalk
<KM114100>
2013/06
- 74 -
[AKD4954A-B]
REVISION HISTORY
Date
(YY/MM/DD)
12/06/14
Manual
Revision
KM114100
Board
Revision
0
Reason
Page
First edition
-
Contents
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information
contained in this document without notice. When you consider any use or application of AKM product
stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized
distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy
or completeness of the information contained in this document nor grants any license to any intellectual
property rights or any other rights of AKM or any third party with respect to the information in this document.
You are fully responsible for use of such information contained in this document in your product design or
applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD
PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR
APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily
high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life,
bodily injury, serious property damage or serious public impact, including but not limited to, equipment used
in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for
automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control
combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and
equipment used in finance-related fields. Do not use Product for the above use unless specifically agreed by
AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for
complying with safety standards and for providing adequate designs and safeguards for your hardware,
software and systems which minimize risk and avoid situations in which a malfunction or failure of the
Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information contained in this
document for any military purposes, including without limitation, for the design, development, use,
stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products
(mass destruction weapons). When exporting the Products or related technology or any information
contained in this document, you should comply with the applicable export control laws and regulations and
follow the procedures required by such laws and regulations. The Products and related technology may not be
used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any
applicable domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations
that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with
applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth in this
document shall immediately void any warranty granted by AKM for the Product and shall not create or extend
in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
consent of AKM.
<KM114100>
2013/06
- 75 -
3
2
J2 HP-OUT
J3 LINE-OUT
1
2
4
3
5
USBGND USB5V
1
T1
R1 0
SVDD
D
R15
22k
C24
1u
TP1
SPP
TP2
SPN
2.2u
VSS3
C
MRF
SDA
+
J1
MIC-IN
2
1
LIN3
LIN2
LIN1
VSS1
C17 C16
1n
1u
JP1
LIN-SEL
C14
1u
C12
1u
C15
1n
R7
2.2k
VSS1
R6
2.2k
VSS1
C13
1n
A
VSS1
C10
1u
R5
2.2k
R4
2.2k
VSS2
C
TVDD
R14
51
15
MCKI
R13
51
14
BICK
R12
51
13
LRCK
R11
51
12
SDTO
R10
51
11
SDTI
1
R9
1k
10
TP3
SDA
SDA
R8
1k
9
1
TP4
SCL
B
SCL
PDN
MPWR2
4
JP9
MP-RIN2
RIN3
RIN2
RIN1
3
1
JP2
RIN-SEL
LIN2
RIN2
C18
1u
SCL
C20
10u
16
8
RIN3
VSS1
3
+
SDTI
LIN3
C19
1n
32
VCOM
LIN1/DMDAT
+
B
SDTO
7
31
VSS1
DMDT
VSS1
C35
2.2u
LRCK
U1
AK4954AEN
JP4
C34
2.2u
30
AVDD
RIN1/DMCLK
C33
0.1u
29
6
+
BICK
2
C32
10u
CN
DMCK
28
AVDD
C21
0.1u
MCKI/OVF
MPWR1
C31
2.2u
27
CP
5
R20
1M
26
VSS3
TVDD
JP8
MP-LIN2
VSS2
C23
0.1u
VSS2
JP7
MP-RIN1
25
C22
10u
VSS3
1M
C30
C25
1u
SVDD
17
R19
21
C7
100u
DVDD
10u
C27
0.1u
+
HPL
VSS1
C26
10u
D3V
22
GND
2
23
C6
0.1u
TK73633AME
+
L1
HPR
1
DVDD
24
C5
0.1u
1
VSS1
TVDD
VEE
GND1
NC GND
VcontPCL
Vin Vout
NC
NC
4
3
2
1
SPP/LOUT
R3 5.1
T2
5
6
7
8
20
AVDD
R16
22k
18
R17
33
SVDD
C28
0.22u
R18
33
19
R2 0
C29
0.22u
SPN/ROUT
SVDD
JP5
1.8V
5V
3.3V
1
VSS2
JP6
MP-LIN1
JP3
D
3
R33 open
1
TK73618AME
+
C4
100u
2
1
DVDD
C3
0.1u
+
+
C1 C2
100u 0.1u
4
3
2
1
+
VDD
NC GND
VcontPCL
Vin Vout
NC
NC
+
5
6
7
8
1
REG1
PDN
C8
1u
C9
1n
A
VSS1
C11
1n
VSS1
Title
AKD4954A-B
Size
- 76 5
4
3
Document Number
A3
Date:
2
Rev
0
AK4954A
Friday, April 26, 2013
Sheet
1
1
of
3
5
4
3
2
1
5
4
3
2
1
GND
ID
D+
DVBUS
PORT3
USB Connector
T3
5
6
7
8
JP17
USB5V
USB5V
D
NC GND
VcontPCL
Vin Vout
NC
NC
4
3
2
1
C50 C51
0.1u 10u
D
+
C49
1u
TK73633AME
USBGND
C
2
RD4/SPP4
3
4
5
7
1
2
A
SCL
3
SDA
4
EN
VREF1 VREF2
RE1/AN6/CK2SPP
RB1/AN10/INT1/SCK/SCL
RE0/AN5/CK1SPP
SCL1
SCL2
SDA1
SDA2
R29
1k
C59 22p
31
XTO
30
XTI
X2
20MHz
C58 22p
29
C57
0.1u
28
C56
10u
27
26
B
25
24
RA3/AN3/Vref+
23
R30
51
22
RA2/AN2/Vref-/CVref
RA1/AN1
20
19
RA4/T0CKI/C1OUT/RCV
32
R26
100k
C55
0.1u
VDD
1
MCLR
2
PGD
3
PGC
4
GND
5
JP16 PIC
6
RA0/AN0
MCLR_N/Vpp/RE3
18
RB7/KBI3/PGD
17
RB6/KBI2/PGC
RB5/KBI1/PGM
R25 4.7k
16
14
NC/ICCK/ICPGC
12
15
RB4/AN11/KBI0/CSSPP
RA5/AN4/SS_N/HLVDIN/C2OUT
8
7
34
RB0/AN12/INT0/FLT0/SDI/SDA
RB3/AN9/CPP2/VPO
R27
100k
R28
1k
VDD1
RE2/AN7/OESPP
PCA9306DP1
GND
NC/ICPORTS
U3
PIC18F4550
RB2/AN8/INT2/VMO
11
C54
0.1u
VSS1
21
10
U4
OSC1/CLKI
NC/ICDT/ICPGD
+
9
C60 0.1u
RD6/SPP6/P1C
VDD0
8
B
OSC2/CLKO/RA6
VSS0
33
C
RC0/T1OSO/T13CKI
RD5/SPP5/P1B
13
C53
0.1u
NC/ICRST_N/ICVpp
RD7/SPP7/P1D
6
C52
10u
35
36
RC7/RX/DT/SDO
RC1/T1OSI/CCP2/UOE_N
VUSB
RC2/CCP1/P1A
37
38
RD0/SPP0
39
RD1/SPP1
40
RD2/SPP2
41
RD3/SPP3
42
RC4/D-/VM
RC5/D+/VP
43
44
RC6/TX/CK
1
C65
0.47u
R31
0
+
R32
0
A
5
Title
AKD4954A-B
USB-PDN
Size
- 77 5
4
3
A3
Date:
2
Document Number
Rev
0
Control I/F (USB)
Friday, April 26, 2013
Sheet
1
3
of
3
5
4
3
2
1
PORT2
JP11
MCKI
MCKI
C38
0.1u
DIR
2
3
EXT
SDTI
ADC
26
VCC
IN
D
13
C40
0.1u
TVDD
14
NC/GP1
15
TX0/GP2
16
TX1/GP3
17
BOUT/GP4
18
COUT/GP5
SDTO
19
20
DVDD
VOUT/GP7
21
22
23
C42
0.1u
UOUT/GP6
JP10
SDTI-SEL
EXT
DIR
BICK
25
DIR
DIR
VSS2
JP13
SDTI
24
EXT
GND
OPT-OUT
C39
10u
+
DIR
+
LRCK
C41
10u
MCKO1
JP12
LRCK
LRCK
VIN/GP0
BICK
XTL1
MCKO2
XTL0
DAUX
P/SN
12
11
EXT
OCKS0/CSN/CAD0
NC
R22
10k
1
H
3
L
C48
0.1u
6
S1
SW DIP-4
H (ON)
L(OFF)
OCKS1
DIF0
DIF1
DIF2
8
7
6
5
5
4
3
2
RP1
47k
B
RX3
1
48
VSS4
47
46
45
VSS3
7
C47
0.47u
C45 0.1u
+
2
SW1
RESET
RX2
IPS0/RX4
TEST1
INT0
41
R24
10k
8
1
2
3
4
DIF0/RX5
37
A
OCKS1/CCLK/SCL
INT1
K
36
TEST2
VCOM
B
CM1/CDTI/SDA
40
35
DIF1/RX6
R
34
CM0/CDTO/CAD1
39
33
VSS1
AVDD
32
DIF2/RX7
PDN
38
31
PDN
9
1
2
3
4
C44 5p
USB-PDN
D1
HSU119
XTI
RX1
1
30
IPS1/IIC
U2
AK4118A
C43 5p
R23 2.2k
10
C
XTO
44
2
C
X1
11.2896MHz
29
NC
JP15
SDTO
43
28
SDTO
RX0
27
JP14
BICK
42
D
1
D3V
C46
10u
R21 470
C36
0.1u
PORT1
1
2
3
OUT
GND
VCC
OPT-IN
A
A
Title
AKD4954A-B
Size
- 78 5
4
3
A3
Date:
2
Document Number
Rev
0
DIR/DIT
Friday, April 26, 2013
Sheet
1
2
of
3
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