5 4 3 2 1 D D EVB-LAN9355 Page No. C Schematic Page 1 Title 2 Block Diagram 3 Power Supply & RST 4 LAN9355 (Part1) 5 Copper Mode Interface 6 SFP Interface 7 STRAP,GPIO,I2C & FXLOS 8 LAN9355 (Part2) 9 MII Interface C B B A A Chennai India 5 4 3 2 Part Number: EVB-LAN9355 Size: B Project Name: Date: Tuesday, June 30, 2015 LAN9355 Page: Board Name: TITLE Rev EVB-LAN9355-REV-A Sheet 1 1 of A 9 5 4 3 2 1 EVB-LAN9355 Block Diagram D 40 Pin MII Connector (Male) 40 Pin MII Connector (Female) 40 Pin MII Connector (Female) 40 Pin MII Connector (Male) MII/RMII/TMII MII/RMII/TMII Mode Switch D Port 0 Port 1 Power Supply Module C I2C EEPROM/ Header Microchip LAN9353 C Reset Switch Straps Jumpers Crystal Port 2 B B 10/100 Ethernet Magnetics & RJ45 Fiber Trasnceiver(SFP) Port 2 A A Chennai India 5 4 3 2 Part Number: EVB-LAN9355 Size: B Project Name: Date: Thursday, June 25, 2015 LAN9355 Page: Board Name: Block Diagram Rev EVB-LAN9355-REV-A Sheet 1 2 of A 9 5 4 3 2 1 POWER SUPPLY 3 5V_SW 3 R1 0 2A/0.05DCR 2 Switch, SPDT, Slide P/N:1101M2S3CQE2 J1 C2 10uF 25V PJ-002AH EN12_1 2 1 VIN ENABLE C3 3_Amp VOUT TRIM GND 4 5 TP9 BLACK R2 1K VOUT_3V3 TP10 BLACK D C1 3 0.1uF OKR-T/3-W12-C R3 3.30K 1% (Ra) R4 470E 1% R4A 33E 1% (Rb) C4 C5 10uF 4.7uF DNP 1 D U1 FB1 2 A 1 0.1uF "3V3 Present" 5V_EXT 3V3 3V3 D1 GRN C 5V SW1 1 TP2 ORANGE 3.3 V REGULATOR, 3A ( 3V3 fixed when Rb=470e) 2 TP1 RED 3V3 3V3 3V3 C C RESET NDS355AN_NMOS 1 R8 3 1K D RST# Q1 1 G 5 RESET# 3 MR# 2 3V3 VDD 4 5 U2 2 1/10W 1% 2 sw_pb_2P 1 R7 100 GND SW2 R5 4.75K 1% 0.1uF 2 1 C6 R6 10.0K 1/10W 1% RED U3 S 2 4 TPS3125 74LVC1G14 1 3 SOT23_5 Threshold = 2.64V Delay = 180ms R9 2.2K 1 A C 2 D2 "Reset" Reset Generator B B A A Chennai India 5 4 3 2 Part Number: EVB-LAN9355 Size: B Project Name: Date: Wednesday, June 24, 2015 LAN9355 Page: Board Name: Power Supply & RST Rev EVB-LAN9355-REV-A Sheet 1 3 of A 9 5 4 3V3 3 2 1 Power Supply Filtering VDD33TXRX1 FB2 3V3 2A/0.05DCR VDDCR VDD12TX1 VDD12TX2 0.1uF BLM18EG221SN1D C20 C21 C22 470pF 0.1uF 0.1uF C19 1uF D FB5 2A/0.05DCR 79 82 6 35 56 17 30 43 55 65 81 5 U6A 74 87 VDD12TX1 VDD12TX2 0.1uF C25 Low ESR C24 C18 C16 C17 0.1uF 0.1uF 0.1uF C14 C13 C12 DNP C11 C15 0.1uF 0.1uF TP3 SMT VDDCR VDD33TXRX1 VDD33TXRX2 C23 1.0uF DNP 3V3 2A/0.05DCR 0.1uF 3V3 FB4 1.0uF 3V3 0.1uF 2A/0.05DCR C10 C9 0.1uF VDD33TXRX2 0.1uF FB3 C8 DNP 1.0uF C7 1.0uF DNP D IRQ ATEST/FXLOSEN 12 62 8 59 B I2C2_SCL I2C2_SDA GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 61 60 66 64 63 47 27 26 14 13 REG_EN RBIAS RST# VDDCR1 VDDCR2 VDDCR3 VDD12TX1 VDD12TX2 TXNA TXPA RXNA RXPA 75 76 77 78 FXSDA/FXLOSA TXNA TXPA RXNA RXPA IRQ ATEST/FXLOSEN TESTMODE I2CSCL/EESCL/TCK I2CSDA/EESDA/TMS TXNB TXPB RXNB RXPB FXSDENB/FXSDB/FXLOSB GPIO0/LED0/TDO/LEDPOL0/MNGT0 GPIO1/LED1/TDI/LEDPOL1/P1_INTPHY GPIO2/LED2/LEDPOL2/E2PSIZE GPIO3/LED3/LEDPOL3/EEEEN GPIO4/LED4/LEDPOL4/1588EN GPIO5/LED5/LEDPOL5/PHYADD GPIO6 GPIO7 11 18 29 31 45 67 68 88 LAN9355_QFN88 86 85 84 83 10 TXNB TXPB RXNB RXPB B FXSDB/FXLOSB GND RST# TP4 WHITE DNP 7 80 9 89 RBIAS 12.1K 1% INT PORT0 R10 INT PORT1 REG_EN 18pF FXSDENA/FXSDA/FXLOSA NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 C27 OSCVDD12 OSCI OSCO OSCVSS OSC 1 3V3 3 1 2 4 OTHER SIGNALS OSCI OSCO VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 POWER 25.000MHz 25ppm Y1 I2C 18pF 2 C26 VDD33BIAS VDD33 C Note: OSCVSS need to connect to Chip gnd. VDD33TXRX1 VDD33TXRX2 C A A Chennai India 5 4 3 2 Part Number: EVB-LAN9355 Size: B Project Name: Date: Wednesday, June 24, 2015 LAN9355 Page: Board Name: LAN9355 (Part1) Rev EVB-LAN9355-REV-A Sheet 1 4 of A 9 5 4 3 2 R61 LINK/ACT LED2_ANODE T1 Pulse J0011D01BNL 9 0E 10 FB6 R11 49.9 1/10W 1% TXPA DNP R16 R17 0 0 TXNA DNP R18 R19 0 0 FX_SFP-TXPA R12 49.9 1/10W 1% R13 49.9 1/10W 1% R14 49.9 1/10W 1% R15 0 GRN 1 COP-TXPA 4 FX_SFP-TXNA A C D 330E LED2_CATHODE VDD33TXRX1 PORT1 1 2 COP-TXNA RJ45 D XMIT TD+ 75 1 75 TXCT 4&5 TD- 2 Default assembly LED1 (Green) = LINK/ACT C31 10pF 50V 5% DNP 7 8 50V 10% 6 2 kV 1000 pF NC CHS GND Note: Capacitors C10 through C13 are optional for EMI purposes and are not populated on the LAN8740/41 evaluation board. These capacitors are required for operation in an EMI constrained environment. YEL C A1 C30 10pF 50V 5% DNP 7&8 12 C C29 10pF 50V 5% DNP 75 RD- GND C28 10pF 50V 5% DNP C32 0.022uF 75 RXCT C1 6 3 11 5 COP-RXNA MTG1 FX_SFP-RXNA MTG 0 0 RD+ 16 DNP R22 R23 LED2 (Yellow) = SPEED RCV 3 COP-RXPA 15 FX_SFP-RXPA GND1 0 0 14 RXNA DNP R20 R21 13 RXPA R62 R24 330E LED0_CATHODE 0 LED0_ANODE SPEED RES1210 R102 LINK/ACT FB7 LED5_ANODE 0E 10 T2 Pulse J0011D01BNL B TXPB TXNB R25 49.9 1/10W 1% DNP R30 R31 0 0 FX_SFP-TXPB DNP R32 R33 0 0 FX_SFP-TXNB DNP R34 R35 0 0 R26 49.9 1/10W 1% R27 49.9 1/10W 1% R28 49.9 1/10W 1% A C 9 PORT2 330E LED5_CATHODE VDD33TXRX2 R29 0 GRN 1 COP-TXPB 4 2 COP-TXNB RJ45 B XMIT TD+ 75 75 1 TXCT 4&5 TD- 2 LED1 (Green) = LINK/ACT NC CHS GND YEL A A1 8 C1 50V 10% 12 Note: Capacitors C10 through C13 are optional for EMI purposes and are not populated on the LAN8740/41 evaluation board. These capacitors are required for operation in an EMI constrained environment. C36 10pF 50V 5% DNP 11 C35 10pF 50V 5% DNP 6 2 kV 1000 pF MTG1 C34 10pF 50V 5% DNP 7 3 7&8 RD- MTG C33 10pF 50V 5% DNP C37 0.022uF 75 16 Note: FB6 and FB7 to be zero ohms 6 COP-RXNB 75 RXCT 15 FX_SFP-RXNB GND1 5 0 0 LED2 (Yellow) = SPEED RD+ GND A DNP R36 R37 3 COP-RXPB 14 RXNB FX_SFP-RXPB 13 RXPB RCV R103 R38 0 Chennai India 330E LED3_CATHODE LED3_ANODE SPEED RES1210 5 4 3 2 Part Number: EVB-LAN9355 Size: B Project Name: Date: Wednesday, June 24, 2015 LAN9355 Page: Board Name: Copper Mode Interface Rev EVB-LAN9355-REV-A Sheet 1 5 of A 9 5 4 3V3 R39 82 D R40 82 R41 49.9 R42 49.9 Note:Place capacitors, and resistors close to FOT 3 3V3 Fiber Port 1 :SFP Interface R43 82 C38 0.1uF R44 82 R45 49.9 2 1 Note:Place capacitors, and resistors close to FOT Fiber Port 2 :SFP Interface R46 49.9 Assemble 0E at C38,C40,C42,C44 FX_SFP-RXNA Assemble 0E at C39,C41,C43,C45 C39 0.1uF C41 0.1uF C43 0.1uF C45 R48 100 DNP 0.1uF D FX_SFP-RXNB C40 0.1uF FX_SFP-RXPA FX_SFP-RXPB C42 FX_SFP-TXPA 0.1uF FX_SFP-TXPB 3V3 R47 100 DNP 3V3 SFP_VCCT C44 L2 SFP_VCCR FX_SFP-TXNA 1uH C48 10uF 16V C49 0.1uF R51 130 R52 130 C50 + 10uF 16V DNP SFP_RD2+ SFP_RD2- C47 0.1uF + SFP_TD2SFP_TD2+ SFP_RD+ SFP_RD- SFP_TDSFP_TD+ R50 130 C46 10uF 16V DNP + L1 1uH SFP_VCCR2 FX_SFP-TXNB 0.1uF R49 130 SFP_VCCT2 C52 + 10uF 16V C51 0.1uF L3 L4 C B R53 4.7K R54 4.7K C55 0.1uF Note:Place resistors close to ASIC J3 FTLF1217P2 R55 4.7K 31 30 29 28 27 26 25 24 23 22 21 C57 0.1uF SFP_VCCT2 1 2 3 4 5 6 7 8 9 10 SFP_VCCT C54 + 10uF 16V VeeT TXFault TX Disable MOD-DEF(2) MOD-DEF (1) MOD-DEF (0) Rate Select LOS VeeR VeeR1 J2 FTLF1217P2 VeeT TXFault TX Disable MOD-DEF(2) MOD-DEF (1) MOD-DEF (0) Rate Select LOS VeeR VeeR1 ASIC 31 30 29 28 27 26 25 24 23 22 21 C56 + 31 10uF 30 16V 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 resistors close to 31 30 29 28 27 26 25 24 23 22 21 VeeT1 TDTD+ VeeT2 VccT VccR VeeR2 RD+ RDVeeR3 20 19 18 17 16 15 14 13 12 11 VeeT1 TDTD+ VeeT2 VccT VccR VeeR2 RD+ RDVeeR3 Note:Place 1uH 1uH 20 19 18 17 16 15 14 13 12 11 C C53 0.1uF R56 4.7K R57 4.7K FXSDA/FXLOSA R58 4.7K R59 4.7K B R60 4.7K FXSDB/FXLOSB A A Note: Fiber mode related components are Not Populated on EVB (Default) Chennai India 5 4 3 2 Part Number: EVB-LAN9355 Size: B Project Name: Date: Wednesday, June 24, 2015 LAN9355 Page: Board Name: SFP Interface Rev EVB-LAN9355-REV-A Sheet 1 6 of A 9 5 4 3 2 GPIO [0:5] & LED_POL_Strap 1 3V3 I2C EEPROM 3V3 GPIO3 GPIO5 R82 10.0K R83 10.0K VCC A0 A1 A2 GPIO0 WP 1 2 2 2 D I2C2_SCL I2C EEPROM Higher size Above 16K(2K X 8) [Default-512KBIT] 1 3 1 GPIO3 3 J15 3 GPIO4 I2C2_SDA 6 2 2 2 GPIO1 5 Note: U5: IC DIP Socket. Different sizes can be mounted I2C EEPROM Lower size Below 16K(2K X 8) R86 0 J13 1 3 1 3 GPIO2 R85 0 J14 J8 1 3 J9 1 J7 R84 1K 2 R74 1K 2 2 R73 0 SDA SCL 7 24FC512 R72 0 0.1uF 3 1 2 3 LED3_CATHODE LED5_CATHODE 2 2 4.7K 2 2 R81 10.0K LED1_CATHODE LED4_CATHODE 2 LED0_CATHODE LED2_CATHODE R66 LED3_ANODE LED5_ANODE 1 R71 10.0K 3 1 3 1 LED1_ANODE LED4_ANODE 1 R70 10.0K J12 2 J10 1 1 1 LED0_ANODE LED2_ANODE R69 10.0K 3 1 J11 2 J5 1 D 2 J6 2 J4 3 1 3 1 U5 2K GPIO4 R67 GPIO1 3V3 2K GPIO2 3V3 8 GPIO0 3V3 GND 3V3 4 3V3 R68 C58 3V3 GPIO5 C C FX_Mode_Strap_1 & 2 Port 2 LEDs Port 1 LEDs LED0_ANODE LED0_CATHODE LED0_ANODE LED0_CATHODE DNP D3 1 GRN A Aardvark - I2C Connector SPEED 2 C LED3_CATHODE LED3_CATHODE FULL DUPLEX / Collision LED1_ANODE LED1_CATHODE LED2_ANODE LED2_CATHODE LED2_ANODE LED2_CATHODE D4 1 GRN A DNP D6 1 GRN A LED3_ANODE LED3_ANODE SPEED LED4_ANODE C LED4_CATHODE LINK/ACT DNP 2 D5 1 GRN A C LED5_ANODE LED5_ANODE LED5_CATHODE LED5_CATHODE D7 1 GRN A MODE PORT 2 C J16 1 3 5 7 9 I2C2_SCL I2C2_SDA FULL DUPLEX / Collision 2 3V3 2 C LINK/ACT DNP 2 D8 1 GRN A C Poupulate Copper (Default) R76 FXSDA/FXLOSA R75 DNP 10K R76 10K R78 DNP 10K R80 10K PORT1 2 4 6 8 10 PORT2 HEADER 5X2 Fiber R75 Copper (Default) R80 Fiber R78 3V3 FXSDB/FXLOSB 3V3 1 2 GPIO6 R99 3 10K B B J20 Strap Name Logic Connector 0 J4,J7 (2&3) 1 J4,J7 (1&2) (Default) FX_Los_Strap_1 & 2 LED Polarity Strap 3V3 The LED is set as active high. 3V3 LED0/GPIO0/MNGT0 0 LED1/GPIO1/ P1_INTPHY 1 0 LED2/GPIO2/E2PSIZE The LED is set as active low, J5,J8 (2&3) (Default) The LED is set as active high. J5,J8 (1&2) The LED is set as active low, J6,J9 (2&3) The LED is set as active high. EEPROM Size=1K bits (128 x 8) through 16K bits (2K x 8) 0 J10,J13 (2&3) The LED is set as active high. EEE Disable 1 J10,J13 (1&2) (Default) The LED is set as active low, EEE Enable 0 J11,J14 (2&3) The LED is set as active high. 1588 Disable 1 J11,J14 (1&2) (Default) The LED is set as active low, 0 J12,J15 (2&3) (Default) The LED is set as active high. PHYADD=0,1,2 J12,J15 (1&2) The LED is set as active low, PHYADD =1,2,3 LED4/GPIO4/1588EN LED5/GPIO5/PHYADD 1 5 3 10K R77 R79 Ref.Voltage Poupulate DNP 3V3 Poupulate Poupulate 1V5 Function DNP 1 2 3 4 5 6 7 8 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 (Default) Poupulate (Default) R77 10K DNP Above 2 V selects FX-LOS for ports 1 and 2 Level of 1.5 V selects FX-LOS for port 1 and FX-SD/copper twisted pair for port 2 further determined by FXSDB J21 The LED is set as active low, EEPROM Size=32K bits (4K x 8) through 512K bits (64K x 8) or 4Mbits (512K x 8) (LAN9252 only) LED3/GPIO3/EEEEN 2 GPIO7 R100 J6,J9 (1&2) (Default) 1 A 1 ATEST/FXLOSEN R79 10K Level of 0V Selects FX-SD / copper twisted pair for ports A and B further determined by FXSDA and FXSDB. 0 (Default) A J27 1588 Enable HEADER 8 4 3 Chennai India 2 Part Number: EVB-LAN9355 Size: B Project Name: Date: Thursday, June 25, 2015 LAN9355 Page: Board Name: STRAP,GPIO,I2C & FXLOS Rev EVB-LAN9355-REV-A Sheet 1 7 of A 9 5 4 SW5 10.0K 1 P0_OUT/REF_CLK_MODE0 R104 3 3V3 2 P0_OUTD0_MODE1 P0_MODE0 SW6 10.0K 1 R105 P0_OUTD1_MODE2 3V3 2 P0_OUTD2_MODE3 SW8 10.0K 1 SW9 10.0K 1 P0_DUPLEX 2 P0_OUTER_SPEED R109 SW10 10.0K 1 JS102011CQN SW13 3V3 2 SW14 3V3 3 2 P1__MDC_DUPLEX JS102011CQN 3V3 SW16 3V3 2 10.0K 1 D P1_MODE1 3 R114 JS102011CQN R113 3V3 2 10.0K 1 P1_OUTD0_MODE1 P1_MODE2 R112 3V3 P1_MODE3 JS102011CQN 2 10.0K 1 P1_OUTD1_MODE2 P0_MODE3 3V3 2 10.0K 1 2 R115 10.0K 1 P1_OUTER_MDIO_SPEED 3 3 3 R108 R111 3 SW15 3V3 P1_OUTD2_MODE3 P1_MODE0 3 JS102011CQN JS102011CQN 3V3 R110 3 P0_MODE2 3 R106 R107 1 SW12 2 10.0K 1 P1_OUT/REF_CLK_MODE0 P0_MODE1 JS102011CQN JS102011CQN SW7 10.0K 1 3V3 2 3 3 D 2 SW11 3 JS102011CQN JS102011CQN JS102011CQN JS102011CQN Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa . Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa . PORT 1 MODE STRAP MAPPING PORT 0 MODE STRAP MAPPING C P1_INTPHY (J5 & J8) B P0_MODE3 (SW8) P0_MODE2 (SW7) P0_MODE1 (SW6) P0_MODE0 (SW5) Port 0 Mode x 0 0 x x x 0 1 0 x MII PHY x 0 1 1 0 Turbo MII PHY 12 ma x 0 1 1 1 Turbo MII PHY 16 ma MII MAC (Default) x 1 0 0 x RMII MAC clock in x 1 0 1 0 RMII MAC clock out 12ma x 1 0 1 1 RMII MAC clock out 16ma x 1 0 x RMII PHY clock in 1 P1_INTPHY (J5 & J8) x 1 1 1 0 RMII PHY clock out 12ma x 1 1 1 1 RMII PHY clock out 16ma P1_MODE3 (SW12) P1_MODE2 (SW13) P1_MODE1 (SW14) P1_MODE0 (SW11) C Port 1 Mode 0 0 0 x x MII MAC (Default) 0 0 1 0 x MII PHY 0 0 1 1 0 Turbo MII PHY 12 ma 0 0 1 1 1 Turbo MII PHY 16 ma 0 1 0 0 x RMII MAC clock in 0 1 0 1 0 RMII MAC clock out 12ma 0 1 0 1 1 RMII MAC clock out 16ma 0 1 1 0 x RMII PHY clock in 0 1 1 1 0 RMII PHY clock out 12ma 0 1 1 1 1 RMII PHY clock out 16ma 1 x x x x Internal PHY B U6B A P0_DUPLEX P0_MDIO P0_MDC P0_IND3 R116 P0_IND2 R117 P0_IND1 R118 P0_IND0 R119 P0_INDV P0_INCLK R120 P0_INER P0_OUTER_SPEED P0_OUT/REF_CLK_MODE0 P0_OUTDV R121 P0_OUTD0_MODE1 R122 P0_OUTD1_MODE2 R123 P0_OUTD2_MODE3 R124 P0_OUTD3 R125 P0_COL P0_CRS P0_MDIO P0_MDC P0_IND3 P0_IND2 P0_IND1 P0_IND0 P0_INDV P0_INCLK P0_INER P0_OUTER_SPEED P0_OUT/REF_CLK_MODE0 P0_OUTDV P0_OUTD0_MODE1 P0_OUTD1_MODE2 P0_OUTD2 P0_OUTD3 P0_COL P0_CRS 33 33 33 33 33 33 33 33 33 33 54 58 57 42 41 39 38 37 40 46 28 36 34 33 32 22 21 70 69 P0_DUPLEX P1_DUPLEX/P1_MDC P0_MDIO P1_IND3 P0_MDC P1_IND2 P0_IND3 P1_IND1 P0_IND2 P1_IND0 P0_IND1 P1_INDV P0_IND0 P1_INCLK P0_INDV P1_INER P0_INCLK P1_OUTER/P1_SPEED/P1_MDIO P0_INER P1_OUTCLK/P1_REFCLK/P1_MODE0 P0_OUTER/P0_SPEED P1_OUTDV P0_OUTCLK/P0_REFCLK/P0_MODE0 P1_OUTD0/P1_MODE1 P0_OUTDV P1_OUTD1/P1_MODE2 P0_OUTD0/P0_MODE1 P1_OUTD2/P1_MODE3 P0_OUTD1/P0_MODE2 P1_OUTD3 P0_OUTD2/P0_MODE3 P1_COL P0_OUTD3 P1_CRS P0_COL P0_CRS 71 15 16 23 24 25 20 19 44 50 53 52 51 49 48 72 73 Emulated Link Partner Default Advertised Ability R126 R127 R128 R129 33 33 33 33 R130 33 R131 33 R132 R133 R134 R135 33 33 33 33 P1__MDC_DUPLEX P1_IND3 P1_IND2 P1_IND1 P1_IND0 P1_INDV P1_INCLK P1_INER P1_OUTER_MDIO_SPEED P1_OUT/REF_CLK_MODE0 P1_OUTDV P1_OUTD0_MODE1 P1_OUTD1_MODE2 P1_OUTD2_MODE3 P1_OUTD3 P1_COL P1_CRS SW9 (P0_DUPLEX) / SW15 (P1_DUPLEX) SW10 (P0_SPEED) / SW16 (P1_SPEED) 1 0 ADVERTISED LINK PARTNER ABILITY (Bits 8,7,6,5) 10BASE-T full-duplex (0010) 1 1 100BASE-X full-duplex (1000) (Default) 0 0 10BASE-T half-duplex (0001) 0 1 100BASE-X half-duplex (0100) A SW21 2 P1_OUTER_MDIO_SPEED 1 3 P1_MDIO Chennai India P1_OUTER LAN9355_QFN88 JS102011CQN P1 MDIO or OUTER selection switch Default (1-2) 5 4 3 2 Part Number: EVB-LAN9355 Size: B Project Name: Date: Thursday, June 25, 2015 LAN9355 Page: Board Name: LAN9355 (Part2) Rev EVB-LAN9355-REV-A Sheet 1 8 of A 9 5 4 3 2 1 MII Male for External MAC Board AMP - 6-5174218-2 MII_RA 10uF 5V 0.1uF MII Female for External PHY Board C59 2 C60 3 Default Short 1-3 10uF JS102011CQN SW18 2 PHY_RXCLK0 PHY_TXCLK0 1 3 C62 0.1uF P0_MDIO P0_MDC P0_OUTD3 P0_OUTD2 P0_OUTD1_MODE2 P0_OUTD0_MODE1 P0_OUTDV P0_OUT/REF_CLK_MODE0 P0_OUTER_SPEED P0_INER P0_INCLK P0_INDV P0_IND0 P0_IND1 P0_IND2 P0_IND3 P0_COL P0_CRS R136 R137 0E 0E MAC_TXCLK0 MAC_RXCLK0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 +5V[3] MDIO MDC RXD3 RXD2 RXD1 RXD0 RX_DV RX_CLK RX_ER TX_ER TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 COL CRS +5V[4] +5V[1] COMMON[1] COMMON[2] COMMON[3] COMMON[4] COMMON[5] COMMON[6] COMMON[7] COMMON[8] COMMON[9] COMMON[10] COMMON[11] COMMON[12] COMMON[13] COMMON[14] COMMON[15] COMMON[16] COMMON[17] COMMON[18] +5V[2] Chassis2 Chassis1 J18 D 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P0_INCLK P0_OUTER_SPEED DNP P0_OUT/REF_CLK_MODE0 R138 R139 R140 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 D Default Short 1-3 JS102011CQN J19 Switch Description Settings P0_MDIO P0_MDC P0_IND3 P0_IND2 P0_IND1 P0_IND0 P0_INDV 0E PHY_RXCLK0 P0_INER 0E TXER0 0E PHY_TXCLK0 P0_OUTDV P0_OUTD0_MODE1 P0_OUTD1_MODE2 P0_OUTD2 P0_OUTD3 P0_COL P0_CRS MAC_RXCLK0 MAC_TXCLK0 1 FEMALE MII CONN AMP - 749069-4 C61 SW17 5V 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Mode SW17 (1-3) Default TX Clock used as a Reference Clock RMII MAC SW17 (1-2) RX Clock used as a Reference Clock RMII MAC SW18 (1-3) Default Reference clock used as a TX clock RMII PHY RMII PHY Reference clock used as a RX clock SW18 (1-2) Note: 1. For Switches to short 1-3, Knob Position should be at 1-2 and vice versa . 2. External PHY considered LAN8742 C PORT 0 MII Male for External MAC Board AMP - 6-5174218-2 MII_RA 10uF 5V 0.1uF MII Female for External PHY Board C63 2 C65 3 Default Short 1-3 10uF JS102011CQN SW20 2 PHY_RXCLK1 PHY_TXCLK1 1 3 C66 0.1uF B P1_MDIO P1__MDC_DUPLEX P1_OUTD3 P1_OUTD2_MODE3 P1_OUTD1_MODE2 P1_OUTD0_MODE1 P1_OUTDV P1_OUT/REF_CLK_MODE0 P1_OUTER P1_INER P1_INCLK P1_INDV P1_IND0 P1_IND1 P1_IND2 P1_IND3 P1_COL P1_CRS R145 R146 0E 0E MAC_TXCLK1 MAC_RXCLK1 +5V[3] MDIO MDC RXD3 RXD2 RXD1 RXD0 RX_DV RX_CLK RX_ER TX_ER TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 COL CRS +5V[4] +5V[1] COMMON[1] COMMON[2] COMMON[3] COMMON[4] COMMON[5] COMMON[6] COMMON[7] COMMON[8] COMMON[9] COMMON[10] COMMON[11] COMMON[12] COMMON[13] COMMON[14] COMMON[15] COMMON[16] COMMON[17] COMMON[18] +5V[2] Chassis2 Chassis1 J23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Default Short 1-3 JS102011CQN J24 Switch P1_INCLK P1_MDIO P1__MDC_DUPLEX P1_IND3 P1_IND2 P1_IND1 P1_IND0 P1_INDV 0E PHY_RXCLK1 P1_INER 0E TXER1 0E PHY_TXCLK1 P1_OUTDV P1_OUTD0_MODE1 P1_OUTD1_MODE2 P1_OUTD2_MODE3 P1_OUTD3 P1_COL P1_CRS R147 DNPR148 P1_OUTER P1_OUT/REF_CLK_MODE0 R149 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MAC_RXCLK1 MAC_TXCLK1 1 FEMALE MII CONN AMP - 749069-4 C64 SW19 5V Description Settings 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Mode B SW19 (1-3) Default TX Clock used as a Reference Clock RMII MAC SW19 (1-2) RX Clock used as a Reference Clock RMII MAC SW20 (1-3) Default Reference clock used as a TX clock RMII PHY SW20 (1-2) Reference clock used as a RX clock RMII PHY Note: 1. For Switches to short 1-3, Knob Position should be at 1-2 and vice versa . 2. External PHY considered LAN8742 PORT 1 A A Pullup for MDIO(common for all PHY) signal J29 P1_INDV 1 2 P1_CRS J26 = Default open J26 = Short, when Pullup is required J25 P0_INDV 1 2 P0_CRS P0_MDIO P0_MDC Short option for RXDV & CRS for RMII mode 5 TP7 TP8 TP5 TP6 2 1 J26 1.5K R141 10K R142 DNP 3V3 3V3 R143 R144 4 10K P0_OUTDV 49.9K DNP TXER0 J30 = Default open J30 = Short, when Pullup is required P1_MDIO 2 P1__MDC_DUPLEX 3 1 J30 3V3 1.5K R150 10K R151 DNP 3V3 R152 R153 10K 49.9K DNP 2 Chennai India P1_OUTDV TXER1 Part Number: EVB-LAN9355 Size: B Project Name: Date: Thursday, June 25, 2015 LAN9355 Page: Board Name: mii conn Rev EVB-LAN9355-REV-A Sheet 1 9 of A 9