Si5442DU

Si5442DU
Vishay Siliconix
N-Channel 20 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
20
RDS(on) () Max.
(A)a
ID
0.0100 at VGS = 4.5 V
25
0.0115 at VGS = 2.5 V
25
0.0135 at VGS = 1.8 V
25
• TrenchFET® Power MOSFET
• Thermally Enhanced PowerPAK®
ChipFET® Package
- Small Footprint Area
- Low On-Resistance
- Thin 0.8 mm Profile
• 100% Rg Tested
• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
Qg (Typ.)
16.6 nC
PowerPAK ChipFET Single
1
APPLICATIONS
2
D
D
D
4
D
D
8
G
D
7
•
•
•
•
3
Load Switch, PA Switch, and for Portable Applications
Point-of-Load
DC/DC Converters
Power Management
D
S
6
S
5
1.9
Marking Code
mm
AQ
XXX
Bottom View
Lot Traceability
and Date Code
G
Part # Code
Ordering Information:
Si5442DU-T1-GE3 (Lead (Pb)-free and Halogen-free)
S
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (TJ = 150 °C)
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
ID
TC = 25 °C
TA = 25 °C
TC = 25 °C
TC = 70 °C
Maximum Power Dissipation
TA = 25 °C
TA = 70 °C
Operating Junction and Storage Temperature Range
Continuous Source-Drain Diode Current
Unit
V
25a
25a
12.4b, c
9.9b, c
60
IDM
Pulsed Drain Current (t = 300 µs)
Soldering Recommendations (Peak
Limit
20
±8
Symbol
VDS
VGS
A
25a
2.6b, c
31
20
IS
PD
W
3.1b, c
2b, c
- 55 to 150
260
TJ, Tstg
Temperature)d, e
°C
THERMAL RESISTANCE RATINGS
t5s
Symbol
RthJA
Typical
34
Maximum
40
Steady State
RthJC
3
4
Parameter
Maximum Junction-to-Ambientb, f
Maximum Junction-to-Case (Drain)
Unit
°C/W
Notes:
a. Package limited.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 90 °C/W.
Document Number: 63233
S13-2149-Rev. B, 14-Oct-13
For technical questions, contact: [email protected]
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5442DU
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
Parameter
Symbol
Test Conditions
Min.
VDS
VGS = 0 V, ID = 250 µA
20
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
VDS/TJ
VDS Temperature Coefficient
V
21
ID = 250 µA
mV/°C
VGS(th) Temperature Coefficient
VGS(th)/TJ
Gate-Source Threshold Voltage
VGS(th)
VDS = VGS , ID = 250 µA
0.9
V
IGSS
VDS = 0 V, VGS = ± 8 V
± 100
nA
VDS = 20 V, VGS = 0 V
1
VDS = 20 V, VGS = 0 V, TJ = 55 °C
10
Gate-Source Leakage
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currenta
ID(on)
Drain-Source On-State Resistancea
RDS(on)
Forward Transconductancea
gfs
VDS 5 V, VGS = 4.5 V
-3
0.4
µA
A
20
VGS 4.5 V, ID = 8 A
0.0080
0.0100
VGS 2.5 V, ID = 7 A
0.0090
0.0115
VGS 1.8 V, ID = 4 A
0.0100
0.0135
VDS = 10 V, ID = 8 A
65

S
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
1700
VDS = 10 V, VGS = 0 V, f = 1 MHz
280
115
VDS = 10 V, VGS = 8 V, ID = 15 A
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Gate Resistance
Rg
tr
Rise Time
td(off)
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Turn-Off Delay Time
nC
2
f = 1 MHz
VDD = 10 V, RL = 1 
ID  10 A, VGEN = 4.5 V, Rg = 1 
0.28
1.4
2.8
10
20
15
30
35
70
10
20
td(on)
10
20
10
20
30
60
10
20
td(off)
VDD = 10 V, RL = 1 
ID  10 A, VGEN = 8 V, Rg = 1 
tf
Fall Time
45
25
tf
tr
Rise Time
29
16.6
1.9
VDS = 10 V, VGS = 4.5 V, ID = 15 A
td(on)
Turn-on Delay Time
pF

ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulse Diode Forward Current
ISM
Body Diode Voltage
VSD
TC = 25 °C
25
60
IS = 10 A, VGS = 0 V
A
0.8
1.2
Body Diode Reverse Recovery Time
trr
20
40
ns
Body Diode Reverse Recovery Charge
Qrr
10
20
nC
Reverse Recovery Fall Time
ta
Reverse Recovery Rise Time
tb
IF = 10 A, dI/dt = 100 A/µs, TJ = 25 °C
11
9
V
ns
Notes:
a. Pulse test; pulse width  300 µs, duty cycle  2 %
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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2
For technical questions, contact: [email protected]
Document Number: 63233
S13-2149-Rev. B, 14-Oct-13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5442DU
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
60
20
VGS = 5 V thru 2 V
VGS = 1.5 V
16
ID - Drain Current (A)
ID - Drain Current (A)
50
40
30
20
12
8
TC = 25 °C
4
10
TC = 125 °C
VGS = 1 V
TC = - 55 °C
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.3
0.6
0.9
1.2
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.014
2500
0.012
2000
C - Capacitance (pF)
RDS(on) - On-Resistance (Ω)
0.0
VGS = 1.8 V
0.010
VGS = 2.5 V
0.008
VGS = 4.5 V
0.006
1.5
Ciss
1500
1000
Coss
500
Crss
0.004
0
0
10
20
30
40
50
60
0
4
8
12
16
ID - Drain Current (A)
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
20
1.6
8
RDS(on) - On-Resistance (Normalized)
VGS - Gate-to-Source Voltage (V)
VGS = 4.5 V, 2.5 V
ID = 15 A
VDS = 10 V
6
VDS = 16 V
VDS = 5 V
4
2
ID = 8 A
1.4
VGS = 1.8 V
1.2
1.0
0.8
0.6
0
0
5
10
15
20
25
30
- 50
- 25
0
25
50
75
100
125
150
Qg - Total Gate Charge (nC)
TJ - Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 63233
S13-2149-Rev. B, 14-Oct-13
For technical questions, contact: [email protected]
www.vishay.com
3
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5442DU
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
0.025
100
ID = 8 A
RDS(on) - On-Resistance (Ω)
IS - Source Current (A)
0.020
TJ = 150 °C
10
TJ = 25 °C
1
0.1
0.0
0.2
0.4
0.6
0.8
0.015
TJ = 125 °C
0.010
TJ = 25 °C
0.005
0.000
0.0
1.0
1.0
VSD - Source-to-Drain Voltage (V)
2.0
3.0
4.0
5.0
VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
0.8
50
0.7
40
Power (W)
VGS(th) (V)
0.6
0.5
0.4
ID = 250 μA
30
20
0.3
10
0.2
0.1
- 50
- 25
0
25
50
75
100
125
0
0.001
150
0.01
0.1
1
10
100
1000
Time (s)
TJ - Temperature (°C)
Threshold Voltage
Single Pulse Power, Junction-to-Ambient
100
Limited by RDS(on)*
100 μs
ID - Drain Current (A)
10
1 ms
10 ms
1
100 ms
1s
10 s
DC
TA = 25 °C
0.1
BVDSS Limited
0.01
0.1
1
10
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
100
Safe Operating Area, Junction-to-Ambient
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For technical questions, contact: [email protected]
Document Number: 63233
S13-2149-Rev. B, 14-Oct-13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5442DU
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
50
35
30
Power Dissipation (W)
ID - Drain Current (A)
40
30
Package Limited
20
25
20
15
10
10
5
0
0
0
25
50
75
100
TC - Case Temperature (°C)
Current Derating*
125
150
25
50
75
100
125
150
TC - Case Temperature (°C)
Power Derating
* The power dissipation PD is based on TJ(max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 63233
S13-2149-Rev. B, 14-Oct-13
For technical questions, contact: [email protected]
www.vishay.com
5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5442DU
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
Notes:
0.1
0.1
PDM
0.05
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = RthJA = 90 °C/W
3. TJM - TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10-4
10-3
10-2
10-1
1
Square Wave Pulse Duration (s)
10
100
1000
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.1
10-4
Single Pulse
10-3
10-2
Square Wave Pulse Duration (s)
10-1
1
Normalized Thermal Transient Impedance, Junction-to-Case
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?63233.
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For technical questions, contact: [email protected]
Document Number: 63233
S13-2149-Rev. B, 14-Oct-13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
PowerPAK® ChipFET® Case Outline
D
(7)
(6)
(5)
(1)
(2)
(3)
(4)
E
(8)
Pin #1
indicator
Side view of single
e
b
H
D1
D(2)
D2
K
D(3)
L
G(4)
K1
D2
SI(1)
GI(2)
S2(3)
D1(8)
D1(7)
D2(6)
Detail Z
G2(4)
K2
L
D(1)
A1
C
A
Z
Side view of dual
E1
E2
E3
H
D3
D(8)
D(7)
D(6)
S(5)
K3
Backside view of dual pad
Backside view of single pad
DIM.
D2(5)
MILLIMETERS
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
0.70
0.75
0.85
0.028
0.030
0.033
A1
0
-
0.05
0
-
0.002
b
0.25
0.30
0.35
0.010
0.012
0.014
C
0.15
0.20
0.25
0.006
0.008
0.010
D
2.92
3.00
3.08
0.115
0.118
0.121
D1
1.75
1.87
2.00
0.069
0.074
0.079
D2
1.07
1.20
1.32
0.042
0.047
0.052
D3
0.20
0.25
0.30
0.008
0.010
0.012
E
1.82
1.90
1.98
0.072
0.075
0.078
E1
1.38
1.50
1.63
0.054
0.059
0.064
E2
0.92
1.05
1.17
0.036
0.041
0.046
E3
0.45
0.50
0.55
0.018
0.020
0.022
e
0.65 BSC
0.026 BSC
H
0.15
0.20
0.25
0.006
0.008
0.010
K
0.25
-
-
0.010
-
-
K1
0.30
-
-
0.012
-
-
K2
0.20
-
-
0.008
-
-
K3
0.20
-
-
0.008
-
-
L
0.30
0.35
0.40
0.012
0.014
0.016
C14-0630-Rev. E, 21-Jul-14
DWG: 5940
Note
• Millimeters will govern
Document Number: 73203
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Revision: 21-Jul-14
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR PowerPAK® ChipFET® Single
0.225
(0.009)
0.350
(0.014)
0.650
(0.026)
0.200
(0.008)
0.300
(0.012)
0.300
(0.012)
0.100
(0.004)
1.500
(0.059)
1.900
(0.075)
0.250
(0.010)
0.500
(0.020)
0.350
(0.014)
0.350
(0.014)
1.870
(0.074)
0.305
(0.012)
2.575
(0.101)
Recommended Minimum Pads
Dimensions in mm/(Inches)
Return to Index
APPLICATION NOTE
Document Number: 69948
Revision: 21-Jan-08
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9
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Disclaimer
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product with the properties described in the product specification is suitable for use in a particular application. Parameters
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Material Category Policy
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
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Revision: 02-Oct-12
1
Document Number: 91000