ESD218-B1-02EL Data Sheet (789 KB, EN)

Protection Device
TVS (Transient Voltage Suppressor)
ESD218-B1 Series
Bi-directional, 24 V, 3 pF, 0201, 0402, RoHS and Halogen Free compliant
ESD218-B1-02ELS
ESD218-B1-02EL
Data Sheet
Revision 1.1, 2015-01-13
Final
Power Management & Multimarket
Edition 2015-01-13
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2015 Infineon Technologies AG
All Rights Reserved.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ESD218-B1 Series
Product Overview
1
Product Overview
1.1
Features
•
•
•
•
•
•
ESD / transient protection according to:
– IEC61000-4-2 (ESD): ±20 kV (air), ±18 kV (contact)
– IEC61000-4-4 (EFT): ±2 kV / 40 A (5/50 ns)
– IEC61000-4-5 (Surge): ±1.5 A (8/20 μs)
Bi-directional, working voltage up to VRWM = ±24 V
Low capacitance: CL = 3 pF (typical)
Low clamping voltage: VCL = 51 V (typical) at ITLP = 16 A
Very low reverse current. IR = < 1nA (typical)
Pb-free (RoHS compliant) and halogen free package
1.2
•
•
•
•
Application Examples
ESD protection of USB-battery charger interface
LCD Backlight protection
NFC antenna protection
Protection of high speed bus rated up to ±24 V
1.3
Product Description
Pin 1 marking
(lasered)
Pin 1
Pin 1
Pin 2
Pin 2
PinConf_and_SchematicDiag.vsd
Figure 1-1 Pin Configuration and Schematic Diagram
Table 1-1
Part Information
Type
Package
Configuration
Marking code
ESD218-B1-02ELS
TSSLP-2-4
1 line, bi-directional
4
ESD218-B1-02EL
TSLP-2-20
1 line, bi-directional
AA
Final Data Sheet
3
Revision 1.1, 2015-01-13
ESD218-B1 Series
Maximum Ratings
2
Maximum Ratings
Table 2-1
Maximum Ratings at TA = 25 °C, unless otherwise specified 1)
Parameter
Symbol
2)
Values
Unit
ESD air discharge
ESD contact discharge2)
VESD
±20
±18
kV
Peak pulse power3)
PPK
67
W
Peak pulse current3)
IPP
±1.5
A
Operating temperature range
TOP
-55 to 150
°C
Storage temperature
Tstg
-65 to 150
°C
1) Device is electrically symmetrical
2) VESD according to IEC61000-4-2
3) Non-repetitive current pulse 8/20µs exponential decay waveform according to IEC61000-4-5
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
3
Electrical Characteristics
$% & %'
&
%( &
&(
!" !! # Figure 3-1 Definitions of electrical characteristics
Final Data Sheet
4
Revision 1.1, 2015-01-13
ESD218-B1 Series
Electrical Characteristics
Table 3-1
DC Characteristics at TA = 25 °C, unless otherwise specified 1)
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Reverse working voltage VRWM
-24
–
24
V
Breakdown voltage
VBR
24.3
25.5
30
V
IT = 1 mA
Reverse leakage current
IR
–
<1
50
nA
VR = 24 V
Unit
Note / Test Condition
1) Device is electrically symmetrical
Table 3-2
AC Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Values
Min.
Typ.
Max.
Line capacitance
CL
–
–
3
3
3.5
3.5
pF
VR = 0 V, f = 1 MHz
VR = 0 V, f = 1 GHz
Series inductance
LS
–
–
0.2
0.4
–
–
nH
ESD218-B1-02ELS
ESD218-B1-02EL
Table 3-3
ESD and Surge Characteristics at TA = 25 °C, unless otherwise specified 1)
Parameter
Symbol
2)
Clamping voltage
VCL
3)
Clamping voltage
Dynamic resistance
2)
RDYN
Values
Unit
Note / Test Condition
V
ITLP = 16 A, tp = 100 ns
Min.
Typ.
Max.
–
51
55.5
–
66
70.5
ITLP = 30 A, tp = 100 ns
–
37
41.5
IPP = 1 A, tp = 8/20 µs
40
44.5
IPP = 1.5 A, tp = 8/20 µs
0.9
–
–
Ω
tp = 100 ns
1) Device is electrically symmetrical
2) Please refer to Application Note AN210[1]. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 300ps.
3) Non-repetitive current pulse 8/20µs exponential decay waveform according to IEC61000-4-5
Final Data Sheet
5
Revision 1.1, 2015-01-13
ESD218-B1 Series
Typical Characteristics Diagrams
4
Typical Characteristics Diagrams
Typical characteristics diagrams at TA = 25°C, unless otherwise specified
-7
10
-8
10
-9
IR [A]
10
-10
10
-11
10
10-12
-13
10
-24 -20 -16 -12
-8
-4
0
4
VR [V]
8
12
16
20
24
Figure 4-1 Reverse leakage current: IR = f(VR)
3.5
3
CL [pF]
2.5
1 MHz
2
1.5
1 GHz
1
0.5
0
-20
-15
-10
-5
0
VR [V]
5
10
15
20
Figure 4-2 Line capacitance: CL = f(VR)
Final Data Sheet
6
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ESD218-B1 Series
Typical Characteristics Diagrams
100
Scope: 6 GHz, 20 GS/s
80
VCL [V]
60
VCL-max-peak = 94 V
40
VCL-30ns-peak = 48 V
20
0
-20
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-3 Clamping voltage (ESD): VCL = f(t), 8 kV positive pulse from pin 1 to pin 2
20
Scope: 6 GHz, 20 GS/s
0
VCL [V]
-20
-40
VCL-max-peak = -94 V
-60
VCL-30ns-peak = -47 V
-80
-100
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-4 Clamping voltage (ESD) VCL = f(t), 8 kV negative pulse from pin 1 to pin 2
Final Data Sheet
7
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ESD218-B1 Series
Typical Characteristics Diagrams
180
Scope: 6 GHz, 20 GS/s
160
140
VCL [V]
120
VCL-max-peak = 170 V
100
80
VCL-30ns-peak = 60 V
60
40
20
0
-20
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-5 Clamping voltage (ESD) VCL = f(t), 15 kV positive pulse from pin 1 to pin 2
20
Scope: 6 GHz, 20 GS/s
0
-20
VCL [V]
-40
-60
-80
-100
VCL-max-peak = -158 V
-120
VCL-30ns-peak = -55 V
-140
-160
-180
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-6 Clamping voltage (ESD) VCL = f(t), 15 kV negative pulse from pin 1 to pin 2
Final Data Sheet
8
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ESD218-B1 Series
Typical Characteristics Diagrams
30
15
ESD218-B1-02series
RDYN
25
12.5
20
10
15
7.5
10
5
5
2.5
0
0
-5
-2.5
-10
-5
-15
-7.5
Equivalent VIEC [kV]
ITLP [A]
RDYN = 0.9 Ω
RDYN = 0.9 Ω
-20
-10
-25
-12.5
-30
-15
-70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70
VTLP [V]
Figure 4-7 Clamping voltage (TLP): ITLP = f(VTLP)[1], pin 2 to pin 1
Final Data Sheet
9
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ESD218-B1 Series
Typical Characteristics Diagrams
2.5
2
1.5
1
IPP [A]
0.5
0
-0.5
-1
-1.5
-2
-2.5
-45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45
VCL [V]
Figure 4-8 Clamping voltage(Surge): IPP = f(VCL)[1]
Final Data Sheet
10
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ESD218-B1 Series
Package Information
5
Package Information
5.1
TSSLP-2-4
Top view
Bottom view
0.31 +0.01
-0.02
0.32 ±0.05
0.355
0.62 ±0.05
2
Pin 1
marking
0.05 MAX.
0.26 ±0.035
0.2 ±0.035 1)
1
1)
1) Dimension applies to plated terminals
TSSLP-2-3, -4-PO V01
Figure 5-1 TSSLP-2-4 Package outline
0.19
0.24
Solder mask
0.19
0.57
0.14
0.62
Copper
0.19
0.27
0.24
0.32
Stencil apertures
TSSLP-2-3, -4-FP V02
Figure 5-2 TSSLP-2-4 Footprint
0.35
4
8
Ey
Tape type
Ex Ey
Punched Tape
0.43 0.73
Embossed Tape 0.37 0.67
Deliveries can be both tape types (no selection possible).
Specification allows identical processing (pick & place) by users.
Pin 1
marking
Ex
TSSLP-2-3, -4-TP V03
Figure 5-3 TSSLP-2-4 Packing
1
Type code
Pin 1 marking
TSSLP-2-3, -4-MK V01
Figure 5-4 TSSLP-2-4 Marking example, Type code see: Table 1-1 “Part Information” on Page 3
Final Data Sheet
11
Revision 1.1, 2015-01-13
ESD218-B1 Series
Package Information
5.2
TSLP-2-20
Top view
Bottom view
0.31 +0.01
-0.02
0.6 ±0.05
1±0.05
2
1
0.25 ±0.035 1)
0.65 ±0.05
0.05 MAX.
0.5 ±0.035 1)
Pin 1
marking
1) Dimension applies to plated terminals
TSLP-2-19, -20-PO V01
Figure 5-5 TSLP-2-20 Package outline
0.28
0.35
Solder mask
0.38
0.93
0.3
1
Copper
0.28
0.45
0.35
0.6
Stencil apertures
TSLP-2-19, -20-FP V01
Figure 5-6 TSLP-2-20 Footprint
0.4
1.16
Pin 1
marking
8
4
0.76
TSLP-2-19, -20-TP V02
Figure 5-7 TSLP-2-20 Packing
Type code
12
Pin 1 marking
TSLP-2-19, -20-MK V01
Figure 5-8 TSLP-2-20 Marking example, Type code see: Table 1-1 “Part Information” on Page 3
Final Data Sheet
12
Revision 1.1, 2015-01-13
ESD218-B1 Series
References
References
[1]
Infineon AG - Application Note AN210: Effective ESD Protection design at System Level Using VF-TLP
Characterization Methodology
[2]
Infineon AG - Recommendations for PCB Assembly of Infineon TSLP and TSSLP Packages
Final Data Sheet
13
Revision 1.1, 2015-01-13
ESD218-B1 Series
Revision History: Rev. 1.0, 2014-04-08
Page or Item
Subjects (major changes since previous revision)
Revision 1.1, 2015-01-13
11
Correction of Footprint drawing
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Last Trademarks Update 2010-10-26
Final Data Sheet
14
Revision 1.1, 2015-01-13
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