ESD101-B1-02EL Data Sheet (657 KB, EN)

Protection Device
TVS (Transient Voltage Suppressor)
ESD101-B1-02 Series
Bi-directional, 5.5 V, 0.1 pF, 0201, 0402, RoHS and Halogen Free compliant
ESD101-B1-02ELS
ESD101-B1-02EL
Data Sheet
Revision 1.3, 2015-07-13
Final
Power Management & Multimarket
Edition 2015-07-13
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2015 Infineon Technologies AG
All Rights Reserved.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ESD101-B1-02 Series
Product Overview
1
Product Overview
1.1
Features
•
•
•
•
•
•
•
ESD / transient protection of high speed data lines according to:
– IEC61000-4-2 (ESD): ±14 kV (air), ±12 kV(contact)
– IEC61000-4-4 (EFT): ±1.5 kV / ±30 A (5/50 ns)
– IEC61000-4-5 (surge): ±2 A (8/20 μs)
Bi-directional working voltage up to: VRWM = ±5.5 V
Extremely low capacitance CL = 0.1 pF (typical) at f = 1 GHz
Very low clamping voltage: VCL = 30 V (typical) at ITLP = 16 A
Very low reverse current: IR < 0.1 nA
Very low dynamic resistance: RDYN = 1.5 Ω (typical)
Pb-free package (RoHS compliant)
1.2
•
Application Examples [3]
Tailored for ESD Protection of capacitance-susceptible application like
– Super high speed interface
– RF antenna
1.3
Product Description
Pin 1 marking
(lasered)
Pin 1
Pin 1
Pin 2
Pin 2
PinConf_and_SchematicDiag.vsd
Figure 1
Pin configuration and Schematic diagram
Table 1
Part Information
Type
Package
Configuration
Marking code
ESD101-B1-02ELS
TSSLP-2-4
1 line, bi-directional
R
ESD101-B1-02EL
TSLP-2-20
1 line, bi-directional
R
Final Data Sheet
3
Revision 1.3, 2015-07-13
ESD101-B1-02 Series
Maximum Ratings
2
Maximum Ratings
Table 2
Maximum Rating at TA = 25 °C, unless otherwise specified1)
Parameter
Symbol
2)
Values
Unit
ESD air discharge
ESD contact discharge2)
VESD
±14
±12
kV
Peak pulse power
PPK
30
W
Peak pulse current3)
IPP
±2
A
Operating temperature
TOP
-55 to 125
°C
Storage temperature
Tstg
-65 to 150
°C
1) Device is electrically symmetrical
2) VESD according to IEC61000-4-2
3) Non-repetitive current pulse 8/20 µs exponential decay waveform according to IEC61000-4-5
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
3
Electrical Characteristics at TA = 25 °C, unless otherwise specified
Figure 2
( )!! %! )*
!
+! )#! % ##%# !"!!""!" #$%"&!'!! Definitions of electrical characteristics
Final Data Sheet
4
Revision 1.3, 2015-07-13
ESD101-B1-02 Series
Electrical Characteristics at TA = 25 °C, unless otherwise specified
Table 3
DC Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Reverse working voltage VRWM
Values
1)
Unit
Min.
Typ.
Max.
-5.5
–
5.5
Trigger voltage
Vt1
6.1
–
–
Holding voltage
Vh
6.1
7.0
7.9
Reverse leakage current
IR
–
<0.1
20
Note / Test Condition
V
IT = 10 mA
nA
VR = 5.5 V
Unit
Note / Test Condition
pF
VR = 0 V, f = 1 MHz
1) Device is electrically symmetrical
Table 4
AC Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
CL
Line capacitance
LS
Serie inductance
Table 5
Values
Min.
Typ.
Max.
–
–
0.2
–
0.1
–
–
–
0.2
0.4
–
–
VR = 0V, f = 1 GHz
nH
ESD101-B1-02ELS
ESD101-B1-02EL
ESD and Surge Characteristics at TA = 25 °C, unless otherwise specified 1)
Parameter
Symbol
2)
VCL
Clamping voltage
3)
Clamping voltage
Dynamic resistance
2)
RDYN
Values
Unit
Note / Test Condition
V
ITLP = 8 A, tp = 100 ns
Min.
Typ.
Max.
–
18
–
–
30
–
ITLP = 16 A, tp = 100 ns
–
9
–
IPP = 1 A, tp = 8/20 μs
–
13
–
IPP = 2 A, tp = 8/20 μs
–
1.5
–
Ω
tp = 100 ns
1) Device is electrically symmetrical
2) Please refer to Application Note AN210[1]. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 300ps.
3) Non-repetitive current pulse 8/20µs exponential decay waveform according to IEC61000-4-5
Final Data Sheet
5
Revision 1.3, 2015-07-13
ESD101-B1-02 Series
Typical Characteristics Diagrams
4
Typical Characteristics Diagrams
Typical characteristics diagrams at TA = 25°C, unless otherwise specified
10-3
10-4
-5
10
10-6
-7
IR [A]
10
10-8
-9
10
10-10
-11
10
-12
10
Figure 3
0
1
2
3
VR [V]
4
5
Reverse leakage current: IR = f(VR)
150
125
CL [fF]
100
75
50
25
0
Figure 4
-5
-4
-3
-2
-1
0
VR [V]
1
2
3
4
5
Line capacitance CL = f(VR), f = 1 GHz
Final Data Sheet
6
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ESD101-B1-02 Series
Typical Characteristics Diagrams
350
Scope: 20 GS/s
300
VCL [V]
250
200
VCL-max-peak = 300 [V]
150
VCL-30ns-peak = 25 [V]
100
50
0
-50
-50
Figure 5
0
50
100
150
200
tp [ns]
250
300
350
400
450
Clamping voltage (ESD): VCL = f(t), 8 kV positive pulse from pin 1 to pin 2
50
Scope: 20 GS/s
0
-50
VCL [V]
-100
-150
VCL-max-peak = -304 [V]
-200
VCL-30ns-peak = -19 [V]
-250
-300
-350
-50
Figure 6
0
50
100
150
200
tp [ns]
250
300
350
400
450
Clamping voltage (ESD): VCL = f(t), 8 kV negative pulse from pin 1 to pin 2
Final Data Sheet
7
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ESD101-B1-02 Series
Typical Characteristics Diagrams
10
ESD101-B1-02Eseries
RDYN
15
7.5
RDYN = 1.5 Ω
ITLP [A]
10
5
5
2.5
0
0
-5
-2.5
RDYN = 1.5 Ω
-10
-5
-15
-20
-40
Equivalent VIEC [kV]
20
-7.5
-30
-20
-10
0
10
20
30
-10
40
VTLP [V]
Figure 7
Clamping voltage (TLP): ITLP = f(VTLP) [1], pin 1 to pin 2
Final Data Sheet
8
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ESD101-B1-02 Series
Typical Characteristics Diagrams
2.5
2
1.5
1
IPP [A]
0.5
0
-0.5
-1
-1.5
-2
-2.5
-15
Figure 8
-10
-5
0
VCL [V]
5
10
15
Clamping voltage (Surge): IPP = f(VCL) [1], pin 1 to pin 2
Final Data Sheet
9
Revision 1.3, 2015-07-13
ESD101-B1-02 Series
Typical Characteristics Diagrams
Insertion Loss [dB]
0
-1
-2
-3
-4
-5
0.1
1
10
f [GHz]
Figure 9
Insertion loss vs. frequency in a 50 Ω system (ESD101-B1-02ELS)
Final Data Sheet
10
Revision 1.3, 2015-07-13
ESD101-B1-02 Series
Package Information
5
Package Information
5.1
TSSLP-2-4
Top view
Bottom view
0.31 +0.01
-0.02
0.32 ±0.05
0.355
0.62 ±0.05
2
Pin 1
marking
0.2 ±0.035 1)
1
0.26 ±0.035 1)
0.05 MAX.
1) Dimension applies to plated terminals
TSSLP-2-3, -4-PO V01
TSSLP-2-4 Package outline (dimension in mm)
0.19
0.24
Solder mask
0.19
0.57
0.62
Copper
0.19
0.27
0.14
0.32
0.24
Figure 10
Stencil apertures
TSSLP-2-3, -4-FP V02
Figure 11
TSSLP-2-4 Footprint (dimension in mm)
marking
0.35
Tape type
Ex Ey
Punched Tape
0.43 0.73
Embossed Tape 0.37 0.67
8
Ey
4
Pin 1
marking
Figure 12
Deliveries can be both tape types (no selection possible).
Specification allows identical processing (pick & place) by users.
Ex
TSSLP-2-3, -4-TP V03
TSSLP-2-4 Packing (dimension in mm)
1
Type code
Pin 1 marking
Figure 13
TSSLP-2-4 Marking example Table 1 “Part Information” on Page 3
Final Data Sheet
11
Revision 1.3, 2015-07-13
ESD101-B1-02 Series
Package Information
5.2
TSLP-2-20
Top view
Bottom view
0.31 +0.01
-0.02
0.6 ±0.05
1±0.05
2
1
0.25 ±0.035 1)
0.65 ±0.05
0.05 MAX.
0.5 ±0.035 1)
Pin 1
marking
1) Dimension applies to plated terminals
TSLP-2-19, -20-PO V01
TSLP-2-20 Package outline (dimension in mm)
0.28
0.35
Solder mask
0.38
0.93
1
Copper
0.28
0.45
0.3
0.6
0.35
Figure 14
Stencil apertures
TSLP-2-19, -20-FP V01
Figure 15
TSLP-2-20 Footprint (dimension in mm)
0.4
1.16
Pin 1
marking
8
4
0.76
TSLP-2-19, -20-TP V02
Figure 16
TSLP-2-20 Packing (dimension in mm)
Type code
12
Pin 1 marking
TSLP-2-19, -20-MK V01
Figure 17
TSLP-2-20 Marking example Table 1 “Part Information” on Page 3
Final Data Sheet
12
Revision 1.3, 2015-07-13
ESD101-B1-02 Series
References
References
[1]
Infineon Technologies AG, “Effective ESD Protection Design at System Level Using VF-TLP
Characterization Methodology”, Application Note AN210, RF and Protection Devices, April 22, 2010,
Rev.1.0
[2]
Infineon AG - Recommendations for PCB Assembly of Infineon TSLP and TSSLP Packages
[3]
Infineon AC - Application Note AN327: ESD101-B1 / ESD103-B1, Bi-directional Ultra Low Capacitance
Transient Voltage Suppression Diodes for High Power RF Applications.
Final Data Sheet
12
Revision 1.3, 2015-07-13
ESD101-B1-02 Series
Revision History: Rev. .1.2, 2013-07-23
Page or Item
Subjects (major changes since previous revision)
Revision 1.3, 2015-07-13
All
Layout changes
5
Table 3-1) updated
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Last Trademarks Update 2010-06-09
Final Data Sheet
13
Revision 1.3, 2015-07-13
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