ESD114-U1-02EL Data Sheet (970 KB, EN)

Protection Device
TVS (Transient Voltage Suppressor)
ESD114-U1-02 Series
Uni-directional, 5.3 V, 0.4 pF, 0402, 0201, RoHS and Halogen Free compliant
ESD114-U1-02ELS
ESD114-U1-02EL
Data Sheet
Revision 1.0, 2014-10-30
Final
Power Management & Multimarket
Edition 2014-10-30
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ESD114-U1-02 Series
Product Overview
1
Product Overview
1.1
Features
•
•
•
•
•
•
•
ESD / Transient protection of high speed data lines exceeding
– IEC61000-4-2 (ESD): ±20 kV (contact)
– IEC61000-4-4 (EFT): ±2 kV / ±40 A (5/50 ns)
– IEC61000-4-5 (surge): ±3 A (8/20 μs)
Maximum working voltage: VRWM = ±5.3 V
Ultra low capacitance: CL = 0.4 pF (typical)
Very low clamping voltage VCL = +20 / -15 V (typical) at ITLP = 16 A
Low dynamic resistance RDYN = 0.5 Ω (typical)
Very small form factor down to 0.62 x 0.32 x 0.31 mm3
Pb-free (RoHS compliant) and halogen free package
1.2
•
•
Application Examples
USB 2.0, Mobile HDMI Link, MDDI, MIPI, etc.
HDMI, DisplayPort, DVI, Ethernet, Firewire, S-ATA
1.3
Product Description
Pin 1
Pin 1
Pin 1 marking
(lasered)
Pin 2
Pin 2
a) Pin configuration
b) Schematic diagram
Single _Die_diode_PinConf_and_SchematicDiag.vst .vsd
Figure 1
Pin Configuration and Schematic Diagram
Table 1
Ordering Information
Type
Package
Configuration
Marking code
ESD114-U1-02ELS
TSSLP-2-3
1 line, uni-directional
K
ESD114-U1-02EL
TSLP-2-19
1 line, uni-directional
K
FinalData Sheet
4
Revision 1.0, 2014-10-30
ESD114-U1-02 Series
Maximum Ratings
2
Maximum Ratings
Table 2
Maximum Ratings at TA = 25 °C, unless otherwise specified
Parameter
Symbol
1)
Values
Unit
VESD
±20
kV
IPP
±3
A
Operating temperature range
TOP
-55 to 125
°C
Storage temperature
1) VESD according to IEC61000-4-2
Tstg
-65 to 150
°C
ESD contact discharge
Peak pulse current (tp = 8/20 μs)
2)
2) Non-repetitive current pulse 8/20µs exponential decay waveform according to IEC61000-4-5
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
3
Electrical Characteristics at TA = 25 °C, unless otherwise specified
Figure 2
%& ' &(
'
&) '
')
!" !!# $ Definitions of Electrical Characteristics
FinalData Sheet
5
Revision 1.0, 2014-10-30
ESD114-U1-02 Series
Electrical Characteristics at TA = 25 °C, unless otherwise specified
Table 3
DC Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Reverse working voltage VRWM
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
–
–
5.3
V
Pin 1 to Pin 2
Breakdown voltage
VBR
6
–
–
V
IBR = 1 mA, from Pin 1
to Pin 2
Reverse current
IR
–
<10
100
nA
VR = 5.3 V, from Pin 1
to Pin 2
Table 4
RF Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
Line capacitance1)
CL
–
0.4
0.6
pF
VR = 0 V, f = 1 MHz
Serie inductance
LS
–
0.2
–
nH
ESD114-U1-02ELS
–
0.4
–
nH
ESD114-U1-02EL
Unit
Note /
Test Condition
V
ITLP = 1 A,
from Pin 1 to Pin 2
1) Total capacitance line to ground
Table 5
ESD Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
VCL
Clamping voltage
Values
Min.
Typ.
Max.
–
10
–
–
20
–
ITLP = 16 A,
from Pin 1 to Pin 2
–
28
–
ITLP = 30 A,
from Pin 1 to Pin 2
–
3
–
ITLP = 1 A,
from Pin 2 to Pin 1
–
15
–
ITLP = 16 A,
from Pin 2 to Pin 1
–
21
ITLP = 30 A,
–
from Pin 2 to Pin 1
Dynamic resistance
1)
RDYN
–
0.56
–
0.43
–
V
Pin 1 to Pin 2
–
V
Pin 2 to Pin 1
1) Please refer to Application Note AN210[1]. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 300ps, averaging window: t1 = 30 ns
to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP charactertistics between IPP1 = 10 A and
IPP2 = 40 A.
FinalData Sheet
6
Revision 1.0, 2014-10-30
ESD114-U1-02 Series
Typical Characteristics Diagrams
4
Typical Characteristics Diagrams
Typical characteristics diagrams at TA = 25°C, unless otherwise specified
10-2
-3
10
10-4
10-5
10-6
IR [A]
10-7
-8
10
-9
10
10-10
10-11
-12
10
10-13
Figure 3
0
1
2
3
VR [V]
4
5
6
Reverse leakage current:IR = f(VR)
1
0.9
0.8
CL [pF]
0.7
0.6
0.5
0.4
1 MHz
0.3
1 GHz
0.2
Figure 4
0
0.5
1
1.5
2
2.5
3
3.5
VR [V]
4
4.5
5
5.5
6
Line capacitance: CL = f(VR)
FinalData Sheet
7
Revision 1.0, 2014-10-30
ESD114-U1-02 Series
Typical Characteristics Diagrams
120
Scope: 6 GHz, 20 GS/s
100
VCL [V]
80
VCL-max-peak = 112 V
60
VCL-30ns-peak = 17 V
40
20
0
-20
-50
Figure 5
0
50
100
150
200
tp [ns]
250
300
350
400
450
IEC61000-4-2 : VCL = f(t), 8 kV positive pulse from pin 1 to pin 2
20
Scope: 6 GHz, 20 GS/s
0
VCL [V]
-20
-40
-60
VCL-max-peak = -99 V
-80
VCL-30ns-peak = -13 V
-100
-120
-50
Figure 6
0
50
100
150
200
tp [ns]
250
300
350
400
450
IEC61000-4-2 : VCL = f(t), 8 kV negative pulse from pin 1 to pin 2
FinalData Sheet
8
Revision 1.0, 2014-10-30
ESD114-U1-02 Series
Typical Characteristics Diagrams
180
Scope: 6 GHz, 20 GS/s
160
140
VCL [V]
120
VCL-max-peak = 154 V
100
80
VCL-30ns-peak = 25 V
60
40
20
0
-20
-50
Figure 7
0
50
100
150
200
tp [ns]
250
300
350
400
450
IEC61000-4-2 : VCL = f(t), 15 kV positive pulse from pin 1 to pin 2
20
Scope: 6 GHz, 20 GS/s
0
-20
VCL [V]
-40
-60
-80
-100
VCL-max-peak = -139 V
-120
VCL-30ns-peak = -19 V
-140
-160
-180
-50
Figure 8
0
50
100
150
200
tp [ns]
250
300
350
400
450
IEC61000-4-2 : VCL = f(t), 15 kV negative pulse from pin 1 to pin 2
FinalData Sheet
9
Revision 1.0, 2014-10-30
ESD114-U1-02 Series
Typical Characteristics Diagrams
ESD114-U1-02EL
RDYN
20
RDYN = 0.56 Ω
30
15
20
10
10
5
0
0
-10
-5
-20
-10
-30
-15
Equivalent VIEC [kV]
ITLP [A]
40
RDYN = 0.43 Ω
-40
-35 -30 -25 -20 -15 -10 -5 0 5
VTLP [V]
Figure 9
-20
10 15 20 25 30 35
Clamping voltage (TLP): ITLP = f(VTLP) [1], pin 1 to pin 2
FinalData Sheet
10
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ESD114-U1-02 Series
Package Information
5
Package Information
5.1
TSSLP-2-3 (mm)[3]
Top view
Bottom view
0.31 +0.01
-0.02
0.32 ±0.05
0.355
0.62 ±0.05
2
Pin 1
marking
0.05 MAX.
0.26 ±0.035
0.2 ±0.035 1)
1
1)
1) Dimension applies to plated terminals
TSSLP-2-3, -4-PO V01
TSSLP-2-3: Package overview
0.19
0.24
Solder mask
0.19
0.57
0.62
Copper
0.19
0.27
0.14
0.32
0.24
Figure 10
Stencil apertures
TSSLP-2-3, -4-FP V02
Figure 11
TSSLP-2-3 Footprint
0.35
Tape type
Ex Ey
Punched Tape
0.43 0.73
Embossed Tape 0.37 0.67
8
Ey
4
Deliveries can be both tape types (no selection possible).
Specification allows identical processing (pick & place) by users.
Pin 1
marking
Figure 12
Ex
TSSLP-2-3, -4-TP V03
TSSLP-2-3: Packing
1
Type code
Pin 1 marking
TSSLP-2-3, -4-MK V01
Figure 13
TSSLP-2-3: Marking (example)
FinalData Sheet
11
Revision 1.0, 2014-10-30
ESD114-U1-02 Series
Package Information
5.2
TSLP-2-19 (mm)[3]
Top view
Bottom view
0.31 +0.01
-0.02
0.6 ±0.05
0.05 MAX.
1±0.05
0.65 ±0.05
2
0.25 ±0.035 1)
1
0.5 ±0.035 1)
Pin 1
marking
1) Dimension applies to plated terminals
TSLP-2-19, -20-PO V01
TSLP-2-19: Package Overview
0.28
0.35
Solder mask
0.38
0.93
1
Copper
0.28
0.45
0.3
0.6
0.35
Figure 14
Stencil apertures
TSLP-2-19, -20-FP V01
TSLP-2-19: Footprint
0.93
0.3
0.35
0.28
1
Copper
0.28
0.45
0.35
0.6
Solder mask
0.38
Figure 15
Stencil apertures
TSLP-2-19, -20-FP V01
Figure 16
TSLP-2-19: Packing
Type code
12
Pin 1 marking
TSLP-2-19, -20-MK V01
Figure 17
TSLP-2-19: Marking (example)
FinalData Sheet
12
Revision 1.0, 2014-10-30
ESD114-U1-02 Series
References
References
[1]
Infineon AG - Application Note AN210: Effective ESD Protection Design at System Level Using VF-TLP
[2]
Infineon AG - Application Note AN140: ESD Protection for Digital High-Speed Interfaces (HDMI, FireWire,
...) using ESD5V3U1U)
[3]
Infineon AG - Recommendations for PCB Assembly of Infineon TSLP and TSSLP Package
FinalData Sheet
15
Revision 1.0, 2014-10-30
ESD114-U1-02 Series
Revision History: Rev.09, 2014-06-20
Page or Item
Subjects (major changes since previous revision)
Revision 1.0, 2014-10-30
All
Status change to Final
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FinalData Sheet
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