Application Note 1082 Application Notes for AP3772 System Solution Prepared by Zhao Jing Jing System Engineering Dept. 1. Introduction The AP3772 uses Pulse Frequency Modulation (PFM) method to realize Discontinuous Conduction Mode (DCM) operation for Flyback power supplies. The operating principle of PFM is different with Pulse Width Modulation (PWM), so the design of transformer is also different. number of external system components. Fixed cable compensation is used in different IC versions to adapt the different voltage drop on output cable and good CV regulation is achieved. Besides, audio noise is reduced by the creative audio suppression technique. The AP3772 can provide accurate constant voltage (CV), constant current (CC) regulation with Primary Side Regulation (PSR) structure. It uses internal line compensation and cable compensation to reduce the 1 The AP3772 is designed for driving bipolar transistor in Flyback converter, with more driving current of about 40mA. With system parameters properly designed, AP3772 can achieve standby power less than 150mW. FR1 L1 T1 BG1 RST1 VINAC C1 R2 Np RST2 DS Ns R1 + D1 CIN1 + CIN2 COUT1 + Da Ra + COUT2 RDUMMY CN1 5V/1.2A Na + CVCC L2 Q1 U1 AP3772 VCC CCPC GND RFB1 OUT CPC FB CS RFB2 RLINE RCS Figure 1. Typical Application Circuit of AP3772 Figure 1 is the typical application circuit of AP3772, which is a conventional Flyback converter with a 3-winding transformer---primary winding (NP), secondary winding (NS) and auxiliary winding (NA). The auxiliary winding is used for providing VCC supply voltage for IC and sensing the output voltage feedback signal to FB pin. the parameters are defined as following. Vdri---The driving signal of primary power switch Ip---The primary side current Is ---The secondary side current IPK---Peak value of primary side current IPKS---Peak value of secondary side current VSEC---The transient voltage at secondary winding VS---The stable voltage at secondary winding when 1 Figure 2 shows the typical waveforms which demonstrate the basic operating principle of AP3772 application. And Apr. 2012 Rev. 1. 0 BCD Semiconductor Manufacturing Limited 1 Application Note 1082 tONP ---The conduction time when primary side switch is “ON” tONS ---The conduction time when secondary side diode is “ON” tOFF ---The dead time when neither primary side switch nor secondary side diode is “ON” tOFFS --- The time when secondary side diode is “OFF” rectification diode is in conducting status, which equals the sum of output voltage VOUT and the forward voltage drop of diode VAUX---The transient voltage at auxiliary winding VA--- The stable voltage at auxiliary winding when rectification diode is in conducting status, which equals the sum of voltage VCC and the forward voltage drop of auxiliary diode tSW ---The period of switching frequency t SW Vdri IPK IP IPKS t OFFS IS VA VAUX VS VSEC t ONP tONS t OFF Figure 2. Operation Waveforms of Flyback PSR Control System (1) 2. Guideline of System Design t START = (R ST1 + R ST 2 ) ⋅ C vcc ⋅ VTH _ ST / VINDC _ MIN 1. 2. 3. 4. 5. 6. Where VTH_ST is the Startup Threshold of VCC, and VINDC_MIN is the rectified DC voltage from the lowest AC input. Low Standby Power Design Switching Frequency Design Transformer and Power Devices Design Feedback Resistors Design Line Compensation Design Cable Compensation Design Besides, the selection of dummy load resistor is a tradeoff between standby power and I-V curve. The recommended value of dummy load resistor RDUMMY is 4.7kΩ to 10kΩ for an application with 5V output voltage. 2.1 Low Standby Power Design In order to achieve low standby power, AP3772 decreases the minimum operating voltage. And the startup resistors RST1+RST2 should be high enough to further lower the power loss. However, there is a tradeoff between low standby power PST and small startup time tSTART, which is Apr. 2012 2.2 Switching Frequency Design Rev. 1. 0 BCD Semiconductor Manufacturing Limited 2 Application Note 1082 As we know, in DCM Flyback converter, the stored energy of primary side will be transferred to secondary side at the time when the primary switch is turned off. And assume the current transfer efficiency from primary to secondary is ηi , then 2 ⋅ VDD Vcpc = IO N PS ⋅ ηi ⋅ I PK If ηT is efficiency of power transmission from transformer primary to the output, then (2) Ipks = Ipk ⋅ N PS ⋅ ηi PO = VO ⋅ I O = Here, NPS is the turn ratio of primary winding to secondary winding. t 1 Ipks ⋅ ONS 2 t SW f SW 2 ⋅VO = 2 IO LP ⋅ I pk ⋅ ηT (7) (8) (3) When voltage at the sense resistor reaches the reference voltage set by AP3772, the switch will be turned off and primary current reaches its maximum value, Then, Io = 1 2 ⋅ LP ⋅ I pk ⋅ f SW ⋅ ηT 2 Where, fSW is the switching frequency. So, It is obvious in Figure 2 that the output current “IO” is the average current of secondary side “IS”, Io = (6) t 1 Ipk ⋅ N PS ⋅ η i ⋅ ONS 2 t SW (4) I PK = Always voltage of CPC pin (VCPC) is determined by, t Vcpc = VDD ⋅ ONS t SW Vcs _ ref (9) Rcs When the constant reference VCS_REF is used, the peak current IPK is constant. From formula (6) and (8), it is obvious that VCPC and fSW increases linearly with the output current IO. (5) Here VDD is a constant voltage generated by IC. Then, VH=0.5V VCS_REF 1.4V VCPC fSW fSW 47.6kHz 20kHz IO 42%IO Figure 3. Relationship Between VCPC, fSW and IO at Constant Peak Current Mode Apr. 2012 Rev. 1. 0 BCD Semiconductor Manufacturing Limited 3 Application Note 1082 decreased to 0.5V/1.5 when IO<42%* IO_MAX, as follows in Figure 4. In AP3772, in order to realize audio noise suppression, two-segmented of current reference voltage VCS_REF is used. The reference is about 0.5V when IO>=42%*IO_MAX and is VLOAD VCPC VH=0.5V VCS_REF VL=0.5V/1.5 0.42хIO_MAX IO_MAX fSW 55kHz 52kHz fSW 23.1kHz 8.89kHz 3.95kHz 20kHz 0.42хIO_MAX IO_MAX ISOURCE IO_MAX Figure 4. Relationship Between VCPC, fSW and IO at Variable Peak Current Mode Then from formula (6) and (8), we can see the VCPC and fSW both has a leap at about 42% of maximum load. At the leap point, if the peak current is decreased by 1.5 times, the voltage of CPC pin at low IPK will be increased to 1.5 times, and the switching frequency fSW at low IPK will be increased to 1.52 times. So the load range in audio is largely narrowed. VCS_REF VH=0.5V VL=0.5V/1.5 39%IO 42%IO IO Figure 5. Hysteresis at Conversion Between Low IPK and High IPK In order to avoid unstable operation, a hysteresis is added at the conversion between low IPK and high IPK. Considering the relationship between audio noise and flux density of transformer, deltaB≤2500 gauss is better for audio noise suppression. the AP3772 can be up to 120kHz. But this is only the limit of the IC; the finally designed maximum switching frequency is determined by the tradeoff between the efficiency, mechanical dimensions and thermal performance. The low limitation of maximum switching frequency is given by audio noise suppression. And the upper limit of Apr. 2012 Rev. 1. 0 BCD Semiconductor Manufacturing Limited 4 Application Note 1082 There is an oscillating signal on FB waveform after secondary Schottky diode current decrease to zero, which is caused by primary inductance and equivalent output capacitance of primary switch. Then some margin is added to tONS as 2.3 Transformer and Power Devices Design In the design of AP3772, constant current control function will keep a fixed proportion between on-time tONS and off-time tOFFS of rectifier D1 (in Figure 1) by discharging or charging a capacitor embedded in the IC. The fixed proportion is tONS 1 = t SW 2 tONS = I pks ⋅ Vs ⋅ Io = 1 1 I O = ⋅ I PKS = ⋅ N PS ⋅ ηi ⋅ I PK k k (18) Then, t SW = (12) The turn ratio of transformer should be designed first, which ensures the power converter operating in DCM within the whole conditions, tSW ≥ tONP + tONS 2 2 ⋅VS ⋅ I O 2 ⋅ ηi Lp ⋅ I pk 2 ⋅ VS ⋅ I O (13) Ls = For the primary side current, 2 ≥ I pks ⋅ Lp Ls ⋅ 1.1 + I pk ⋅ Vs Vindc_min (20) Lp N PS (21) 2 At full load, the system will work in the boundary of CC regulation. IO can be given by formula (12)，the following can be obtained, Lp (14) N PS ≤ N PS _ MAX = Where LP is the inductance of primary winding. Vindc is the rectified DC voltage of input. When Vindc is the minimum value, the maximum tONP can be obtained. So, Vindc_min ⋅ ηi VS k ⋅ ( − 1.1) 2 (22) Then designed turns ratio NPS should be no more than NPS_MAX defined in formula (22). 2.3.2 Check Stress Voltage of Primary Side Switch and Reverse Voltage of Secondary Diode Lp Vindc _ min (19) Relationship between inductance of primary side and secondary side is, As we know, if equation (13) is met at minimum input voltage and full load, it can ensure that the power converter operates in DCM in all conditions. Vindc 2 L p ⋅ I pk ⋅ ηi tONP , tONS and tSW in (13) are replaced with (15), (16) and (19), then 2.3.1 Calculate Turn Ratio of Transformer (NPS) (15) If NPS is fixed by customer according to design step 2.3.1, real stress voltage of primary side switch and reverse voltage of secondary diode can be calculated. For the secondary side current, LS is the inductance of secondary winding, Vd is the forward voltage of secondary diode. Apr. 2012 1 1 Lp 1 ⋅ Ls ⋅ Ipks 2 ⋅ fsw = ⋅ ⋅ ( Ipk ⋅ N PS ⋅ ηi ) 2 ⋅ fsw = ⋅ Lp ⋅ Ipk 2 ⋅ fsw ⋅ ηi 2 2 2 N PS 2 2 (11) Then the output constant-current value IO is t ONP_MAX = I pk ⋅ (17) From formula (4) and formula (16), we can get 2 ⋅ t SW =4 tONS t ONP = I pk ⋅ (16) VS = VO + Vd (10) It is assumed k= LS ⋅ 1. 1 VS Rev. 1. 0 BCD Semiconductor Manufacturing Limited 5 Application Note 1082 Where, fSW was set by the user based on definite requirement. Then, LP can be gotten by, The maximum stress voltage of primary side switch is, Vds _ switch = Vdc_spike + Vindc_max + VS ⋅ N P NS (23) LP = Be careful that the value of Vdc_spike is determined by the snubber circuit design. 2 ⋅ PS 1 ⋅ 2 I ⋅ f SW ηi 2 PK (27) 2.3.5 Calculate the Turns of Primary, Secondary and Auxiliary (NP, NS, NA) Maximum reverse voltage of secondary side， The turns of primary winding, Vdr = VS + Vindc_max ⋅ N S NP (24) Np = For Flyback converter design, higher turns ratio NPS brings higher stress voltage of primary side switch, higher transforming efficiency, and the lower reverse voltage of secondary diode. Finally, in design of turns ratio NPS, formula (22), (23) and (24) should be totally considered. NS = NP N PS (29) Turns of auxiliary winding is, NA = IPK can be calculated by the output current. k ⋅ IO N PS ⋅ ηi (28) As NPS and NP are fixed, we can get NS by 2.3.3 Calculate the Peak Current of Primary Side and Current Sensed Resistor (IPK & RCS) I pk = LP ⋅ I PK LP ⋅ I PK ≥ Ae ⋅ ∆B Ae ⋅ B max (25) N S ⋅ VA VS (30) 2.3.6 Check the Maximum Duty Cycle of Primary Side After turn ratio of primary side and secondary side is designed, the maximum duty cycle of primary side at low line voltage can be calculated again. In AP3772, 0.5V is an internal reference voltage. If the sensed voltage VCS_REF reaches 0.5V, the power switch will shut down and tONP will be ended. Considering the Volt-second balance between magnetizing and de-magnetizing, the formula of duty cycle is So RCS can be obtained by formula (9) and selected with a real value from the standard resistor series. We recommended using 1% tolerance resistors for RCS. After RCS is selected, IPK should be modified based on the selected RCS. D max = ( VO + Vd ) ⋅ N PS t ons ⋅ Vindc ⋅ η i t sw (31) 2.3.7 Check Reverse Voltage of Auxiliary Diode 2.3.4 Calculate the Inductance of Primary Side---LP The primary side inductance LP is relative with the stored energy. LP should be big enough to store enough energy, so that PO_MAX can be obtained from this system. If NP and NA is fixed according to design step 2.3.5, real reverse voltage of auxiliary diode can be calculated by formula (32). According to formula (18), the output power can be given by, Vdar = VA + PS = VS ⋅ I O = Apr. 2012 1 2 2 ⋅ L p ⋅ I pk ⋅ f SW ⋅ ηi 2 Vindc_max ⋅ N A NP (32) (26) Rev. 1. 0 BCD Semiconductor Manufacturing Limited 6 Application Note 1082 2.4 Feedback Resistors Design Figure 6. Feedback Resistors Circuit From above Figure 6, Vo = VFB ⋅ (R FB1 + R FB 2 ) N S ⋅ − VD R FB 2 NA R FB1 Vo + VD = ⋅ NA −1 RFB 2 N S ⋅ VFB RFB2 are within 5kΩ to 100kΩ. (33) 2.5 Line Compensation Design The internal line compensation function in AP3772 is shown in Figure 7. S1 is closed when the primary switch is “ON”. The line voltage can be detected from the FB pin. The detected voltage internally compensates the peak current. So the line compensation is determined by RLINE. In different applications, the value of RLINE is different. (34) Through adjusting RFB1 and RFB2, a suitable output voltage can be achieved. The recommended values of RFB1 and Figure 7. Line Compensation Circuit Apr. 2012 Rev. 1. 0 BCD Semiconductor Manufacturing Limited 7 Application Note 1082 Figure 8. Waveform of FB Pin The negative voltage VN of FB pin (in Figure 8) is linear to line voltage. The AP3772 samples VN to realize the line compensation. VN = Vindc ⋅ NA R FB 2 ⋅ N P R FB1 + R FB 2 regulation of output current. R LINE = ( (35) 1 ⋅ 0.8 ⋅ RLINE 670k t delay LP (36) (38) As defined in datasheet below, for example, in AP3772A, there is a total voltage increase of 6% at VFB when the output is at full load (IOUT_MAX). And if the output is at 10%*IOUT_MAX, the increase voltage of VFB is 0.6%. Proper version of IC can be chosen according to the resistance of the output cable. (37) ⋅ Rcs NA R FB 2 0.8 ⋅ ⋅ ) N P R FB1 + R FB 2 670k Three versions of IC are designed to meet different requirement for cable voltage compensation. As we know, an increase voltage at VFB (∆VFB_CABLE) will introduce an increase voltage at VOUT (∆VOUT_ CABLE), which is a linear function of the output load (IOUT). Then in application of AP3772, CPC pin detects the load information and a corresponding delta voltage is added to VFB to compensate the voltage drop at output cable. This is designed to compensate the additional voltage of VCS introduced by tdelay, which is the delay time of internal drivers of IC and primary side switch. Vdelta = Vindc ⋅ Lp ⋅ R cs ) /( 2.6 Cable Compensation Design The compensated voltage of line compensation (VCS_LINE) can be calculated by the following formula, VCS _ LINE = VN ⋅ t delay Then RLINE can be adjusted to achieve excellent line CABLE COMPENSATION SECTION Cable Compensation Voltage ∆VFB _CABLE/VFB % AP3772A AP3772B AP3772C Assume ∆VFB % = (39) VFB 7 4 % % % RFB1 + R FB 2 N S ⋅ ) RFB 2 NA (41) Design Example (for 5V/1.2A application): Then from Figure 6, R + RFB 2 N S ⋅ FB1 ⋅ = I O _ MAX ⋅ RCABLE RFB 2 NA Specification: Input voltage: 85VAC to 265VAC Output voltage @ cable: VO_CABLE=5V Output current: IO=1.2A Output voltage @ PCB: VO=5.13V, (AWG22 Cable, Length of cable=100cm) (40) Then after ∆VFB% is calculated, proper version of AP3772 can be chosen accordingly. Apr. 2012 6 3 0 ∆VFB % = I O _ MAX ⋅ RCABLE /(VFB ⋅ ∆VFB _ CABLE ∆VOUT _ CABLE = ∆VFB % ⋅ VFB 5 2 Rev. 1. 0 BCD Semiconductor Manufacturing Limited 8 Application Note 1082 Other setting by users: Switching frequency: fSW=65kHz Forward voltage of secondary diode: Vd=0.4V Forward voltage of auxiliary diode: Vda=1.1V VCC voltage: VCC=14V Core_type: RM5 (Ae=23.7mm2), Bmax<3000GS Vdc_spike=50V (with snubber circuit) We choose NP=93T NS = NP =6T N PS (50) NA = N S ⋅ VA = 16 T VS (51) Design Steps: 6) Check the maximum duty cycle of primary side 1) Calculate turn ratio of transformer (NPS) N PS ≤ N PS _ MAX = Vindc_min ⋅ η i VS k ⋅ ( − 1.1) = 15.8 2 Vindc_min = Vinac_min ⋅ 2 − 40 (42) The maximum duty cycle of primary side is calculated as following, (43) D= Considering some margin for Flyback PSR control, we choose NPS=15.5. (VO + Vd ) ⋅ N PS ⋅ 0.4 = 0.49 Vindc ⋅ η i 7) Check reverse voltage of auxiliary diode 2) Check stress voltage of primary side switch and reverse voltage of secondary diode Vdar = VA + According to formulas (23) (24) and the selected NPS, proper power devices could be chosen. 8) Vds _ switch = Vdc_spike + Vindc_max Vdr = VS + Vindc_max ⋅ N S NP V ⋅ NP + S = 510V < 700V NS I pks N PS ⋅ η i RCS = = (44) VCS = 1.5 Ω I pk NP (53) = 79V Feedback Resistors (54) RFB1=24.9kΩ, RFB2=9.85kΩ = 29V < 40V (45) k ⋅ IO = 330mA N PS ⋅ η i Vindc_max ⋅ N A RFB1 Vo + VD = ⋅ N A − 1 = 2.56 RFB 2 N S ⋅ VFB 9) Line Compensation Resistors RLINE = ( 3) Calculate the peak current of primary side and current sense resistor (IPK & RCS) I pk = (52) tdelay Lp ⋅ Rcs ) /( NA RFB 2 0.8 ⋅ ⋅ ) = 3.4k Ω (55) N P RFB1 + RFB 2 670k 10) Cable Compensation Choice (46) VFB=4.04V , the same in three versions of AP3772. Then, (47) VFB % = I O _ MAX ⋅ RCABLE /(VFB ⋅ RFB1 + RFB 2 N S ⋅ ) = 2.4% RFB 2 NA (56) 4) Calculate the inductance of primary side---LP LP = According to datasheet information, AP3772B is a better choice. 2 ⋅ VS ⋅ I O = 1.9 mH (48) 2 2 ⋅ f SW ⋅ ηi I PK VO _ FL = VO _ NL + (VFB % ⋅VFB ⋅ 5) Calculate the turns of primary, secondary and auxiliary (NP, NS, NA) Np = LP ⋅ I PK LP ⋅ I PK ≥ = 89.8 T Ae ⋅ ∆B Ae ⋅ B max Apr. 2012 R FB1 + R FB 2 N S ⋅ ) − I O _ MAX ⋅ RCABLE = 5.03V R FB 2 NA (57) Where VO_NL=5V. Therefore, the output voltage at cable terminal at full load is a little higher than the voltage at no load. (49) Rev. 1. 0 BCD Semiconductor Manufacturing Limited 9 Application Note 1082 Design Results Summary: 1.Maximum peak current of primary side and RCS IPK 330 mA RCS 1.5 Ω LP 1.90 mH NPS= 15.5 Peak current of primary side Current sensed resistor 2.Transformer Inductance of primary side Turn ratio of primary and secondary NP 93 T Turns of primary side NS 6 T Turns of secondary side NA 16 T Turns of auxiliary side DMAX 0.49 Maximum duty cycle of primary side at VINDC=80V 3. Primary power switch and diode Vds_switch 510 V Voltage stress of primary power switch Vdr 29 V Maximum reverse voltage of secondary diode Vdar 79 V Maximum reverse voltage of auxiliary diode 4. Voltage feedback resistors RFB1 24.9k Ω Feedback resistor at upside from auxiliary side to FB pin RFB2 9.85k Ω Feedback resistor at downside from FB pin to GND Ω Line compensation resistor 5. Line compensation resistor RLINE 3.4k 6.Cable Compensation IC version AP3772B VO_NL 5 V Output cable voltage @ no load VO_FL 5.03 V Output cable voltage @ full load 3. Summary preliminary design guideline about these aspects and considers ideal conditions, so some parameters need to be adjusted slightly on the basis of the calculated results. In order to get good performance of AP3772, it is important to correctly design standby power, switching frequency, transformer parameters, feedback resistance and line compensation resistance. This application note only gives a Apr. 2012 Rev. 1. 0 BCD Semiconductor Manufacturing Limited 10 Application Note 1082 4. Application of AP3772 with AP4340 FR1 L1 BG1 RST1 VINAC C1 R2 Np RST2 R1 + CIN2 Ns R3 AP4340 OUT VCC D1 CIN1 DS T1 R4 + GND + COUT Da CN1 5V/1.2A Ra Na + CVCC L2 + Q1 U1 AP3772 VCC CCPC RFB1 OUT CPC GND FB CS RFB2 RLINE RCS Figure 9. Typical Application Circuit of AP3772 with AP4340 AP3772 can effectively improve the transient performance for Primary Side Regulation power system. Besides, dummy load is not needed at secondary side and as a result standby power will be decreased. For more detailed operating principles, please refer to Application Note of AP4340 (Application Note 1078_BCD). In Primary Side Regulation of AP3772 application, if AP4340 is used at secondary side as the output voltage regulator, excellent dynamic response and low standby power can be achieved. When detecting the output voltage lower than a certain level, the AP4340 outputs periodical signals which will be coupled to auxiliary side and detected by AP3772. By fast response and cooperation, AP4340 and Apr. 2012 Rev. 1. 0 BCD Semiconductor Manufacturing Limited 11

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