NTMFS4833N D

NTMFS4833N
Power MOSFET
30 V, 191 A, Single N−Channel, SO−8FL
Features
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
These are Pb−Free Devices
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V(BR)DSS
Applications
•
•
•
•
Refer to Application Note AND8195/D
CPU Power Delivery
DC−DC Converters
Low Side Switching
RDS(ON) MAX
ID MAX
2.0 mW @ 10 V
30 V
191 A
3.0 mW @ 4.5 V
D (5)
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
±20
V
ID
28
A
Continuous Drain
Current RqJA
(Note 1)
TA = 25°C
Power Dissipation
RqJA (Note 1)
TA = 25°C
PD
2.7
W
Continuous Drain
Current RqJA
(Note 2)
TA = 25°C
ID
16
A
Power Dissipation
RqJA (Note 2)
TA = 85°C
Steady
State
TA = 85°C
N−CHANNEL MOSFET
D
W
Continuous Drain
Current RqJC
(Note 1)
TC = 25°C
ID
191
A
Power Dissipation
RqJC (Note 1)
TC = 25°C
TC = 85°C
113.6
W
IDM
288
A
TJ, TSTG
−55 to
+150
°C
IS
104
A
Drain to Source dV/dt
dV/dt
6
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 30 V, VGS = 10 V,
IL = 35 Apk, L = 1.0 mH, RG = 25 W)
EAS
612.5
mJ
TL
260
°C
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
(Cu area = 50 mm2 [1 oz])
© Semiconductor Components Industries, LLC, 2014
March, 2014 − Rev. 10
SO−8 FLAT LEAD
CASE 488AA
STYLE 1
D
4833N
AYWZZ
D
D
138
PD
Source Current (Body Diode)
S
S
S
G
1
1.1
Operating Junction and Storage
Temperature
MARKING
DIAGRAM
12
PD
TA = 25°C,
tp = 10 ms
S (1,2,3)
20.5
TA = 25°C
Pulsed Drain
Current
G (4)
1
A
Y
W
ZZ
= Assembly Location
= Year
= Work Week
= Lot Traceability
ORDERING INFORMATION
Device
Package
Shipping†
NTMFS4833NT1G
SO−8FL 1500/Tape & Reel
(Pb−Free)
NTMFS4833NT3G
SO−8FL 5000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NTMFS4833N/D
NTMFS4833N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Junction−to−Case (Drain)
Parameter
RqJC
1.1
Junction−to−Ambient – Steady State (Note 3)
RqJA
45.6
Junction−to−Ambient – t < 10s (Note 3)
RqJA
17.1
Junction−to−Ambient – Steady State (Note 4)
RqJA
117.4
Unit
°C/W
3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
4. Surface−mounted on FR4 board using the minimum recommended pad size. (Cu area = 50 mm2 [1 oz])
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
17
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25 °C
1
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.5
V
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
Forward Transconductance
VGS(TH)/TJ
RDS(on)
1.5
7.12
VGS = 10 V to
11.5 V
ID = 30 A
1.3
ID = 15 A
1.3
VGS = 4.5 V
ID = 30 A
2.3
ID = 15 A
2.3
gFS
VDS = 15 V, ID = 15 A
mV/°C
2.0
3.0
30
mW
S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
650
Total Gate Charge
QG(TOT)
39
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
5600
VGS = 0 V, f = 1 MHz, VDS = 12 V
VGS = 4.5 V, VDS = 15 V; ID = 30 A
1200
6.0
16
pF
58
nC
17
QG(TOT)
VGS = 11.5 V, VDS = 15 V; ID = 30 A
88
nC
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
25
VGS = 4.5 V, VDS = 15 V, ID = 15 A,
RG = 3.0 W
34
35
tf
17
td(ON)
14
tr
td(OFF)
VGS = 11.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
19
50
10
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
ns
ns
NTMFS4833N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Typ
Max
TJ = 25°C
−
0.8
1.0
TJ = 125°C
−
0.68
−
−
38
−
−
19
−
Unit
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
Charge Time
Discharge Time
VSD
VGS = 0 V,
IS = 30 A
tRR
ta
ns
−
19
−
QRR
−
36
−
nC
Source Inductance
LS
−
0.50
−
nH
Drain Inductance
LD
−
0.005
−
nH
Gate Inductance
LG
−
1.84
−
nH
Gate Resistance
RG
−
1.0
−
W
Reverse Recovery Charge
tb
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 30 A
V
PACKAGE PARASITIC VALUES
TA = 25°C
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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3
NTMFS4833N
TYPICAL PERFORMANCE CURVES
TJ = 25°C
150
3.8 V
125
3.6 V
100
3.4 V
75
50
3.2 V
25
3.0 V
2.8 V
0
1
2
4
3
5
100
TJ = 125°C
75
50
TJ = 25°C
25
TJ = −55°C
0
2
1
4
3
5
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
ID = 30 A
TJ = 25°C
0.006
0.004
0.002
1.5
125
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.008
1.75
150
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.010
0
VDS ≥ 10 V
175
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
VGS = 4.0 V
ID, DRAIN CURRENT (AMPS)
175
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
200
4.2 V thru 10 V
2
6
4
8
10
12
0.004
TJ = 25°C
0.003
VGS = 4.5 V
0.002
VGS = 11.5 V
0.001
0
25
50
100
75
125
150
175
200
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100,000
ID = 30 A
VGS = 10 V
VGS = 0 V
IDSS, LEAKAGE (nA)
ID, DRAIN CURRENT (AMPS)
200
1.25
TJ = 150°C
10,000
1.0
0.75
0.5
TJ = 125°C
1,000
0.25
0
−50
100
−25
0
25
50
75
100
125
150
0
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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4
30
NTMFS4833N
TYPICAL PERFORMANCE CURVES
C, CAPACITANCE (pF)
7000
12
TJ = 25°C
Ciss
Ciss
5000
Crss
3000
2000
Coss
1000
0
10
VDS = 0 V
5
VGS
VGS = 0 V
0
VDS
5
10
15
20
25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
t, TIME (ns)
100
td(off)
tr
td(on)
1
8
6
Q1
4
10
RG, GATE RESISTANCE (W)
2
0
ID = 30 A
TJ = 25°C
0
TJ = 25°C
20
15
10
5
100 ms
1 ms
0.01
0.01
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
100 ms
dc
0.1
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
I D, DRAIN CURRENT (AMPS)
0.1
0.2
0
0.4
0.6
0.8
1.0
Figure 10. Diode Forward Voltage vs. Current
10 ms
1
90
80
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
10 ms
VGS = 20 V
SINGLE PULSE
TC = 25°C
50
20
30
60
70
40
QG, TOTAL GATE CHARGE (nC)
VGS = 0 V
0
100
1000
10
10
25
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
100
Q2
30
IS, SOURCE CURRENT (AMPS)
VDD = 15 V
ID = 15 A
VGS = 11.5 V
tf
10
VGS
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
Figure 7. Capacitance Variation
1000
QT
10
6000
4000
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
8000
650
600
550
500
450
400
350
300
250
200
150
100
50
0
ID = 35 A
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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5
NTMFS4833N
TYPICAL PERFORMANCE CURVES
I D, DRAIN CURRENT (AMPS)
1000
100
25°C
100°C
10
125°C
1
10
1
1,000
100
PULSE WIDTH (ms)
10,000
Figure 13. Avalanche Characteristics
100
Duty Cycle = 0.5
R(t) (°C/W)
10
1
0.2
0.1
0.05
0.02
0.01
0.1
0.01
0.000001
Single Pulse
0.00001
0.0001
0.001
0.01
0.1
1
t, time (s)
Figure 14. FET Thermal Response
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6
10
100
1000
NTMFS4833N
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE G
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
0.20 C
D
2
A
B
D1
2X
0.20 C
4X
E1
2
3
q
E
2
1
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
c
A1
4
TOP VIEW
C
3X
e
0.10 C
SEATING
PLANE
DETAIL A
A
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
0.10 C
SIDE VIEW
SOLDERING FOOTPRINT*
DETAIL A
3X
8X
0.10
C A B
0.05
c
4X
e/2
1
4
0.965
K
G
0.750
1.000
L
PIN 5
(EXPOSED PAD)
4X
1.270
b
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.15 BSC
4.50
4.90
5.10
3.50
−−−
4.22
6.15 BSC
5.50
5.80
6.10
3.45
−−−
4.30
1.27 BSC
0.51
0.61
0.71
1.20
1.35
1.50
0.51
0.61
0.71
0.05
0.17
0.20
3.00
3.40
3.80
0_
−−−
12 _
1.330
2X
0.905
2X
E2
L1
M
0.495
4.530
3.200
0.475
D2
2X
BOTTOM VIEW
1.530
4.560
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTMFS4833N/D