AT25080B/160B/320B/640B Automotive - Complete

AT25080B, AT25160B, AT25320B, and AT25640B
SPI Automotive Temperature Serial EEPROMs
8K (1024 x 8), 16K (2048 x 8), 32K (4096 x 8), 64K (8192 x 8)
DATASHEET
Features


Serial Peripheral Interface (SPI) compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
̶

Data sheet describes Mode 0 operation
Medium-voltage and standard-voltage operation
̶




VCC = 2.5V to 5.5V
Extended temperature range -40C to 125C
5MHz clock rate
32-byte page mode
Block write protection
̶



Protect 1/4, 1/2, or entire array
Write Protect (WP) pin and Write Disable instructions for both hardware and
software data protection
Self-timed write cycle (5ms max)
High reliability
̶
̶

Endurance: one million write cycles
Data retention: 100 years
8-lead JEDEC SOIC and 8-lead TSSOP packages
Description
The Atmel® AT25080B/160B/320B/640B provides 8192/16384/32768/65536 bits
of Serial Electrically-Erasable Programmable Read-Only Memory (EEPROM)
organized as 1024/2048/4096/8192 words of eight bits each. The device is
optimized for use in many automotive applications where low-power and
low-voltage operation are essential. AT25080B/160B/320B/640B is available in
space-saving 8-lead JEDEC SOIC and 8-lead TSSOP packages.
AT25080B/160B/320B/640B is enabled through the Chip Select pin (CS) and
accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data
Output (SO), and Serial Clock (SCK). All programming cycles are completely
self-timed, and no separate erase cycle is required before write.
Block write protection is enabled by programming the status register with one of
four blocks of write protection. Separate program enable and program disable
instructions are provided for additional data protection. Hardware data protection
is provided via the WP pin to protect against inadvertent write attempts to the
status register. The HOLD pin may be used to suspend any serial communication
without resetting the serial sequence.
Atmel-8803D-SEEPROM-AT25080B-160B-320B-640B-Auto-Datasheet_062015
1.
Pin Descriptions and Pinouts
Table 1-1.
Pin Name
2.
Pin Configurations
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
8-lead SOIC
8-lead TSSOP
(Top View)
(Top View)
CS
1
8
VCC
SO
2
7
HOLD
WP
3
6
SCK
GND
4
5
SI
Note:
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
Drawings are not to scale.
Absolute Maximum Ratings*
Operating Temperature  40C to +125C
Storage Temperature 65C to +150C
Voltage on any pin
with respect to ground 1.0V to +7.0V
Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . .5.0mA
2
CS
SO
WP
GND
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
AT25080B/160B/320B/640B Automotive [DATASHEET]
Atmel-8803D-SEEPROM-AT25080B-160B-320B-640B-Auto-Datasheet_062015
3.
Block Diagram
Figure 3-1.
Block Diagram
VCC
Status
Register
GND
Memory Array
1024/2048/
4096/8192 x 8
Address
Decoder
Data
Register
Output
Buffer
SI
CS
Mode
Decode
Logic
WP
SCK
Clock
Generator
SO
HOLD
AT25080B/160B/320B/640B Automotive [DATASHEET]
Atmel-8803D-SEEPROM-AT25080B-160B-320B-640B-Auto-Datasheet_062015
3
4.
Serial Interface Description
Master: The device that generates the serial clock.
Slave: Because the Serial Clock pin (SCK) is always an input, AT25080B/160B/320B/640B always operates as
a slave.
Transmitter/Receiver: AT25080B/160B/320B/640B has separate pins designated for data transmission (SO)
and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
Serial Opcode: After the device is selected with CS going low, the first byte will be received. This byte contains
the opcode that defines the operations to be performed.
Invalid Opcode: If an invalid opcode is received, no data will be shifted into AT25080B/160B/320B/640B, and
the Serial Output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again.
This will reinitialize the serial communication.
Chip Select: AT25080B/160B/320B/640B is selected when the CS pin is low. When the device is not selected,
data will not be accepted via the SI pin, and the Serial Output pin (SO) will remain in a high impedance state.
Hold: The HOLD pin is used in conjunction with the CS pin to select AT25080B/160B/320B/640B. When the
device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication
with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while
the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low
(SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high
impedance state.
Write Protect: The Write Protect pin (WP) will allow normal read/write operations when held high. When the
WP pin is brought low and WPEN bit is one, all write operations to the status register are inhibited. WP going
low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is
blocked when the WPEN bit in the status register is zero. This will allow the user to install
AT25080B/160B/320B/640B in a system with the WP pin tied to ground and still be able to write to the status
register. All WP pin functions are enabled when the WPEN bit is set to one.
4
AT25080B/160B/320B/640B Automotive [DATASHEET]
Atmel-8803D-SEEPROM-AT25080B-160B-320B-640B-Auto-Datasheet_062015
5.
Memory Organization
5.1
Pin Capacitance
Table 5-1.
Pin Capacitance(1)
Applicable at these conditions, unless otherwise noted. TA = 25C, f = 1.0MHz, VCC = +5.0V.
Symbol
Test Conditions
COUT
CIN
Note:
5.2
1.
Max
Units
Conditions
Output Capacitance (SO)
8
pF
VOUT = 0V
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
VIN = 0V
This parameter is characterized and is not 100% tested.
DC Characteristics
Table 5-2.
DC Characteristics
Applicable over recommended operating range from: TA = 40C to +125C, VCC = +2.5V to +5.5V.
Symbol
Parameter
VCC1
Supply Voltage
ICC1
Supply Current
ICC2
Supply Current
ICC3
Supply Current
ISB1
Standby Current
VCC = 2.5V, CS = VCC
ISB2
Standby Current
VCC = 5.0V, CS = VCC
IIL
Input Leakage
VIN = 0V to VCC
3.0
IOL
Output Leakage
VIN = 0V to VCC
3.0
3.0
μA
Input Low-voltage
0.6
VCC x 0.3
V
VIH
Input High-voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low-voltage
0.4
V
VOH1
Output High-voltage
VIL(1)
(1)
Note:
1.
Test Condition
Min
Typ
Max
Units
5.5
V
6.0
mA
3.0
mA
7.0
mA
0.2
10.0
μA
2.0
13.0
μA
2.5
VCC = 5.0V at 5MHz,
SO = Open, Read
VCC = 5.0V at 1MHz
VCC = 5.0V at 5MHz,
SO = Open, Read, Write
2.5V  VCC  5.5V
IOL = 3.0mA
IOH = 1.6mA
μA
VCC  0.8
V
VIL min and VIH max are reference only and are not tested.
AT25080B/160B/320B/640B Automotive [DATASHEET]
Atmel-8803D-SEEPROM-AT25080B-160B-320B-640B-Auto-Datasheet_062015
5
5.3
AC Characteristics
Table 5-3.
AC Characteristics
Applicable over recommended operating range from TA = 40C to +125C, VCC = As Specified,
CL = 1 TTL Gate and 100pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
fSCK
SCK Clock Frequency
2.5–5.5
0
5.0
MHz
tRI
Input Rise Time
2.5–5.5
2
μs
tFI
Input Fall Time
2.5–5.5
2
μs
tWH
SCK High Time
2.5–5.5
40
ns
tWL
SCK Low Time
2.5–5.5
40
ns
tCS
CS High Time
2.5–5.5
80
ns
tCSS
CS Setup Time
2.5–5.5
80
ns
tCSH
CS Hold Time
2.5–5.5
80
ns
tSU
Data In Setup Time
2.5–5.5
5
ns
tH
Data In Hold Time
2.5–5.5
20
ns
tHD
Hold Setup Time
2.5–5.5
40
ns
tCD
Hold Hold Time
2.5–5.5
40
ns
tV
Output Valid
2.5–5.5
0
tHO
Output Hold Time
2.5–5.5
0
tLZ
Hold to Output Low Z
2.5–5.5
0
tHZ
Hold to Output High Z
tDIS
ns
ns
40
ns
2.5–5.5
80
ns
Output Disable Time
2.5–5.5
80
ns
tWC
Write Cycle Time
2.5–5.5
5
ms
Endurance(1)
5.0V, 25°C, Page Mode
Note:
6
40
1.
This parameter is characterized and is not 100% tested.
AT25080B/160B/320B/640B Automotive [DATASHEET]
Atmel-8803D-SEEPROM-AT25080B-160B-320B-640B-Auto-Datasheet_062015
1M
Write Cycles
Figure 5-1.
SPI Serial Interface
Master:
Microcontroller
Slave:
AT25080B/160B/320B/640B
Data Out (MOSI)
Data In (MISO)
Serial Clock (SPI CK)
SS0
SS1
SS2
SS3
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
AT25080B/160B/320B/640B Automotive [DATASHEET]
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7
6.
Functional Description
AT25080B/160B/320B/640B is designed to interface directly with the synchronous Serial Peripheral Interface
(SPI) of the 6805 and 68HC11 series of microcontrollers.
AT25080B/160B/320B/640B utilizes an 8-bit instruction register. The list of instructions and their operation
codes are contained in the below table. All instructions, addresses, and data are transferred with the MSB first
and start with a high-to-low CS transition.
Table 6-1.
Instruction Set for the Atmel AT25080B/160B/320B/640B
Instruction Name
Instruction Format
Operation
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
WRSR
0000 X001
Write Status Register
READ
0000 X011
Read Data from Memory Array
WRITE
0000 X010
Write Data to Memory Array
Write Enable (WREN): The device will power up in the write disable state when VCC is applied. All programming
instructions must therefore be preceded by a Write Enable instruction.
Write Disable (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables
all programming modes. The WRDI instruction is independent of the status of the WP pin.
Read Status Register (RDSR): The Read Status Register instruction provides access to the status register.
The Ready/Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly,
the block write protection bits indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 6-2.
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
Table 6-3.
Bit
Bit 0 (RDY)
Bit 1 (WEN)
Read Status Register Bit Definition
Definition
Bit 0 = 0 (RDY) indicates the device is ready.
Bit 0 = 1 indicates the write cycle is in progress.
Bit 1= 0 indicates the device is not write-enabled.
Bit 1 = 1 indicates the device is write-enabled.
Bit 2 (BP0)
See Table 6-4 on page 9.
Bit 3 (BP1)
See Table 6-4 on page 9.
Bits 4 6 are zeros when device is not in an internal write cycle.
Bit 7 (WPEN)
See Table 6-5 on page 9.
Bits 0  7 are ones during an internal write cycle.
8
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Write Status Register (WRSR): The WRSR instruction allows the user to select one of four levels of protection.
AT25080B/160B/320B/640B is divided into four array segments; one-quarter, one-half, or all of the memory
segments can be protected. Any of the data within any selected segment will therefore be read-only. The block
write protection levels and corresponding status register control bits are shown in the below table.
Bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular
memory cells (e.g., WREN, tWC, RDSR).
Table 6-4.
Block Write Protect Bits
Status
Register Bits
Array Addresses Protected
Level
BP1
BP0
AT25080B
AT25160B
AT25320B
AT25640B
0
0
0
None
None
None
None
1 (1/4)
0
1
0300  03FF
0600 07FF
0C00 0FFF
1800 1FFF
2 (1/2)
1
0
0200 03FF
0400 07FF
0800 0FFF
1000 1FFF
3 (All)
1
1
0000  03FF
0000 07FF
0000 0FFF
0000 1FFF
The WRSR instruction also allows the user to enable or disable the Write Protect (WP) pin through the use of
the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the
WPEN bit is one. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is zero.
When the device is hardware write protected, writes to the status register, including the block protect bits and
the WPEN bit, and the
block-protected sections in the memory array are disabled. Writes are only allowed to sections of the memory
that are not block-protected.
Note:
When the WPEN bit is hardware write protected, it cannot be changed back to zero as long as the WP
pin is held low.
Table 6-5.
WPEN Operation
WPEN
WP
WEN
Protected
Blocks
Unprotected
Blocks
Status
Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writeable
Writeable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writeable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writeable
Writeable
Read Sequence (Read): Reading AT25080B/160B/320B/640B via the Serial Output (SO) pin requires the
following sequence. After the CS line is pulled low to select a device, the read opcode is transmitted via the SI
line followed by the byte address to be read (A15A0, see Table 6-6). Upon completion, any data on the SI line
will be ignored. The data (D7D0) at the specified address is then shifted out onto the SO line. If only one byte
is to be read, the CS line should be driven high after the data comes out. The read sequence can be continued
since the byte address is automatically incremented and data will continue to be shifted out. When the highest
address is reached, the address counter will roll-over to the lowest address, allowing the entire memory to be
read in one continuous read cycle.
AT25080B/160B/320B/640B Automotive [DATASHEET]
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9
Write Sequence (Write): In order to program AT25080B/160B/320B/640B, two separate instructions must be
executed. First, the device must be write enabled via the WREN instruction. Then a Write instruction may be
executed. Also, the address of the memory location(s) to be programmed must be outside the protected
address field location selected by the block write protection level. During an internal write cycle, all commands
will be ignored except the RDSR instruction.
A Write instruction requires the following sequence. After the CS line is pulled low to select the device, the Write
opcode is transmitted via the SI line followed by the byte address (A15A0) and the data (D7 – D0) to be
programmed (See Table 6-6). Programming will start after the CS pin is brought high. The low-to-high transition
of the CS pin must occur during the SCK low-time immediately after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR)
instruction. If Bit 0 = one, the write cycle is still in progress. If Bit 0 = zero, the write cycle has ended. Only the
RDSR instruction is enabled during the write programming cycle.
AT25080B/160B/320B/640B is capable of a 32-byte page write operation. After each byte of data is received,
the five low-order address bits are internally incremented by one; the high-order bits of the address will remain
constant. If more than 32 bytes of data are transmitted, the address counter will roll-over and the previously
written data will be overwritten. AT25080B/160B/320B/640B is automatically returned to the write disable state
at the completion of a write cycle.
Note:
If the device is not Write Enabled (WREN), the device will ignore the Write instruction and will return to
the standby state, when CS is brought high. A new CS falling edge is required to reinitiate the serial
communication.
Table 6-6.
10
Address Key
Address
AT25080B
AT25160B
AT25320B
AT25640B
AN
A9–A0
A10–A0
A11–A0
A12–A0
Don’t Care Bits
A15–A10
A15–A11
A15–A12
A15–A13
AT25080B/160B/320B/640B Automotive [DATASHEET]
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7.
Timing Diagrams
Figure 7-1.
Synchronous Data Timing (for Mode 0)
t CS
VIH
CS
VIL
t CSH
t CSS
VIH
t WH
SCK
t WL
VIL
tH
t SU
SI
VIH
VALID IN
VIL
tV
VOH
SO
t HO
t DIS
HI-Z
HI-Z
VOL
Figure 7-2.
WREN Timing
CS
SCK
WREN Opcode
SI
HI-Z
SO
Figure 7-3.
WRDI Timing
CS
SCK
SI
SO
WRDI Opcode
HI-Z
AT25080B/160B/320B/640B Automotive [DATASHEET]
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11
Figure 7-4.
RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
7
6
11
12
13
14
15
4
3
2
1
0
12
13
14
15
2
1
0
SCK
Instruction
SI
Data Out
High-impedance
SO
5
MSB
Figure 7-5.
WRSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
7
6
5
4
SCK
Data In
SI
SO
12
Instruction
High-impedance
AT25080B/160B/320B/640B Automotive [DATASHEET]
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3
Figure 7-6.
Read Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
Byte Address
SI
SO
15 14 13 ...
Instruction
3
2
1
0
Data Out
High-impedance
7
6
5
4
3
2
1
0
MSB
Figure 7-7.
Write Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
Byte Address
SI
SO
Instruction
15 14 13 ...
3
Data In
2
1
0
7
6
5
4
3
2
1
0
High-impedance
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13
Table 7-1.
HOLD Timing
CS
SCK
HOLD
SO
7.1
Power Recommendation
The device internal POR (Power-On Reset) threshold is just below the minimum device operating voltage.
Power shall rise monotonically from 0.0Vdc to full VCC in less than 1ms. Hold at full VCC for at least 100μs before
the first operation. Power shall drop from full VCC to 0.0Vdc in less than 1ms. Power shall remain off (0.0Vdc) for
0.03ms minimum. Power dropping to a non-zero level and then slowly going to zero is not recommended, but if
unavoidable the VCC level supplied to the part must remain below 0.5V for at least 0.1ms to ensure a proper
reset.
Please consult Atmel if your power conditions do not meet the above recommendations.
14
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8.
Ordering Information
8.1
Ordering Code Detail
AT 2 5 0 8 0 B - S S P D x x - T
Atmel Designator
Shipping Carrier Option
T = Tape and Reel
Product Family
25 = SPI Automotive
Serial EEPROM
Product Variation
GV= See ordering code table for
valid options.
Operating Voltage
Device Density
080 = 8 kilobit
160 = 16 kilobit
320 = 32 kilobit
640 = 64 kilobit
Device Revision
D = 1.7V to 5.5V
Package Device Grade or
Wafer/Die Thickness
P = Lead-free / Halogen-free
Automotive Temperature Range
(-40°C to +125°C)
Package Option
SS = JEDEC SOIC
X = TSSOP
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8.2
Ordering Code Information
Delivery Information
Atmel Ordering Code
AT25080B-SSPDGV-T
AT25080B-XPDGV-T
AT25160B-SSPDGV-T
AT25160B-XPDGV-T
AT25320B-SSPDGV-T
AT25320B-XPDGV-T
AT25640B-SSPDGV-T
AT25640B-XPDGV-T
8.3
Lead Finish
Package
Form
8S1
NiPdAu
(Lead-free/Halogen-free)
8X
Tape and Reel
8S1
NiPdAu
(Lead-free/Halogen-free)
8X
(Lead-free/Halogen-free)
8X
(Lead-free/Halogen-free)
8X
4,000 per Reel
Automotive
Temperature
40C to 125C)
5,000 per Reel
5,000 per Reel
4,000 per Reel
Tape and Reel
8S1
NiPdAu
Operation Range
4,000 per Reel
Tape and Reel
8S1
NiPdAu
Quantity
5,000 per Reel
4,000 per Reel
Tape and Reel
5,000 per Reel
Automotive
Temperature
40C to 125C)
Automotive
Temperature
40C to 125C)
Automotive
Temperature
40C to 125C)
Legacy Ordering Code Information (Not Recommended for New Designs, NRND)
Delivery Information
Atmel Ordering Code
AT25080B-SSPD-T
AT25080B-XPD-T
AT25160B-SSPD-T
AT25160B-XPD-T
AT25320B-SSPD-T
AT25320B-XPD-T
AT25640B-SSPD-T
AT25640B-XPD-T
Lead Finish
Package
NiPdAu
(Lead-free/Halogen-free)
NiPdAu
(Lead-free/Halogen-free)
NiPdAu
(Lead-free/Halogen-free)
NiPdAu
(Lead-free/Halogen-free)
Form
8S1
8X
Tape and Reel
8S1
8X
8S1
8-lead, 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X
8-lead 4.4mm body, Plastic Thin Shrink Small Outline (TSSOP)
AT25080B/160B/320B/640B Automotive [DATASHEET]
Atmel-8803D-SEEPROM-AT25080B-160B-320B-640B-Auto-Datasheet_062015
Automotive
Temperature
40C to 125C)
5,000 per Reel
5,000 per Reel
5,000 per Reel
4,000 per Reel
Tape and Reel
Package Type
16
4,000 per Reel
4,000 per Reel
Tape and Reel
8S1
8X
Operation Range
4,000 per Reel
Tape and Reel
8S1
8X
Quantity
5,000 per Reel
Automotive
Temperature
40C to 125C)
Automotive
Temperature
40C to 125C)
Automotive
Temperature
40C to 125C)
9.
Part Markings
AT25080B, AT25160B, AT25320B & AT25640B:
Automotive Package Marking Information
8-lead TSSOP
8-lead SOIC
ATPYWW
#####@
AAAAAAA
ATMLPYWW
##### @
AAAAAAAA
Note 1:
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT25080B, GV Product Variation
Truncation Code #####:
58BGV
AT25160B, GV Product Variation
Truncation Code #####:
5ABGV
AT25320B, GV Product Variation
Truncation Code #####:
5BBGV
AT25640B, GV Product Variation
Truncation Code #####:
5CBGV
AT25080B, Not Recommended for New Design
Truncation Code ####:
58BD
AT25160B, Not Recommended for New Design
Truncation Code ####:
5ABD
AT25320B, Not Recommended for New Design
Truncation Code ####:
5BBD
AT25640B, Not Recommended for New Design
Truncation Code ####:
5CBD
Date Codes
Y = Year
5: 2015
6: 2016
7: 2017
8: 2018
% = Voltages
9: 2019
0: 2020
1: 2021
2: 2022
M = Month
A: January
B: February
...
L: December
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
Country of Assembly
Lot Number
@ = Country of Assembly
AAA...A = Atmel Wafer Lot Number
Trace Code
D: 2.5V minimum
Grade/Lead Finish Material
P: Automotive/NiPdAu
Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code)
Example: AA, AB.... YZ, ZZ
AT: Atmel
ATM: Atmel
ATML: Atmel
6/25/15
TITLE
Package Mark Contact:
[email protected]
25080-160-320-640BAM, AT25080B, AT25160B, AT25320B
& AT25640B Automotive Package Marking Information
DRAWING NO.
REV.
25080-160-320-640BAM
B
AT25080B/160B/320B/640B Automotive [DATASHEET]
Atmel-8803D-SEEPROM-AT25080B-160B-320B-640B-Auto-Datasheet_062015
17
10.
Packaging Information
10.1
8S1 — 8-lead JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
MIN
NOM
MAX
–
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
SYMBOL
A
D
4.90 BSC
E
6.00 BSC
E1
3.90 BSC
e
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
NOTE
3/6/2015
Package Drawing Contact:
[email protected]
18
TITLE
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
AT25080B/160B/320B/640B Automotive [DATASHEET]
Atmel-8803D-SEEPROM-AT25080B-160B-320B-640B-Auto-Datasheet_062015
GPC
SWB
DRAWING NO.
REV.
8S1
H
10.2
8X — 8-lead TSSOP
C
1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
A
b
A1
e
COMMON DIMENSIONS
(Unit of Measure = mm)
A2
D
SYMBOL
Side View
Notes:
1. This drawing is for general information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
MIN
NOM
MAX
A
-
-
1.20
A1
0.05
-
0.15
NOTE
A2
0.80
1.00
1.05
D
2.90
3.00
3.10
2, 5
E
6.40 BSC
E1
4.30
4.40
4.50
3, 5
b
0.19
0.25
0.30
4
e
L
0.65 BSC
0.45
L1
C
0.60
0.75
1.00 REF
0.09
-
0.20
2/27/14
TITLE
Package Drawing Contact:
[email protected]
GPC
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
TNR
DRAWING NO.
8X
AT25080B/160B/320B/640B Automotive [DATASHEET]
Atmel-8803D-SEEPROM-AT25080B-160B-320B-640B-Auto-Datasheet_062015
REV.
E
19
11.
Revision History
Doc. Rev.
Date
Comments
Updated ordering codes tables and Section 7.1
8803D
06/2015
Updated part marking information.
Updated 8S1 and 8X package drawings.
Updated footers and reorganized the document.
20
8803C
12/2012
8803B
08/2012
8803A
02/2012
Condensed and updated ordering code table.
Removed preliminary status.
Updated Atmel logos and disclaimer/copy page.
Initial document release.
AT25080B/160B/320B/640B Automotive [DATASHEET]
Atmel-8803D-SEEPROM-AT25080B-160B-320B-640B-Auto-Datasheet_062015
XXXXXX
Atmel Corporation
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T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
|
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© 2015 Atmel Corporation. / Rev.: Atmel-8803D-SEEPROM-AT25080B-160B-320B-640B-Auto-Datasheet_062015.
Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and
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